High-efficiency LLC half-bridge resonant switch controller circuit

Abstract

This invention relates to a high-efficiency LLC half-bridge resonant switch controller circuit, comprising a current detection circuit, an oscillation clock generation circuit, a current loss tracking detection circuit, a comprehensive control logic circuit, an input buffer circuit, a feedback voltage detection circuit, a programmable dead time generation circuit, a level shifting circuit, a delay compensation circuit, an over-temperature protection circuit (OTP), an over-current protection circuit (OCP), and a high / low-side output drive circuit. This invention employs dead-time adaptive adjustment technology to improve the efficiency of the LLC half-bridge resonant controller. On one hand, it is controlled by the reference clock (OSC) to set different dead times; on the other hand, it can also respond to external changes in soft-switching losses by adjusting the dead time, thereby minimizing switching losses. This invention also employs load condition mode switching technology, dividing the operating mode into heavy-load and light-load modes based on the state of the voltage signal FB output by the LLC half-bridge resonant converter power system, thereby improving efficiency under light load conditions.

Description

Technical Field

[0001] This invention relates to a high-efficiency LLC half-bridge resonant switch controller circuit for use in LLC half-bridge resonant converter power supply systems. Background Technology

[0002] For a long time, limited by production capacity and costs, the application of lithium batteries in power storage has not been widespread. However, compared to traditional lead-acid batteries, lithium batteries have many advantages, such as high energy density, long cycle life, and no pollution. Due to the high energy density of lithium batteries, their volume is only one-fifth that of lead-acid batteries when storing the same amount of energy. The large-scale application of lithium batteries in various power scenarios, from small to large, remains a future trend, requiring corresponding adjustments to the power supplies used in equipment. Miniaturized and lightweight charging devices are widely favored. With breakthroughs in materials physics and power device technology, many power electronics theories have been realized and developed. Switching power supplies, with their significant advantages of light weight, small size, and high energy efficiency, hold a considerable market share in the lithium battery charger field. Among them, resonant converters with soft-switching characteristics are conducive to further promoting the high-frequency and miniaturization of power supply equipment. Among the many types of resonant soft-switching converters, LLC resonant converters, which simultaneously possess strong no-load operating capability and the ability to reflect the load weight with resonant current, have been widely used.

[0003] A typical LLC half-bridge resonant converter topology is shown below. Figure 1As shown, Vin is a DC voltage source; two MOSFET switches Q1 and Q2 form a half-bridge switching network, DQ1 and DQ2 are the body diodes of switches Q1 and Q2 respectively, and CQ1 and CQ2 are the parasitic capacitances of switches Q1 and Q2 respectively; the half-bridge driver outputs two switching signals with a duty cycle of 50% and a frequency of f, and the two signals are 180° out of phase, controlling Q1 and Q2 to conduct alternately; Cr is a resonant capacitor, Lm is a magnetizing inductor, and Lr is a resonant inductor, and the three components Cr, Lm, and Lr form a resonant cavity; the primary and secondary turns ratio of the transformer is N1:; D1, D2, and the output capacitor Co form a rectifier and filter circuit; the load is a lithium battery pack. In the above system, the drive signals for Q1 and Q2 are provided by an LLC half-bridge resonant controller. The dead time between the drive signals for Q1 and Q2 must be set properly to create conditions for zero-voltage turn-on. If the dead time is not set properly, the MOSFETs will not be able to achieve ZVS turn-on. If the dead time is set too small, the MOSFET will be hard-turned on before the junction capacitor voltage has discharged to 0V. If the dead time is set too large, the junction capacitor voltage may have discharged to 0V, but due to the excessive dead time, the junction capacitor will start to charge in reverse. Turning on the MOSFET at this point will also result in a hard turn-on, increasing losses. It can be seen that, with a fixed frequency, the choice of dead time directly determines the soft-switching range of the converter, thus affecting the voltage stress on the MOSFET and the overall efficiency of the converter.

[0004] Figure 2 This is a detailed topology diagram of a typical LLC half-bridge resonant converter system. In this resonant converter system, the control signals for the main switches MOSFETs S1~S2 are HG and LG, generated by the LLC resonant controller chip 200 based on the states of the converter output voltage feedback signal FB, the output current detection signal CS, and the frequency control signal FSET. The current output SW node of the resonant controller chip 200 is connected to drive the LLC resonant cavity. In traditional controllers, the dead time between the MOSFET control signals HG and LG is usually set to a fixed value, and the output capacitor charging and discharging time and dead time are estimated based on the output capacitor data in the MOSFET's technical specifications. When load conditions and temperature change, the aforementioned dead time will deviate, potentially affecting the realization of zero-voltage turn-on and ultimately reducing the system's conversion efficiency. Therefore, providing a resonant controller circuit that can adaptively adjust the dead time is of significant practical importance for improving the efficiency of LLC resonant control chips and resonant switch controllers. Summary of the Invention

[0005] Based on existing technology, this invention provides a high-efficiency LLC half-bridge resonant switch controller circuit, which improves the overall efficiency and stability of the controller.

[0006] The high-efficiency LLC half-bridge resonant switch controller circuit proposed in this invention includes: a current detection circuit, an oscillation clock generation circuit, a current loss tracking detection circuit, a comprehensive control logic circuit, an input buffer circuit, a feedback voltage detection circuit, a programmable dead time generation circuit, a level shifting circuit, a delay compensation circuit, an over-temperature protection circuit, an over-current protection circuit, a high-side output drive circuit, and a low-side output drive circuit.

[0007] The current detection circuit is used to detect the current signal CS output by the LLC half-bridge resonant converter power system. Under the control of the current sampling control clock Ckcs and the dead time control clock Ckdt, it generates a current loss detection signal Vcs, a CS sampling signal Vcsin, and an output current detection signal Ics. The current loss detection signal Vcs is connected to the input terminal of the current loss follower detection circuit, the CS sampling signal Vcsin is connected to the input terminal of the overcurrent protection circuit, and the output current detection signal Ics is connected to the input terminal of the oscillation clock generation circuit. The other input terminal of the oscillation clock generation circuit is connected to the input frequency control signal Ifset generated by the input buffer circuit. The oscillation clock generation circuit determines the frequency based on the output current. The detection signal Ics and the input frequency control signal Ifset generate the reference clock OSC, the current sampling control clock Ckcs, the current follower control clock Ckcom, and the dead time control clock Ckdt. The reference clock OSC is connected to the integrated control logic circuit. The current sampling control clock Ckcs and the dead time control clock Ckdt are connected to the current detection circuit and the current loss follower detection circuit. The current follower control clock Ckcom is connected to the current loss follower detection circuit. Under the control of the current sampling control clock Ckcs, the current follower control clock Ckcom, and the dead time control clock Ckdt, the current loss follower detection circuit generates the current loss quantization signal D based on the current loss detection signal Vcs. The input control circuit is connected to the input terminal of the integrated control logic circuit. The input buffer circuit generates the input frequency control signal Ifset based on the external frequency control signal FSET. The feedback voltage detection circuit is used to detect the voltage signal FB output by the power system of the LLC half-bridge resonant converter and generates the output voltage detection signal Dfb, which is connected to the input terminal of the integrated control logic circuit. The overcurrent protection circuit generates the overcurrent protection signal OCP based on the CS sampling signal Vcsin. The overtemperature protection circuit monitors the chip temperature in real time and generates the overtemperature protection signal OTP. Both the overcurrent protection signal OCP and the overtemperature protection signal OTP are also connected to the input terminal of the integrated control logic circuit. The integrated control logic circuit is based on the reference clock OSC and the current consumption. The status output power switch control signal Din and the N-bit dead time control code Dt(N) of the power switch control signal Dcs, voltage detection signal Dfb, overcurrent protection signal OCP, and overtemperature protection signal OTP are connected to a programmable dead time generation circuit, where N is any positive integer. The programmable dead time generation circuit generates a high-side output switch control signal Dho and a low-side output switch control signal Dlo with dead time protection based on the power switch control signal Din and the dead time control code Dt(N). The high-side output switch control signal Dho enters a level shifting circuit to generate a high-side output signal Dhho, which then passes through a high-side output drive circuit to generate a high-side gate drive signal HG, a floating power supply BST, and a floating ground SW.The low-side output switch control signal Dlo enters the delay compensation circuit to generate the low-side output signal Dllo, which then passes through the low-side output drive circuit to generate the low-side gate drive signal LG.

[0008] When the circuit starts working, the oscillation clock generation circuit first generates a set of default initial reference clock OSC, current sampling control clock Ckcs, current follower control clock Ckcom, and dead time control clock Ckdt; then the integrated control logic circuit first generates a default power switch control signal Din and dead time control code Dt(N); then the programmable dead time generation circuit generates a high-side output switch control signal Dho and a low-side output switch control signal Dlo with dead time protection; the high-side output switch control signal Dho enters the level shift circuit to generate the high-side output signal Dhho, and then passes through the high-side output drive circuit to generate the high-side gate drive signal HG and the floating power supply BST and floating ground SW for the LLC half-bridge resonant converter power supply system; the low-side output switch control signal Dlo enters the delay compensation circuit to generate the low-side output signal Dllo, and then passes through the low-side output drive circuit to generate the low-side gate drive signal LG for the LLC half-bridge resonant converter power supply system; the LLC half-bridge resonant converter power supply system... The current signal CS output by the power supply system of the bridge resonant converter will correspondingly change its characteristics. The change in the CS signal will be detected by the current detection circuit and the current loss follower detection circuit, and will generate the output current detection signal Ics and the current loss quantization signal Dcs, respectively. At the same time, the voltage signal FB output by the power supply system of the LLC half-bridge resonant converter will be detected by the feedback voltage detection circuit and will generate the output voltage detection signal Dfb. The input buffer circuit will generate the input frequency control signal Ifset according to the external frequency control signal FSET. The output current detection signal Ics and the input frequency control signal Ifset enter the oscillation clock generation circuit to adjust the clock frequencies of the reference clock OSC, the current sampling control clock Ckcs, the current follower control clock Ckcom, and the dead time control clock Ckdt. The current loss quantization signal Dcs is used to adjust the dead time of the high-side output switch control signal Dho and the low-side output switch control signal Dlo, which are generated by the programmable dead time generation circuit with dead time protection.

[0009] The states of the voltage detection signal Dfb, overcurrent protection signal OCP, and overtemperature protection signal OTP control the operating mode of the overall LLC half-bridge resonant switch controller circuit and adjust the frequency characteristics of the power switch control signal Din.

[0010] Specifically, the current detection circuit includes: a Dt sampling switch, a Cs sampling switch, a current compensation buffer, and a voltage buffer; the Dt sampling switch samples the current signal CS under the control of the dead-time control clock Ckdt to obtain the sampling signal Vdtin; the Cs sampling switch samples the current signal CS under the control of the current sampling control clock Ckcs to obtain the sampling signal Vcsin; the sampling signal Vdtin is connected to the voltage buffer, which isolates and buffers the sampling signal Vdtin and outputs the current loss detection signal Vcs; the sampling signal Vcsin is connected to the current compensation buffer on one hand and to the overcurrent protection circuit on the other hand; the current compensation buffer generates the output current detection signal Ics based on the reference voltage Vref and the sampling signal Vcsin; the Dt sampling switch and the Cs sampling switch are the same sampling switches, and the control clocks Ckdt and Ckcs of the Dt sampling switch and the Cs sampling switch are clock signals whose sampling effective times do not overlap, that is, the Dt sampling switch and the Cs sampling switch cannot sample simultaneously at any time.

[0011] Specifically, the current compensation buffer includes PMOS transistors M701, M702, M704, M705, M706, M707, M708, NMOS transistors M709, M710, M711, M712, and M713, resistors R71 and R72, and capacitors C71 and C72.

[0012] Specifically, the gate of PMOS transistor M705 is connected to the reference voltage Vref; the gates of PMOS transistors M701 and M702 are connected to the bias voltage Vbc71; the gates of PMOS transistors M707 and M708 are connected to the bias voltage Vbc72; the gates of NMOS transistors M710 and M709 are connected to the bias voltage Vbc73; the drain of PMOS transistor M701 is connected to the source of PMOS transistors M705 and M706; the drain of PMOS transistor M705 is connected to the source of PMOS transistor M707; the drain of PMOS transistor M707 is connected to the drain of NMOS transistor M710; the source of NMOS transistor M710 is connected to the drain of NMOS transistor M711, the gate of NMOS transistor M711, and the gate of NMOS transistor M712; the drain of PMOS transistor M706 is connected to the source of PMOS transistor M708; and the drain of PMOS transistor M708... The drain of NMOS transistor M709 is connected to the drain of NMOS transistor M713, the gate of NMOS transistor M713, and the upper end of resistor R72. The lower end of resistor R72 is connected to the upper end of capacitor C72. The source of NMOS transistor M709 is connected to the drain of NMOS transistor M712. The drain of PMOS transistor M702 is connected to the drain of NMOS transistor M713, the right end of capacitor C71, and the gate of PMOS transistor M704. The gate of NMOS transistor M706 is connected to the left end of capacitor C71 and the right end of resistor R71. The left end of resistor R71 is connected to the sampling signal Vcsin. The drain of PMOS transistor M704 serves as the output terminal of the output current detection signal Ics. The sources of PMOS transistors M701, M702, and M704 are all connected to the power supply voltage VCC. The sources of NMOS transistors M711, M712, and M713, and the lower end of capacitor C72 are all connected to the ground voltage GND.

[0013] Specifically, the current loss tracking detection circuit includes: a sampling switch, a hold circuit, and a high-precision comparator; the control clock input terminal of the sampling switch is connected to the current sampling control clock CKcs, and the input current loss detection signal Vcs is connected to the analog signal input terminal of the sampling switch; the first analog signal output terminal of the sampling switch is connected to the positive input terminal of the high-precision comparator, and the connection is controlled by the current tracking control clock CKcom; the second analog signal output terminal of the sampling switch is connected to the signal input terminal of the hold circuit, and the connection is controlled by the dead time control clock Ckdt; the analog signal output terminal of the hold circuit is connected to the negative input terminal of the high-precision comparator, and the connection is controlled by the current tracking control clock CKcom; the current sampling control clock Ckcs, the current tracking control clock Ckcom, and the dead time control clock Ckdt are three-phase non-overlapping clocks; the data output of the quantization output terminal of the high-precision comparator is output to the integrated control logic circuit.

[0014] The operation of the above current loss tracking detection circuit is as follows: In phase Ckcs, the sampling switch samples the input current loss detection signal Vcs. The voltage obtained during the Kth sampling is... V cs (K); Ckcom phase, high-precision comparator samples the voltage from the switch. V cs (K) is the voltage held by the holding circuit in the previous clock cycle. V cs The data D(K) output from the quantization output terminal of the high-precision comparator is the current loss quantization signal Dcs, which is compared with (K-1). When the output D(K) is 1, it indicates that... V cs The voltage increases, and the output D(K) is 0, then the opposite occurs; Ckdt phase, V cs (K) will enter the holding circuit for holding.

[0015] Specifically, the integrated control logic circuit includes: a counter, error handling logic, waveform data generation circuit, input serial register, serial / parallel conversion circuit, buffer, N-bit buffer, control logic circuit, and control register; the counter generates a working control clock Ck_ctrl based on the reference clock OSC, and the working control clock Ck_ctrl is simultaneously connected to the control clock input terminals of the control logic circuit, input serial register, serial / parallel conversion circuit, and control register; the control logic circuit connects the working control clock Ck_ctrl, voltage detection signal Dfb, and error signal ERR, and generates a chip status control signal SET and a chip mode control signal ON / OFF based on the state of these signals. The chip status control signal SET is connected to the control register, and the chip mode control signal ON / OFF is connected to the waveform data generation circuit; the control register outputs control signal Ctrl and control signal Ctrl1. Control signal Ctrl is connected to the control signal input terminals of the error handling logic, waveform data generation circuit, and buffer, and control signal Ctrl1 is connected to the input serial register, The serial / parallel conversion circuit and the N-bit buffer are connected to the control signal input terminals. The error handling logic is connected to the overcurrent protection signal OCP and the overtemperature protection signal OTP. Under the control of the control signal Ctrl, the error signal ERR is generated based on the overcurrent protection signal OCP and the overtemperature protection signal OTP. The waveform data generation circuit, under the control of the control signal Ctrl, generates the power switch control pre-output signal Din_pre based on the external input reference clock OSC and the chip mode control signal ON / OFF. This pre-output signal is connected to the buffer, which generates the power switch control signal Din. The input serial register, under the control of the working control clock Ck_ctrl and the control signal Ctrl1, receives the current loss quantization signal Dcs in chronological order and outputs it to the serial / parallel conversion circuit in a first-in-first-out order. Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the serial / parallel conversion circuit converts the serially input current loss quantization signal Dcs into a parallel output N-bit dead-time pre-output control code, which is then buffered by an N-bit buffer to obtain the N-bit dead-time control code Dt(N).

[0016] After the chip powers on, in the integrated control logic circuit, the counter starts working first. After the counter is working normally, it outputs the working control clock Ck_ctrl according to the OSC signal, and simultaneously outputs it to the control logic circuit, control register, input serial register, and serial / parallel conversion circuit. Next, the control logic circuit generates the chip status control signal SET and the chip mode control signal ON / OFF according to the state of the working control clock Ck_ctrl. The chip status control signal SET is output to the control register, and the chip mode control signal ON / OFF is output to the waveform data generation circuit. The control register will then generate control signals Ctrl and Ctrl1, and control signal Ctr... l will activate the waveform data generation circuit, buffer, and error handling logic. The waveform data generation circuit generates a power switch control pre-output signal Din_pre based on the external input reference clock OSC and the chip mode control signal ON / OFF. After buffering, the power switch control signal Din is generated. After a certain time delay, the control register will generate the control signal Ctrl1 and activate the input serial register, serial / parallel conversion circuit, and N-bit buffer. The input serial register receives the current loss quantization signal Dcs and outputs it to the serial / parallel conversion circuit in a first-in-first-out order. The parallel output signal of the serial / parallel conversion circuit is buffered by the N-bit buffer to obtain the N-bit dead time control code Dt(N).

[0017] When the voltage detection signal Dfb is high, it indicates that the LLC half-bridge resonant converter power system output is under normal heavy load, the chip mode control signal ON / OFF is invalid, and the overall LLC half-bridge resonant controller circuit is in heavy load mode; when the voltage detection signal Dfb is low, it indicates that the LLC half-bridge resonant converter power system is under light load, the chip mode control signal ON / OFF is valid, and the overall LLC half-bridge resonant controller circuit is in light load ON / OFF control mode; when in heavy load mode, the frequency of the power switch control signal Din is greater than the frequency when in light load ON / OFF control mode.

[0018] Specifically, the feedback voltage detection circuit includes: PMOS transistors M601, M602, M606, M607, M610, M611, M612, M619, and M621; NMOS transistors M603, M604, M605, M608, M609, M613, M614, M615, M616, M617, M618, M620, and M622; capacitor C61; resistor R61; inverters Inv61 and Inv62; and Schmitt triggers Sch61 and Sch62.

[0019] The inverter Inv61 has its input connected to the control signal OEN, and its output connected to the input of inverter Inv62 and the gate of NMOS transistor M618. The output of inverter Inv62 is simultaneously connected to the gates of PMOS transistors M601, M602, and M603. The drain of NMOS transistor M603 is connected to current source Ib6, and its source is connected to the drains and gates of NMOS transistors M613, M614, M615, M616, and M617. The gate of NMOS transistor M604 serves as the signal gate. The first input terminal is connected to the reference voltage Vref6. The gate of NMOS transistor M605 serves as another signal input terminal, connected to the feedback voltage signal FB. The source of NMOS transistor M604 is connected to the drain of NMOS transistor M614 and the gate of NMOS transistor M609. The source of NMOS transistor M605 is connected to the drain of NMOS transistor M615 and the gate of NMOS transistor M608. The drain of PMOS transistor M601 is connected to the gates of PMOS transistors M606, M607, M610, and M608. The drain of PMOS transistor M607 is connected to the drain of NMOS transistor M609 and the drain of PMOS transistor M611. The drain of transistor M602 is connected to the gate of PMOS transistor M612; the source of NMOS transistors M608 and M609 are connected to the source, and also to the drain of NMOS transistor M616; the drain of PMOS transistor M610 is connected to the source of PMOS transistor M611; the drain of PMOS transistor M612 is connected to the drain of NMOS transistor M617, the gate of PMOS transistor M611, the drain of NMOS transistor M618, and the input of Schmitt trigger Sch61; the output of Schmitt trigger Sch61 is connected to the gate of PMOS transistor M619 and the gate of NMOS transistor M620; the drain of PMOS transistor M619 is connected to the drain of NMOS transistor M620, and also to the gate of PMOS transistor M621. The gate of NMOS transistor M622 is connected to the drain of PMOS transistor M621. One end of resistor R61 is connected to the drain of NMOS transistor M622, one end of capacitor C61, and the input of Schmitt trigger R62. The output of Schmitt trigger R62 outputs the voltage detection signal Dfb. The drains of NMOS transistors M604 and M605, the sources of PMOS transistors M601, M602, M606, M607, M610, M612, M619, and M621 are all connected to the power supply voltage VCC.The sources of NMOS transistors M613, M614, M615, M616, M617, M618, M620, and M622, along with the other end of capacitor C61, are simultaneously connected to ground (GND).

[0020] The advantages of this invention are: To improve the efficiency of the LLC half-bridge resonant switch controller, (1) this invention adopts dead-time adaptive adjustment technology. On the one hand, it is controlled by the reference clock OSC, and different dead times are set according to the frequency. On the other hand, it can also respond to changes in soft switching losses caused by external loads and other operating characteristics, and adjust the size of the dead time to minimize switching losses. (2) To further improve efficiency, this invention also adopts load condition mode conversion technology. According to the state of the voltage signal FB output by the LLC half-bridge resonant converter power system, the working mode is divided into heavy load and light load modes to improve efficiency under light load. The solution of this invention can be widely applied to various LLC resonant converter power systems. Attached Figure Description

[0021] Figure 1 This is a block diagram of a typical LLC half-bridge resonant converter system.

[0022] Figure 2 This is a detailed topology diagram of a typical LLC half-bridge resonant converter system.

[0023] Figure 3 This is a block diagram of the overall circuit structure of the present invention.

[0024] Figure 4 This is a block diagram of the current detection circuit.

[0025] Figure 5 The schematic diagram and control clock waveform of the current loss tracking detection circuit are shown.

[0026] Figure 6 This is a schematic diagram of a feedback voltage detection circuit.

[0027] Figure 7 for Figure 4 An example of a medium current compensation buffer circuit.

[0028] Figure 8 This is an example of an oscillation clock generation circuit.

[0029] Figure 9 This is an example of an overcurrent protection circuit.

[0030] Figure 10 This is an example of a programmable dead-time generation circuit.

[0031] Figure 11 This is an internal block diagram of the integrated control logic circuit. Detailed Implementation

[0032] The present invention will now be described in further detail with reference to the accompanying drawings and embodiments.

[0033] like Figure 3 As shown, the circuit of the present invention includes: a current detection circuit 1, an oscillation clock generation circuit 2, a current follower detection circuit 3, a comprehensive control logic circuit 4, an input buffer circuit 5, a feedback voltage detection circuit 6, a programmable dead time generation circuit 7, a level shifting circuit 8, a delay compensation circuit 9, an over-temperature protection circuit, an over-current protection circuit, a high-side output drive circuit 11, and a low-side output drive circuit 10.

[0034] The current detection circuit 1 is used to detect the current signal CS output by the LLC half-bridge resonant converter power system, and generates a current loss detection signal Vcs, an output current detection signal Ics, and a CS sampling signal Vcsin under the control of the current sampling control clock Ckcs and the dead time control clock Ckdt. The current loss detection signal Vcs is connected to the current loss following detection circuit 3, the output current detection signal Ics is connected to the oscillation clock generation circuit 2, and the CS sampling signal Vcsin is connected to the overcurrent protection circuit.

[0035] The oscillation clock generation circuit 2 generates a reference clock OSC, a current sampling control clock Ckcs, a current following control clock Ckcom, and a dead time control clock Ckdt based on the output current detection signal Ics and the input frequency control signal Ifset.

[0036] The current loss following detection circuit 3 generates a current loss quantization signal Dcs based on the current loss detection signal Vcs under the control of the current sampling control clock Ckcs, the current following control clock Ckcom, and the dead time control clock Ckdt.

[0037] The input buffer circuit 5 generates an input frequency control signal Ifset based on the external frequency control signal FSET.

[0038] The feedback voltage detection circuit 6 is used to detect the voltage signal FB output by the power supply system of the LLC half-bridge resonant converter and generate the output voltage detection signal Dfb.

[0039] The overcurrent protection circuit generates an overcurrent protection signal OCP based on the CS sampling signal Vcsin, and the overtemperature protection circuit monitors the chip temperature in real time and generates an overtemperature protection signal OTP.

[0040] The integrated control logic circuit 4 generates a power switch control signal Din and an N-bit dead-time control code Dt(N) based on the states of the reference clock OSC, the current loss quantization signal Dcs, the voltage detection signal Dfb, the overcurrent protection signal OCP, and the overtemperature protection signal OTP.

[0041] The programmable dead-time generation circuit 7 generates a high-side output switch control signal Dho and a low-side output switch control signal Dlo with dead-time protection based on the power switch control signal Din and the dead-time control code Dt(N). The high-side output switch control signal Dho enters the level shift circuit to generate the high-side output signal Dhho, which then passes through the high-side output drive circuit 11 to generate the high-side gate drive signal HG and the floating power supply BST and floating ground SW. The low-side output switch control signal Dlo enters the delay compensation circuit to generate the low-side output signal Dllo, which then passes through the low-side output drive circuit 10 to generate the low-side gate drive signal LG. Here, N is any positive integer.

[0042] Figure 3The controller circuit shown detects the state of the current signal CS output by the LLC half-bridge resonant converter power system at different times to determine whether the dead time setting is optimal, and then adaptively adjusts the size of the dead time to minimize the switching losses of the LLC half-bridge resonant converter power system and achieve the best soft-switching characteristics. When the circuit starts working, the oscillation clock generation circuit 2 first generates a set of default initial reference clock OSC, current sampling control clock Ckcs, current follower control clock Ckcom, and dead time control clock Ckdt; then, the integrated control logic circuit 4 first generates a default power switch control signal Din and a dead time control code Dt(N); immediately afterward, the programmable dead time generation circuit 6 generates a high-side output switch control signal Dho and a low-side output switch control signal Dlo with dead time protection; the high-side output switch control signal Dho enters the level shift circuit to generate the high-side output signal Dhho, and passes through the high-side output drive circuit 11 to generate the high-side gate drive signal HG and the floating power supply BST and floating ground SW; the low-side output switch control signal Dlo enters the delay compensation circuit to generate the low-side output signal Dllo, and passes through the low-side output drive circuit 10 to generate the low-side gate drive signal LG. The high-side gate drive signal HG and the low-side gate drive signal LG respectively drive the high-speed power switching devices (which can be MOSFETs, IGBTs, or GaN) of the LLC half-bridge resonant converter power system. The gates of various devices (such as HEMTs) enable the system to operate normally; the current signal CS output by the LLC half-bridge resonant converter power supply system will correspondingly change its characteristics. The change in the CS signal will be detected by the current detection circuit 1 and the current loss follower detection circuit 3, and will generate the output current detection signal Ics and the current loss quantization signal Dcs, respectively; at the same time, the voltage signal FB output by the LLC half-bridge resonant converter power supply system will be detected by the feedback voltage detection circuit 6 and will generate the output voltage detection signal Dfb. The input buffer circuit 5 will generate the input frequency control signal Ifset according to the external frequency control signal FSET; the output current detection signal Ics and the input... The frequency control signal Ifset enters the oscillation clock generation circuit 2 to adjust the clock frequencies of the reference clock OSC, current sampling control clock Ckcs, current follower control clock Ckcom, and dead time control clock Ckdt; the current loss quantization signal Dcs is used to adjust the dead time of the high-side output switch control signal Dho and the low-side output switch control signal Dlo generated by the programmable dead time generation circuit 7 with dead time protection; the voltage detection signal Dfb, the overcurrent protection signal OCP, and the overtemperature protection signal OTP will control the operating mode of the LLC half-bridge resonant switch controller circuit and adjust the frequency characteristics of the power switch control signal Din.

[0043] The feedback voltage detection circuit 6 is used to detect the voltage signal FB output by the LLC half-bridge resonant converter power system and generate an output voltage detection signal Dfb. When Dfb is high, it indicates that the LLC half-bridge resonant converter power system output is under normal heavy load, and the overall LLC half-bridge resonant controller circuit is in heavy load mode; when Dfb is low, the opposite is true, indicating that the system is under light load, and the overall LLC half-bridge resonant controller circuit is in light load ON / OFF control mode.

[0044] For example, in constant current mode, if the feedback voltage detection circuit 6 detects that the output current is less than the reference value, Dfb is low, and the LLC half-bridge resonant controller circuit enters the ON / OFF control state. In the ON / OFF control state, if the load current is detected to be greater than the reference value, the LLC half-bridge resonant controller circuit switches from ON / OFF control to heavy load control state. ON / OFF control can greatly improve the dynamic response of the system. For example, a fixed ON / OFF cycle can be used to control the ripple of the output voltage, while selecting 80% full load as the peak efficiency point, and adjusting the duty cycle of ON / OFF control proportionally according to different load conditions.

[0045] As can be seen from the above working process, to improve the efficiency of the LLC half-bridge resonant controller, this invention first employs an adaptive dead-time adjustment technique. This dead-time optimization technique, in its adaptive adjustment of the dead time, is controlled by the reference clock OSC, setting different dead times according to the frequency. Furthermore, it can respond to changes in soft-switching losses caused by external loads and other operating characteristics, adjusting the dead-time value accordingly to minimize switching losses. To further improve efficiency, this invention also employs a load condition mode switching technique. Based on the state of the voltage signal FB output by the LLC half-bridge resonant converter power system, the operating mode is divided into heavy-load and light-load modes, improving efficiency under light load conditions.

[0046] Figure 4 This is a block diagram of the current detection circuit 1 of the present invention. The current detection circuit 1 internally includes: a Dt sampling switch 40, a Cs sampling switch 41, a current compensation buffer 42, and a voltage buffer 43.

[0047] The Dt sampling switch 40 and Cs sampling switch 41 sample the current signal CS output by the LLC half-bridge resonant converter power system under the control of the dead time control clock Ckdt and the current sampling control clock Ckcs, respectively, and obtain the sampling signal Vdtin and the sampling signal Vcsin, respectively.

[0048] The current compensation buffer 42 generates an output current detection signal Ics based on the reference voltage Vref and the sampling signal Vcsin.

[0049] The voltage buffer 43 isolates and buffers the sampling signal Vdtin to obtain the current loss detection signal Vcs.

[0050] Figure 4 The Dt sampling switch 40 and the Cs sampling switch 41 are the same sampling switches and can be implemented using various existing voltage sampling switches. The control clocks Ckdt and Ckcs of the Dt sampling switch 40 and the Cs sampling switch 41 are clock signals whose valid sampling times do not overlap, that is, the Dt sampling switch 40 and the Cs sampling switch 41 cannot sample at the same time.

[0051] Figure 5 The schematic diagram of the current loss tracking detection circuit 3 of the present invention includes: a high-performance sampling switch 50, a holding circuit 51, and a high-precision comparator 53.

[0052] The input current loss detection signal Vcs is connected to the analog signal input terminal of the high-performance sampling switch 50. The first analog signal output terminal of the high-performance sampling switch 50 is connected to the positive input terminal of the high-precision comparator 53 under the control of the current follower control clock CKcom. The second analog signal output terminal of the high-performance sampling switch 50 is connected to the signal input terminal of the holding circuit 51 under the control of the current sampling control clock CKdt. The analog signal output terminal of the holding circuit 51 is connected to the negative input terminal of the high-precision comparator 53 under the control of the current follower control clock CKcom. The data D(K) of the quantization output terminal of the high-precision comparator 53 is the current loss quantization signal Dcs, which is output to the integrated control logic circuit 4.

[0053] Figure 5 The document also provides the operating control clock waveform for the current loss tracking detection circuit 3. In this invention, the reference clock OSC is further subdivided into a three-phase non-overlapping clock consisting of a current sampling control clock Ckcs, a current tracking control clock Ckcom, and a dead-time control clock Ckdt. The control clock of the sampling switch 50 is connected to the current sampling control clock CKcs.

[0054] The simplified operation of the current loss tracking detection circuit is as follows: In phase Ckcs, the high-performance sampling switch 50 samples the input current loss detection signal Vcs. Assuming this is the Kth sampling, the voltage sampled by the switch is... V cs (K); Ckcom phase, high-precision comparator 53 will sample the voltage from the switch. V cs (K) will hold the voltage held by the holding circuit 51 for the previous clock cycle. V csThe comparison is performed using (K-1) (during the first sampling, the high-precision comparator 53 outputs a default signal; when K>1, it starts outputting a valid comparison quantization signal). The high-precision comparator 53 obtains the quantized data D(K), and an output D(K) of 1 indicates... V cs If the voltage increases, the high-precision comparator 53 outputs quantized data D(K) of 0, then the opposite occurs; Ckdt phase, V cs (K) will be held in the holding circuit 51.

[0055] The integrated control logic circuit 4 can obtain the changing trend of the current loss detection signal Vcs by reading the quantized data D(K). For example, if D(K) is continuously 1, it means that the current loss detection signal Vcs continues to rise. The current loss of the current signal CS output by the LLC half-bridge resonant converter power system increases during the dead time, and the dead time needs to be modulated. Figure 5 The accuracy of the circuit shown depends on the performance of the hold circuit 51 and the high-precision comparator 53. Obviously, speed and accuracy are contradictory indicators. To improve accuracy, the frequency of the control clock can be reduced. Different application backgrounds have very different requirements for the speed and accuracy of the hold circuit 51 and the high-precision comparator 53, and different circuit structures need to be designed.

[0056] Figure 6 The feedback voltage detection circuit 6 of the present invention includes: PMOS transistors M601, M602, M606, M607, M610, M611, M612, M619, M621, NMOS transistors M603, M604, M605, M608, M609, M613, M614, M615, M616, M617, M618, M620, and M622; capacitor C61; resistor R61; inverters Inv61 and Inv62; and Schmitt triggers Sch61 and Sch62.

[0057] The inverter Inv61 has its input connected to the control signal OEN, and its output connected to both the input of inverter Inv62 and the gate of NMOS transistor M618. Inverter Inv62 has its output connected to the gates of PMOS transistors M601, M602, and M603. The drain of NMOS transistor M603 is connected to current source Ib6, and its source is connected to the drain and gate of NMOS transistors M613, M614, M615, and M616, as well as the gate of NMOS transistor M618. The gate of transistor 617; the gate of NMOS transistor M604 serves as the signal input terminal, connected to the reference voltage Vref6; the gate of NMOS transistor M605 serves as another signal input terminal, connected to the feedback voltage signal FB; the source of NMOS transistor M604 is connected to the drain of NMOS transistor M614, and also to the gate of NMOS transistor M609; the source of NMOS transistor M605 is connected to the drain of NMOS transistor M615, and also to the gate of NMOS transistor M608; the drain of PMOS transistor M601 is simultaneously connected to the gates of PMOS transistors M606, M607, M610, and PMOS transistors... The drain of M606 is connected to the drain of PMOS transistor M608; the drain of PMOS transistor M607 is simultaneously connected to the drain of NMOS transistor M609, the drain of PMOS transistor M611, the drain of PMOS transistor M602, and the gate of PMOS transistor M612; the source of NMOS transistor M608 is connected to the source of NMOS transistor M609, and also to the drain of NMOS transistor M616; the drain of PMOS transistor M610 is connected to the source of PMOS transistor M611; the drain of PMOS transistor M612 is connected to the drain of NMOS transistor M617, and also to the gate of PMOS transistor M611 and the drain of NMOS transistor M618. The input terminal of Schmitt trigger Sch61 is connected to the input terminal; the output terminal of Schmitt trigger Sch61 is connected to the gate of PMOS transistor M619 and NMOS transistor M620; the drain of PMOS transistor M619 is connected to the drain of NMOS transistor M620, and is also connected to the gate of PMOS transistor M621 and NMOS transistor M622; the drain of PMOS transistor M621 is connected to one end of resistor R61, the other end of resistor R61 is connected to the drain of NMOS transistor M622 and one end of capacitor C61, and is also connected to the input terminal of Schmitt trigger R62; the output terminal of Schmitt trigger R62 serves as the Dfb signal output terminal of feedback voltage detection circuit 6.The drains of NMOS transistors M604 and M605, and the sources of PMOS transistors M601, M602, M606, M607, M610, M612, M619, and M621 are all connected to the power supply voltage VCC. The sources of NMOS transistors M613, M614, M615, M616, M617, M618, M620, and M622, along with the other end of capacitor C61, are all connected to ground voltage GND.

[0058] In the above circuit, NMOS transistors M604 and M614 form a source follower, NMOS transistors M605 and M615 form another source follower, PMOS transistors M606, M607, M608, M609, M616, M612, and M617 form a two-stage comparator, resistor R61 and capacitor C61 form an RC filter, and PMOS transistors M601, M602, M603, and M618 are the circuit's on / off control switches. When the control signal OEN is 0, the output Dfb of the feedback voltage detection circuit is locked; when the control signal OEN is 1, the output Dfb of the feedback voltage detection circuit is determined by the feedback voltage signal FB and the reference voltage Vref6.

[0059] Figure 7 for Figure 4 One embodiment of the medium current compensation buffer 42 includes PMOS transistors M701, M702, M704, M705, M706, M707, M708, NMOS transistors M709, M710, M711, M712, and M713, resistors R71 and R72, and capacitors C71 and C72.

[0060] In this configuration, the gate of PMOS transistor M705 is connected to the reference voltage Vref; the gates of PMOS transistors M701 and M702 are connected to the bias voltage Vbc71; the gates of PMOS transistors M707 and M708 are connected to the bias voltage Vbc72; the gates of NMOS transistors M710 and M709 are connected to the bias voltage Vbc73; and the drain of PMOS transistor M701 is simultaneously connected to PMOS transistors M705 and... The source of PMOS transistor M706; the drain of PMOS transistor M705 is connected to the source of PMOS transistor M707, the drain of PMOS transistor M707 is connected to the drain of NMOS transistor M710, and the source of NMOS transistor M710 is simultaneously connected to the drain of NMOS transistor M711, and the gates of NMOS transistors M711 and M712; the drain of PMOS transistor M706 is connected to the source of PMOS transistor M708, and the drain of PMOS transistor M708 is connected to the gate of NMOS transistor M702. The drain of MOSFET M709 and the gate of NMOS transistor M713 are connected to the upper end of resistor R72, and the lower end of resistor R72 is connected to the upper end of capacitor C72; the source of NMOS transistor M709 is connected to the drain of NMOS transistor M712; the drain of PMOS transistor M702 is connected to the drain of NMOS transistor M713, and is connected to the right end of capacitor C71 and the gate of PMOS transistor M704; the gate of NMOS transistor M706 is connected to the left end of capacitor C71 and resistor R72. The right end of R71 and the left end of R71 are connected to the sampling signal Vcsin; the drain of PMOS transistor M704 serves as the output terminal of the current detection signal Ics of the current compensation buffer; the sources of PMOS transistors M701, M702, and M704 are simultaneously connected to the power supply voltage VCC; the sources of NMOS transistors M711, M712, and M713 and the lower end of capacitor C72 are simultaneously connected to the ground voltage GND.

[0061] Figure 7 In this circuit, PMOS transistors M701, M702, M705, M706, M707, and M708, NMOS transistors M709, M710, M711, M712, and M713, along with resistor R72 and capacitor C72, constitute a two-stage common-source cascode operational amplifier. The two operational amplifiers, along with resistor R71 and capacitor C71, form an integrator circuit. This integrator circuit integrates the sampled signal Vcsin based on the reference voltage provided by Vref, controlling the gate signal of PMOS transistor M704 so that the magnitude of Ics follows the change in the sampled signal Vcsin, thus providing a real-time response to the CS signal.

[0062] Figure 8This is an embodiment of the oscillation signal generation circuit 2 of the present invention. The circuit includes: PMOS transistor M80, NMOS transistor M81, delay capacitor C80, Schmitt trigger S80, inverter Inv80, inverter Inv81, inverter Inv82, output buffer Buf80, and multi-phase clock generation circuit.

[0063] In this circuit, inverters Inv80, Inv81, and Inv82 are connected sequentially to form an odd-stage inverter chain. PMOS transistor M80 and NMOS transistor M81 form a delay-controlled inverter. The drain of PMOS transistor M80 is connected to the drain of NMOS transistor M81, serving as the output of the delay-controlled inverter. The gate of PMOS transistor M80 is connected to the gate of NMOS transistor M81, serving as the input of the delay-controlled inverter. The source of PMOS transistor M80 is connected to the output current detection signal Ics and the input frequency control signal. The source of NMOS transistor M81 is grounded, controlled by the Ifset signal. The output of the delay-controlled inverter is simultaneously connected to the upper end of the delay capacitor C80 and the input of Schmitt trigger S80. The output of Schmitt trigger S80 is connected to the input of the odd-stage inverter chain. The output of the odd-stage inverter chain is simultaneously connected to the input of output buffer Buf80, the input of the delay-controlled inverter, and the input of multi-phase clock generation circuit 81. The output of output buffer Buf80 outputs the reference clock OSC. Multi-phase clock generation circuit 81 generates three-phase non-overlapping current sampling control clock Ckcs, current following control clock Ckcom, and dead-time control clock Ckdt. The delay-controlled inverter, Schmitt trigger S80, and odd-stage inverter chain are cascaded to form a ring oscillator with an odd number of stages, generating an oscillation clock signal. The frequency of the oscillator output clock is controlled by the output current detection signal Ics and the input frequency control signal Ifset to delay the charging and discharging of the delay capacitor C80.

[0064] Figure 9 This is one embodiment of the overcurrent protection circuit of the present invention. The circuit includes PMOS transistors M901, M902, M903, M904, M905, M906, M907, M910, M911, M917, M919, NMOS transistors M908, M909, M912, M913, M914, M915, M916, M918, and M920, resistors R91 and R92, inverters Inv91 and Inv92.

[0065] In this circuit, the input of inverter Inv91 is connected to the control signal OEN. The output of inverter Inv91 is simultaneously connected to the gates of NMOS transistors 905, M914, M915, and M916, as well as the input of inverter Inv92. The output of inverter Inv92 is simultaneously connected to the gates of PMOS transistors 901 and 902. The drain of PMOS transistor 901 is simultaneously connected to the gates of PMOS transistors 903 and 904, as well as the drain of PMOS transistor 903 and the source of PMOS transistor 905. The drain of PMOS transistor 905 is connected to current source Ib9. The drain of PMOS transistor 904 is simultaneously connected to the sources of PMOS transistors M906 and M907. The gate of PMOS transistor M906 is connected to the reference voltage Vref9. The gate of MOSFET M907 is connected to the CS sampling signal Vcsin; the drain of PMOS transistor M906 is simultaneously connected to the drain of NMOS transistor M908, one end of resistor R91, the gate of NMOS transistor M913, and the drain of NMOS transistor M915; the drain of PMOS transistor M907 is simultaneously connected to the drain of NMOS transistor M909, one end of resistor R92, the gate of NMOS transistor M912, and the drain of NMOS transistor M914; the gates of NMOS transistors M908 and M909 are connected, and the other ends of resistors R91 and R92 are also connected; the drain of PMOS transistor M902 is simultaneously connected to the gate of PMOS transistor M910, the drain of PMOS transistor M910, the gate of PMOS transistor M911, and the drain of NMOS transistor M912; PMOS transistor M... The drain of transistor 911 is connected to the drain of NMOS transistor M913, and also to the drain of NMOS transistor M916, the gate of PMOS transistor M917, and the gate of NMOS transistor M918; the drain of PMOS transistor M917 is connected to the drain of NMOS transistor M918, and also to the gate of PMOS transistor M919 and the gate of NMOS transistor M920; the drain of PMOS transistor M919 is connected to the drain of NMOS transistor M920, and also serves as the signal output terminal OUT of the module; PMOS transistors M901 and M912... The sources of PMOS transistors M902, M903, M904, M910, M911, M917, and M919 are connected to the power supply voltage VCC; the sources of NMOS transistors M908, M909, M912, M913, M914, M915, M916, M918, and M920 are connected to the ground voltage GND.

[0066] In the above circuit, PMOS transistors M904, M906, M907, M908, M909, M910, M912, M911, and M913 form a two-stage comparator; PMOS transistors M917, M918, M919, and M920 form a two-stage inverter; and PMOS transistors M901, M902, M914, M915, and M916 act as the circuit's on / off control switch. When OEN is 0, the output OCP of the overcurrent protection circuit is locked; when OEN is 1, the output OCP of the overcurrent protection circuit is determined by the magnitude of Vcsin and the reference voltage Vref9.

[0067] Figure 10 This is one embodiment of the programmable dead-time generation circuit 7 of the present invention. The function of this embodiment is to convert the power switch control signal Din into a set of signals Dh and D with dead-time protection. l Where Dh serves as the high-side output switch control signal, and D... l The dead time serves as the low-side output switch control signal. It is achieved through cross-coupling and logic control of the numerically controlled delay unit, and its length is adjusted by the unit. The dead time control code Dt(N) adjusts the delay time using different control codes, ultimately controlling the overall dead time. Figure 10 The circuit described above is for generating one set of signals with dead time protection. By using multi-channel cross-coupling, multiple sets of signals with dead time protection can be generated.

[0068] Figure 11 The diagram shows the internal block diagram of the integrated control logic circuit 4 of the present invention. The circuit includes: a counter 100, an error handling logic 101, a waveform data generation circuit 102, an input serial register 103, a serial-to-parallel conversion circuit 104, a buffer 105, an N-bit buffer 106, a control logic circuit 107, and a control register 108.

[0069] The counter 100 generates a working control clock Ck_ctrl based on the external input reference clock OSC. The working control clock Ck_ctrl is simultaneously connected to the control clock input terminals of the control logic circuit 107, the input serial register 103, the serial / parallel conversion circuit 104, and the control register 108.

[0070] The control logic circuit 107 generates a chip status control signal SET and a chip mode control signal ON / OFF based on the status of the working control clock Ck_ctrl, the voltage detection signal Dfb, and the error signal ERR. The chip status control signal SET will be output to the control register 108, and the chip mode control signal ON / OFF will be output to the waveform data generation circuit 102.

[0071] Control register 108 generates control signal Ctrl and control signal Ctrl1. Control signal Ctrl is connected to the control signal input terminals of error handling logic 101, waveform data generation circuit 102 and buffer 105. Control signal Ctrl1 is connected to the control signal input terminals of input serial register 103, serial / parallel conversion circuit 104 and N-bit buffer 106.

[0072] The error handling logic 101 generates an error signal ERR under the control of the control signal Ctrl, based on the overcurrent protection signal OCP and the overtemperature protection signal OTP.

[0073] The waveform data generation circuit 102 generates a power switch control pre-output signal Din_pre based on the external input reference clock OSC and the chip mode control signal ON / OFF under the control of the working control clock Ck_ctrl and the control signal Ctrl. The power switch control pre-output signal Din_pre is connected to the buffer 105, and then the power switch control signal Din is generated through the buffer 105.

[0074] Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the input serial register 103 receives the current loss quantization signal Dcs in chronological order and outputs it to the serial / parallel conversion circuit 104 in a first-in-first-out order.

[0075] Under the control of the working control clock Ck_ctrl and the control signal Ctrl1, the serial-input current loss quantization signal Dcs is converted into the parallel output N-bit dead time pre-output control code Dt(N)_pre, and then the N-bit dead time control code Dt(N) is obtained through the N-bit buffer 106.

[0076] After the chip is powered on, the first component in the integrated control logic circuit 4 of this invention to start working normally is the counter 100. After the counter 100 is working normally, it outputs the working control clock Ck_ctrl according to the OSC signal and simultaneously inputs it to the control logic circuit 107, the control register 108, the input serial register 103, and the serial / parallel conversion circuit 104. Then, the control logic circuit 107 generates the chip status control signal SET and the chip mode control signal ON / OFF according to the working control clock Ck_ctrl. The chip status control signal SET will be output to the control register 108, and the chip mode control signal ON / OFF will be output to the waveform data generation circuit 102. The control register 108 will then generate the control signal Ctrl and the control signal Ct sequentially. rl1, the control signal Ctrl will turn on the waveform data generation circuit 102 and the buffer 105. The waveform data generation circuit 102 generates the power switch control pre-output signal Din_pre based on the external input reference clock OSC and the chip mode control signal ON / OFF. After being buffered by the buffer 105, the power switch control signal Din is generated. After a certain time delay, the control register 108 will generate the control signal Ctrl1 and turn on the input serial register 103, the serial / parallel conversion circuit 104 and the N-bit buffer 106. The input serial register 103 receives the current loss quantization signal Dcs and outputs it to the serial / parallel conversion circuit 104 in a first-in-first-out order. Finally, the N-bit dead time control code Dt(N) is obtained through the N-bit buffer 106.

[0077] When the voltage detection signal Dfb is high, it indicates that the LLC half-bridge resonant converter power system output is under normal, relatively heavy load. The chip mode control signal ON / OFF is invalid, and the overall LLC half-bridge resonant controller circuit is in heavy load mode. Conversely, when the voltage detection signal Dfb is low, it indicates that the power system is under light load. The chip mode control signal ON / OFF is valid, and the overall LLC half-bridge resonant controller circuit is in light load ON / OFF control mode. When the overall LLC half-bridge resonant controller circuit is in heavy load mode, the frequency of the power switch control signal Din will be higher than the Din frequency when the circuit is in light load ON / OFF control mode.

[0078] In the above-described operation of the integrated control logic circuit 4 of this invention, the working control clock Ck_ctrl is typically a clock signal with a frequency not higher than OSC. The delay time for generating control signals Ctrl and Ctrl1 must be greater than a positive integer multiple of the period of the working control clock Ck_ctrl; the specific duration can be set according to the application scenario. The control logic circuit 107 can be implemented in various ways, the most common being state machine control. The waveform data generation circuit 102 can also be implemented in various ways; it can use a memory to store the waveform or use pulse frequency modulation of the waveform.

[0079] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A high-efficiency LLC half-bridge resonant switch controller circuit, characterized in that... It includes a current detection circuit (1), an oscillation clock generation circuit (2), a current loss tracking detection circuit (3), a comprehensive control logic circuit (4), an input buffer circuit (5), a feedback voltage detection circuit (6), a programmable dead time generation circuit (7), a level shifting circuit (8), a delay compensation circuit (9), an over-temperature protection circuit, an over-current protection circuit, a high-side output drive circuit (11), and a low-side output drive circuit (10). The current detection circuit (1) is used to detect the current signal CS output by the power supply system of the LLC half-bridge resonant converter, and generates the current loss detection signal Vcs, the CS sampling signal Vcsin and the output current detection signal Ics under the control of the current sampling control clock Ckcs and the dead time control clock Ckdt. The current loss detection signal Vcs is connected to the input terminal of the current loss following detection circuit (3), the CS sampling signal Vcsin is connected to the input terminal of the overcurrent protection circuit, and the output current detection signal Ics is connected to the input terminal of the oscillation clock generation circuit (2). The other input terminal of the oscillation clock generation circuit (2) is connected to the input frequency control signal Ifset generated by the input buffer circuit (5). The oscillation clock generation circuit (2) generates a reference clock OSC, a current sampling control clock Ckcs, a current following control clock Ckcom, and a dead time control clock Ckdt based on the output current detection signal Ics and the input frequency control signal Ifset. The reference clock OSC is connected to the integrated control logic circuit (4). The current sampling control clock Ckcs and the dead time control clock Ckdt are connected to the current detection circuit (1) and the current loss following detection circuit (3). The current following control clock Ckcom is connected to the current loss following detection circuit (3). Under the control of the current sampling control clock Ckcs, the current following control clock Ckcom, and the dead time control clock Ckdt, the current loss following detection circuit (3) generates a current loss quantization signal Dcs based on the current loss detection signal Vcs and is connected to the integrated control logic circuit (4). The input terminal of the input buffer circuit (5) generates the input frequency control signal Ifset according to the external frequency control signal FSET; the feedback voltage detection circuit (6) is used to detect the voltage signal FB output by the power system of the LLC half-bridge resonant converter and generate the output voltage detection signal Dfb, which is connected to the input terminal of the integrated control logic circuit (4); the overcurrent protection circuit generates the overcurrent protection signal OCP according to the CS sampling signal Vcsin, and the overtemperature protection circuit monitors the chip temperature in real time and generates the overtemperature protection signal OTP. The overcurrent protection signal OCP and the overtemperature protection signal OTP are also connected to the input terminal of the integrated control logic circuit (4); the integrated control logic circuit (4) outputs the power switch control signal Din and the N-bit dead time control code Dt(N) according to the status of the reference clock OSC, the current loss quantization signal Dcs, the voltage detection signal Dfb, the overcurrent protection signal OCP and the overtemperature protection signal OTP, which are connected to the programmable dead time generation circuit (7), where N is any positive integer; The programmable dead time generation circuit (7) generates a high-side output switch control signal Dho and a low-side output switch control signal Dlo with dead time protection based on the power switch control signal Din and the dead time control code Dt(N). The high-side output switch control signal Dho enters the level shift circuit to generate the high-side output signal Dhho, and then passes through the high-side output drive circuit (11) to generate the high-side gate drive signal HG, the floating power supply BST, and the floating ground SW. The low-side output switch control signal Dlo enters the delay compensation circuit (9) to generate the low-side output signal Dllo, and then passes through the low-side output drive circuit (10) to generate the low-side gate drive signal LG.

2. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 1, characterized in that, When the circuit starts working, the oscillation clock generation circuit (2) first generates a set of default initial reference clock OSC, current sampling control clock Ckcs, current follower control clock Ckcom and dead time control clock Ckdt; then the integrated control logic circuit (4) first generates a default power switch control signal Din and dead time control code Dt(N); then the programmable dead time generation circuit (7) generates a high-side output switch control signal Dho and a low-side output switch control signal Dlo with dead time protection; the high-side output switch control signal Dho enters the level shift circuit to generate the high-side output signal Dhho, and then passes through the high-side output drive circuit (11) to generate the high-side gate drive signal HG and the floating power supply BST and floating ground SW for the LLC half-bridge resonant converter power supply system. The low-side output switch control signal Dlo enters the delay compensation circuit to generate the low-side output signal Dllo, which then passes through the low-side output drive circuit (10) to generate the low-side gate drive signal LG for the LLC half-bridge resonant converter power supply system. The current signal CS output by the LLC half-bridge resonant converter power supply system will generate corresponding characteristic changes. The changes in the CS signal will be detected by the current detection circuit (1) and the current loss follower detection circuit (3), and will generate the output current detection signal Ics and the current loss quantization signal Dcs, respectively. At the same time, the voltage signal FB output by the LLC half-bridge resonant converter power supply system will be detected by the feedback voltage detection circuit (6) and generate the output voltage detection signal Dfb. The input buffer circuit (5) will generate the input frequency control signal Ifset according to the external frequency control signal FSET. The output current detection signal Ics and the input frequency control signal Ifset enter the oscillation clock generation circuit (2) to adjust the clock frequencies of the reference clock OSC, the current sampling control clock Ckcs, the current following control clock Ckcom and the dead time control clock Ckdt. The current loss quantization signal Dcs is used to adjust the dead time of the programmable dead time generation circuit (7) that generates the high-side output switch control signal Dho and the low-side output switch control signal Dlo with dead time protection.

3. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 1, characterized in that, The states of the voltage detection signal Dfb, the overcurrent protection signal OCP, and the overtemperature protection signal OTP control the operating mode of the overall LLC half-bridge resonant switch controller circuit and adjust the frequency characteristics of the power switch control signal Din.

4. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 1, characterized in that, The current detection circuit (1) includes: a Dt sampling switch (40), a Cs sampling switch (41), a current compensation buffer (42), and a voltage buffer (43); the Dt sampling switch (40) samples the current signal CS under the control of the dead time control clock Ckdt to obtain the sampling signal Vdtin; the Cs sampling switch (41) samples the current signal CS under the control of the current sampling control clock Ckcs to obtain the sampling signal Vcsin; the sampling signal Vdtin is connected to the voltage buffer (43), which isolates and buffers the sampling signal Vdtin and outputs the current. The loss detection signal Vcs; the sampling signal Vcsin is connected to the current compensation buffer (42) on one side and the overcurrent protection circuit on the other side. The current compensation buffer (42) generates the output current detection signal Ics according to the reference voltage Vref and the sampling signal Vcsin. The Dt sampling switch (40) and the Cs sampling switch (41) are the same sampling switches. The control clocks Ckdt and Ckcs of the Dt sampling switch (40) and the Cs sampling switch (41) are clock signals with non-overlapping sampling effective times. That is, the Dt sampling switch (40) and the Cs sampling switch (41) cannot sample at the same time.

5. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 4, characterized in that, The current compensation buffer (42) includes PMOS transistors M701, M702, M704, M705, M706, M707, M708, NMOS transistors M709, M710, M711, M712, and M713, resistors R71 and R72, and capacitors C71 and C72. Specifically, the gate of PMOS transistor M705 is connected to the reference voltage Vref; the gates of PMOS transistors M701 and M702 are connected to the bias voltage Vbc71; the gates of PMOS transistors M707 and M708 are connected to the bias voltage Vbc72; the gates of NMOS transistors M710 and M709 are connected to the bias voltage Vbc73; the drain of PMOS transistor M701 is connected to the source of PMOS transistors M705 and M706; the drain of PMOS transistor M705 is connected to the source of PMOS transistor M707; the drain of PMOS transistor M707 is connected to the drain of NMOS transistor M710; the source of NMOS transistor M710 is connected to the drain of NMOS transistor M711, the gate of NMOS transistor M711, and the gate of NMOS transistor M712; the drain of PMOS transistor M706 is connected to the source of PMOS transistor M708; and the drain of PMOS transistor M708... The drain of NMOS transistor M709 is connected to the drain of NMOS transistor M713, the gate of NMOS transistor M713, and the upper end of resistor R72. The lower end of resistor R72 is connected to the upper end of capacitor C72. The source of NMOS transistor M709 is connected to the drain of NMOS transistor M712. The drain of PMOS transistor M702 is connected to the drain of NMOS transistor M713, the right end of capacitor C71, and the gate of PMOS transistor M704. The gate of NMOS transistor M706 is connected to the left end of capacitor C71 and the right end of resistor R71. The left end of resistor R71 is connected to the sampling signal Vcsin. The drain of PMOS transistor M704 serves as the output terminal of the output current detection signal Ics. The sources of PMOS transistors M701, M702, and M704 are all connected to the power supply voltage VCC. The sources of NMOS transistors M711, M712, and M713, and the lower end of capacitor C72 are all connected to the ground voltage GND.

6. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 1, characterized in that, The current loss tracking detection circuit (3) includes: a sampling switch (50), a holding circuit (51), and a high-precision comparator (53); the control clock input terminal of the sampling switch (50) is connected to the current sampling control clock CKcs, and the input current loss detection signal Vcs is connected to the analog signal input terminal of the sampling switch (50); the first analog signal output terminal of the sampling switch (50) is connected to the positive input terminal of the high-precision comparator (53), and the connection is controlled by the current tracking control clock CKcom; the second analog signal output terminal of the sampling switch (50) is connected to the signal input terminal of the holding circuit (51), and the connection is controlled by the dead time control clock Ckdt; the analog signal output terminal of the holding circuit (51) is connected to the negative input terminal of the high-precision comparator (53), and the connection is controlled by the current tracking control clock CKcom; the current sampling control clock Ckcs, the current tracking control clock Ckcom, and the dead time control clock Ckdt are three-phase non-overlapping clocks; the data output of the quantization output terminal of the high-precision comparator (53) is output to the integrated control logic circuit (4).

7. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 6, characterized in that, The operation of the current loss tracking detection circuit (3) is as follows: In phase Ckcs, the sampling switch (50) samples the input current loss detection signal Vcs. The voltage obtained during the Kth sampling is... V cs (K); Ckcom phase, high-precision comparator (53) samples the voltage of the switch. V cs (K) and the voltage held by the holding circuit (51) in the previous clock cycle. V cs (K-1) is compared, and the data D(K) output by the quantization output terminal of the high-precision comparator (53) is the current loss quantization signal Dcs; the output D(K) is 1, indicating that V cs The voltage increases, and the output D(K) is 0, then the opposite occurs; Ckdt phase, V cs (K) will be held in the holding circuit (51).

8. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 1, characterized in that, The integrated control logic circuit (4) includes: a counter (100), error handling logic (101), waveform data generation circuit (102), input serial register (103), serial-to-parallel conversion circuit (104), buffer (105), N-bit buffer (106), control logic circuit (107), and control register (108); the counter (100) generates a working control clock Ck_ctrl according to the reference clock OSC, and the working control clock Ck_ctrl is simultaneously connected to the control logic circuit (107), input serial register (103), serial-to-parallel conversion circuit (104), and control register (108) for control timing. The clock input terminal; the control logic circuit (107) is connected to the working control clock Ck_ctrl, the voltage detection signal Dfb, and the error signal ERR. Based on the state of these signals, it generates a chip status control signal SET and a chip mode control signal ON / OFF. The chip status control signal SET is connected to the control register (108), and the chip mode control signal ON / OFF is connected to the waveform data generation circuit (102). The control register (108) outputs control signals Ctrl and Ctrl1. The control signal Ctrl is connected to the control signals of the error handling logic (101), the waveform data generation circuit (102), and the buffer (105). The input terminal is connected to the control signal input terminal of the input serial register (103), the serial / parallel conversion circuit (104), and the N-bit buffer (106); the error handling logic (101) is connected to the overcurrent protection signal OCP and the overtemperature protection signal OTP, and generates the error signal ERR under the control of the control signal Ctrl; the waveform data generation circuit (102) generates the power switch control pre-output signal Din_pre under the control of the control signal Ctrl based on the external input reference clock OSC and the chip mode control signal ON / OFF, and is connected to the buffer ( 105), the power switch control signal Din is generated by the buffer (105); the serial input register (103) receives the current loss quantization signal Dcs in the order of time according to the working control clock Ck_ctrl and the control signal Ctrl1 and outputs it to the serial / parallel conversion circuit (104) in the order of first-in-first-out; the serial / parallel conversion circuit (104) converts the serial input current loss quantization signal Dcs into the parallel output N-bit dead time pre-output control code under the control of the working control clock Ck_ctrl and the control signal Ctrl1, and then obtains the N-bit dead time control code Dt(N) through the N-bit buffer (106).

9. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 8, characterized in that, After the chip is powered on, the counter (100) in the integrated control logic circuit (4) starts working first. After the counter (100) works normally, it outputs the working control clock Ck_ctrl according to the OSC signal, and outputs it to the control logic circuit (107), control register (108), input serial register (103) and serial / parallel conversion circuit (104). Then, the control logic circuit (107) generates the chip status control signal SET and the chip mode control signal ON / OFF according to the state of the working control clock Ck_ctrl. The chip status control signal SET will be output to the control register (108), and the chip mode control signal ON / OFF will be output to the waveform data generation circuit (102). The control register (108) will generate the control signal Ctrl and the control signal Ctrl1 in sequence. The control signal Ctrl will turn on the waveform. The data generation circuit (102), buffer (105), and error handling logic (101) are used. The waveform data generation circuit (102) generates a power switch control pre-output signal Din_pre based on the external input reference clock OSC and the chip mode control signal ON / OFF. After buffering (105), the power switch control signal Din is generated. After a certain time delay, the control register (108) generates a control signal Ctrl1 and enables the input serial register (103), serial / parallel conversion circuit (104), and N-bit buffer (106). The input serial register (103) receives the current loss quantization signal Dcs and outputs it to the serial / parallel conversion circuit (104) in a first-in-first-out order. The serial / parallel conversion circuit (104) outputs the parallel signal through the N-bit buffer (106) to obtain the N-bit dead time control code Dt(N). When the voltage detection signal Dfb is high, it indicates that the LLC half-bridge resonant converter power system output is under normal heavy load, the chip mode control signal ON / OFF is invalid, and the overall LLC half-bridge resonant controller circuit is in heavy load mode; when the voltage detection signal Dfb is low, it indicates that the LLC half-bridge resonant converter power system is under light load, the chip mode control signal ON / OFF is valid, and the overall LLC half-bridge resonant controller circuit is in light load ON / OFF control mode; when in heavy load mode, the frequency of the power switch control signal Din is greater than the frequency when in light load ON / OFF control mode.

10. The high-efficiency LLC half-bridge resonant switch controller circuit according to claim 1, characterized in that, The feedback voltage detection circuit (6) includes: PMOS transistors M601, M602, M606, M607, M610, M611, M612, M619, M621, NMOS transistors M603, M604, M605, M608, M609, M613, M614, M615, M616, M617, M618, M620, M622, capacitor C61, resistor R61, inverter Inv61, inverter Inv62, Schmitt trigger Sch61, and Schmitt trigger Sch62; The inverter Inv61 has its input connected to the control signal OEN, and its output connected to the input of inverter Inv62 and the gate of NMOS transistor M618. The output of inverter Inv62 is simultaneously connected to the gates of PMOS transistors M601, M602, and M603. The drain of NMOS transistor M603 is connected to current source Ib6, and its source is connected to the drains and gates of NMOS transistors M613, M614, M615, M616, and M617. The gate of NMOS transistor M604 serves as the signal gate. The first input terminal is connected to the reference voltage Vref6. The gate of NMOS transistor M605 serves as another signal input terminal, connected to the feedback voltage signal FB. The source of NMOS transistor M604 is connected to the drain of NMOS transistor M614 and the gate of NMOS transistor M609. The source of NMOS transistor M605 is connected to the drain of NMOS transistor M615 and the gate of NMOS transistor M608. The drain of PMOS transistor M601 is connected to the gates of PMOS transistors M606, M607, M610, and M608. The drain of PMOS transistor M607 is connected to the drain of NMOS transistor M609 and the drain of PMOS transistor M611. The drain of transistor M602 is connected to the gate of PMOS transistor M612; the source of NMOS transistors M608 and M609 are connected to the source, and also to the drain of NMOS transistor M616; the drain of PMOS transistor M610 is connected to the source of PMOS transistor M611; the drain of PMOS transistor M612 is connected to the drain of NMOS transistor M617, the gate of PMOS transistor M611, the drain of NMOS transistor M618, and the input of Schmitt trigger Sch61; the output of Schmitt trigger Sch61 is connected to the gate of PMOS transistor M619 and the gate of NMOS transistor M620; the drain of PMOS transistor M619 is connected to the drain of NMOS transistor M620, and also to the gate of PMOS transistor M621. The gate of NMOS transistor M622 is connected to the drain of PMOS transistor M621. One end of resistor R61 is connected to the drain of NMOS transistor M622, one end of capacitor C61, and the input of Schmitt trigger R62. The output of Schmitt trigger R62 outputs the voltage detection signal Dfb. The drains of NMOS transistors M604 and M605, the sources of PMOS transistors M601, M602, M606, M607, M610, M612, M619, and M621 are all connected to the power supply voltage VCC.The sources of NMOS transistors M613, M614, M615, M616, M617, M618, M620, and M622, along with the other end of capacitor C61, are simultaneously connected to ground (GND).

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