A novel gallium nitride IGBT device and its fabrication method and chip

Abstract

This application belongs to the field of power device technology, and provides a novel gallium nitride IGBT device and its fabrication method and chip. A second groove extending into the N-type gallium nitride layer is formed by etching the back side of a semiconductor substrate. P-type dopant ions are then implanted into the N-type gallium nitride layer under first preset conditions, forming a P-type collector region on the back side of the N-type gallium nitride layer. By sampling the P-type dopant ion implantation in the N-type gallium nitride layer under the first preset conditions, the concentration of the P-type collector region can reach 2.3–2.5 × 10⁻⁶. 19 cm ‑3 This results in a high concentration of P-type collector regions. The high concentration of P-type collector regions allows IGBT devices to have lower on-resistance during operation, thus expanding the application range and scenarios of IGBT devices.

Description

Technical Field

[0001] This application belongs to the field of power device technology, and in particular relates to a novel gallium nitride IGBT device and its fabrication method and chip. Background Technology

[0002] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It combines the low on-resistance and high voltage withstand characteristics of both BJTs and MOSFETs, and also possesses many excellent characteristics such as voltage control, high input impedance, low drive power, low on-resistance, and low switching losses. It is widely used in medium and high power electronic systems.

[0003] However, in the traditional process of fabricating IGBT devices, the substrate is first thinned, and then ion implantation is performed on the thinned substrate. However, because the substrate is thin, it is not convenient to perform the subsequent ion implantation process. Moreover, after the ion implantation process, the annealing process can only be laser annealing, low-temperature annealing, or high-temperature annealing followed by photolithography etching of the front metal. As a result, the doping concentration of the ion implantation region is relatively low, which leads to a large defect density and high resistance in the fabricated IGBT device. Summary of the Invention

[0004] The purpose of this application is to provide a novel gallium nitride IGBT device and its fabrication method and chip, aiming to solve the problem of high resistance in existing IGBT devices.

[0005] The first aspect of this application provides a method for fabricating a novel gallium nitride IGBT device, the novel gallium nitride IGBT device comprising:

[0006] A buffer layer is formed on the front side of a semiconductor substrate, and an N-type gallium nitride layer is formed on the buffer layer;

[0007] A P-type gallium nitride layer is formed on the N-type gallium nitride layer;

[0008] The P-type gallium nitride layer is trenched to form a first groove extending into the N-type gallium nitride layer, and a gate dielectric layer is formed on the inner wall of the first groove; wherein, the gate dielectric layer divides the P-type gallium nitride layer into a first P-type gallium nitride unit and a second P-type gallium nitride unit;

[0009] In a portion of the first P-type gallium nitride (GaN) unit and the second P-type GaN unit, an N-type doped ion implantation process is performed to form a first N-type emitter region in the first P-type GaN unit and a second N-type emitter region in the second P-type GaN unit; wherein both the first N-type emitter region and the second N-type emitter region are in contact with the gate dielectric layer;

[0010] A gate is formed within the first groove;

[0011] A first emitter is formed on the first P-type gallium nitride cell and the first N-type emitter region, and a second emitter is formed on the second P-type gallium nitride cell and the second N-type emitter region;

[0012] A second groove is formed by etching on the back side of the semiconductor substrate, extending into the N-type gallium nitride layer, and P-type dopant ions are implanted into the N-type gallium nitride layer under a first preset condition to form a P-type collector region on the back side of the N-type gallium nitride layer.

[0013] A collector electrode is formed on the back side of the P-type collector region.

[0014] In one embodiment, forming a gate dielectric layer on the inner wall of the first groove includes:

[0015] A gate dielectric material is filled into the first groove, and the gate dielectric material is etched to form the gate dielectric layer attached to the inner wall of the first groove; wherein the gate dielectric layer has a concave structure, and the groove depth of the gate dielectric layer is greater than the thickness of the P-type gallium nitride layer.

[0016] In one embodiment, etching the back side of the semiconductor substrate to form a second groove extending into the N-type gallium nitride layer includes:

[0017] A portion of the back side of the semiconductor substrate is etched to form a second groove opposite to the gate dielectric layer, and the semiconductor substrate is divided into a first substrate unit and a second substrate unit, and the buffer layer is divided into a first buffer unit and a second buffer unit.

[0018] In one embodiment, the implantation of P-type dopant ions into the N-type gallium nitride layer under a first preset condition includes:

[0019] Under a first preset condition, P-type doped ions are injected into the second groove to form a P-type collector region at the bottom of the second groove that is not in contact with the gate dielectric layer.

[0020] In one embodiment, the implantation of P-type dopant ions into the N-type gallium nitride layer under a first preset condition includes:

[0021] A P-type doped ion implantation process is performed under a pressure range of 300MPa-500MPa and a temperature range of 1200℃-1300℃ to form a P-type collector region on the back side of the N-type gallium nitride layer; wherein the P-type doped ion implantation process takes 10-20 minutes.

[0022] In one embodiment, the width of the second groove is greater than the width of the gate dielectric layer and less than the width of the buffer layer.

[0023] In one embodiment, the width of the second groove is equal to the width of the buffer layer.

[0024] In one embodiment, the concentration of N-type dopant ions in the first N-type emitter region and the second N-type emitter region is 10-100 times the concentration of P-type dopant ions in the P-type gallium nitride layer.

[0025] A second aspect of this application provides a novel gallium nitride IGBT device, which is fabricated by any of the methods described above.

[0026] A third aspect of this application provides a chip comprising a novel gallium nitride IGBT device fabricated by any of the methods described above.

[0027] This application provides a novel gallium nitride IGBT device and its fabrication method. In this chip, a second groove is formed by etching the back side of a semiconductor substrate, extending into an N-type gallium nitride layer. Under first preset conditions, P-type dopant ions are implanted into the N-type gallium nitride layer, forming a P-type collector region on the back side of the N-type gallium nitride layer. By implanting P-type dopant ions into the N-type gallium nitride layer under the first preset conditions, the concentration of the P-type collector region can reach 2.3–2.5 × 10⁻⁶. 19 cm -3 This results in a high concentration of P-type collector regions, which allows IGBT devices to have lower on-resistance during operation, thus expanding the application scenarios of IGBT devices. Attached Figure Description

[0028] Figure 1 This is a schematic flowchart of a novel gallium nitride IGBT device fabrication method provided in an embodiment of this application;

[0029] Figure 2 This is a schematic diagram of the formation of a buffer layer and an N-type gallium nitride layer provided in an embodiment of this application;

[0030] Figure 3 This is a schematic diagram of the formation of a P-type gallium nitride layer provided in an embodiment of this application;

[0031] Figure 4 This is a schematic diagram of the formation of the gate dielectric layer provided in an embodiment of this application;

[0032] Figure 5 This is a schematic diagram illustrating the formation of the first N-type emission region and the second N-type emission region provided in an embodiment of this application;

[0033] Figure 6 This is a schematic diagram of the formation of the gate provided in an embodiment of this application;

[0034] Figure 7 This is a schematic diagram of the formation of the first emitter and the second emitter provided in an embodiment of this application;

[0035] Figure 8 This is a schematic diagram of the formation of a P-type collector region provided in an embodiment of this application;

[0036] Figure 9 This is a schematic diagram of the formation of the collector provided in the embodiments of this application. Figure 1 ;

[0037] Figure 10 This is a schematic diagram of the formation of the collector provided in the embodiments of this application. Figure 2 . Detailed Implementation

[0038] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0039] It should be noted that when a component is referred to as being "fixed to" or "set on" another component, it can be directly on or indirectly on that other component. When a component is referred to as being "connected to" another component, it can be directly connected to or indirectly connected to that other component.

[0040] It should be understood that the terms "length", "width", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this application.

[0041] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0042] An Insulated Gate Bipolar Transistor (IGBT) is a composite, fully controllable, voltage-driven power semiconductor device composed of a BJT (Bipolar Junction Transistor) and a MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). It combines the low on-resistance and high voltage withstand characteristics of both BJTs and MOSFETs, and also possesses many excellent characteristics such as voltage control, high input impedance, low drive power, low on-resistance, and low switching losses. It is widely used in medium and high power electronic systems.

[0043] However, in the traditional process of fabricating IGBT devices, the substrate is first thinned, and then ion implantation is performed on the thinned substrate. However, because the substrate is thin, it is not convenient to perform the subsequent ion implantation process. Moreover, after the ion implantation process, the annealing process can only be laser annealing, low-temperature annealing, or high-temperature annealing followed by photolithography etching of the front metal. As a result, the doping concentration of the ion implantation region is relatively low, which leads to a large defect density and high resistance in the fabricated IGBT device.

[0044] To address the aforementioned technical problems, this application provides a novel method for fabricating gallium nitride IGBT devices, referring to... Figure 1 As shown, the novel gallium nitride IGBT device includes steps S10 to S80.

[0045] Step S10 includes: referencing Figure 2 As shown, a buffer layer 20 is formed on the front side of the semiconductor substrate 10, and an N-type gallium nitride layer 30 is formed on the buffer layer 20.

[0046] In this embodiment, see Figure 2 As shown, a buffer layer 20 is formed on the front side of the semiconductor substrate 10, and an N-type gallium nitride layer 30 is formed on the front side of the buffer layer 20. The thickness of the N-type gallium nitride layer 30 is greater than the thickness of the buffer layer 20. The N-type gallium nitride layer 30 can be obtained by doping gallium nitride material with N-type dopant ions.

[0047] In one specific embodiment, the semiconductor substrate 10 is a silicon substrate or a silicon carbide substrate.

[0048] In one specific embodiment, the material of the buffer layer 20 can be aluminum nitride.

[0049] In one embodiment, step S10 specifically includes steps S11 and S12.

[0050] Step S11 includes: forming a buffer layer 20 on the front side of the semiconductor substrate 10 by epitaxial growth.

[0051] Step S12 includes: forming an N-type gallium nitride layer 30 on the front side of the buffer layer 20 by epitaxial growth.

[0052] In this embodiment, reference Figure 2 As shown, when the semiconductor substrate 10 is a silicon substrate, aluminum nitride material is deposited on the front side of the silicon substrate, and gallium nitride material is etched to obtain the following result: Figure 2 The buffer layer 20 is shown. The thickness of the N-type gallium nitride layer 30 is controlled by depositing N-type gallium nitride material on the buffer layer 20 and etching it.

[0053] In one embodiment, in step S12, an N-type gallium nitride layer 30 can be formed by first depositing gallium nitride material on the buffer layer 20 and then performing an N-type doped ion implantation process on the gallium nitride material.

[0054] In one embodiment, in-situ doping can be used during the deposition of the N-type gallium nitride layer 30, that is, N-type impurities can be introduced during the deposition process. Alternatively, after the N-type gallium nitride layer 30 is deposited, N-type impurities can be introduced into the N-type gallium nitride layer 30 through steps such as impurity implantation and propulsion, or steps such as pre-deposition and propulsion.

[0055] In one specific embodiment, the concentration of N-type doped ions in the N-type gallium nitride layer 30 is 10. 19 cm -3 .

[0056] Step S20 includes: referencing Figure 3 As shown, a P-type gallium nitride layer 40 is formed on the N-type gallium nitride layer 30.

[0057] In this embodiment, a P-type gallium nitride layer 40 is formed on the N-type gallium nitride layer 30 by epitaxial growth. Specifically, the P-type gallium nitride layer 40 is formed by depositing P-type gallium nitride material on the N-type gallium nitride layer 30, and the thickness of the P-type gallium nitride layer 40 can be controlled by an etching process.

[0058] In one embodiment, gallium nitride material can be deposited first on the N-type gallium nitride layer 30, and then a P-type doped ion implantation process can be performed on the gallium nitride material to form the P-type gallium nitride layer 40.

[0059] In one specific embodiment, the concentration of P-type doped ions in the P-type gallium nitride layer 40 is 10. 19 cm -3 .

[0060] In one specific embodiment, the thickness of the P-type gallium nitride layer 40 is the same as the thickness of the N-type gallium nitride layer 30.

[0061] Step S30 includes: referencing Figure 4 As shown, trench etching is performed on the P-type gallium nitride layer 40 to form a first groove extending into the N-type gallium nitride layer 30, and a gate dielectric layer 50 is formed on the inner wall of the first groove; wherein, the gate dielectric layer 50 divides the P-type gallium nitride layer 40 into a first P-type gallium nitride unit 41 and a second P-type gallium nitride unit 42.

[0062] In this embodiment, the P-type gallium nitride layer 40 is dry etched to form a first groove extending into the N-type gallium nitride layer 30 in a preset area. The width of the first groove is 1 / 3 of the width of the N-type gallium nitride layer 30, and the portion of the first groove extending into the N-type gallium nitride layer 30 is 1 / 3 of the thickness of the N-type gallium nitride layer 30. Then, a gate dielectric material is deposited on the inner wall of the first groove to form a gate dielectric layer 50.

[0063] In this embodiment, the gate dielectric layer 50 divides the P-type gallium nitride layer 40 into a first P-type gallium nitride unit 41 and a second P-type gallium nitride unit 42. It is understood that, referring to... Figure 4 As shown, when etching to form the first groove, the middle part of the P-type gallium nitride layer 40 is completely etched to expose the N-type gallium nitride layer 30, thereby splitting the P-type gallium nitride layer 40 from the middle into the first P-type gallium nitride unit 41 and the second P-type gallium nitride unit 42 on the left and right sides, so that the first P-type gallium nitride unit 41 and the second P-type gallium nitride unit 42 are isolated by the first trench.

[0064] In one embodiment, step S30 specifically includes steps S31 and S32.

[0065] Step S31 includes: under the cover of a mask, trench etching is performed on the P-type gallium nitride layer 40 to form a first groove extending into the N-type gallium nitride layer 30.

[0066] Step S32 includes: depositing a gate dielectric material on the inner wall of the first groove to form a gate dielectric layer 50.

[0067] In this embodiment, photoresist can be used as a mask to cover the P-type gallium nitride layer 40, and then photolithography can be performed on the P-type gallium nitride layer 40. After removing the photoresist, the result is as follows: Figure 3The first trench is shown. The depth of the first trench is greater than the thickness of the P-type gallium nitride layer 40. A gate dielectric material is filled in the first trench, and the gate dielectric material is etched to form a gate dielectric layer 50 attached to the inner wall of the first trench; wherein, the gate dielectric layer 50 has a concave structure, and the trench depth of the gate dielectric layer 50 is greater than the thickness of the P-type gallium nitride layer 40.

[0068] In this embodiment, the gate dielectric layer 50 is mainly used to isolate the gate 80 and the P-type gallium nitride layer 40, the gate 80 and the N-type gallium nitride layer 30, the gate 80 and the first N-type emitter region, and the gate 80 and the second N-type emitter region.

[0069] In one embodiment, forming a gate dielectric layer 50 on the inner wall of the first groove includes: filling the first groove with a gate dielectric material and etching the gate dielectric material to form a gate dielectric layer 50 attached to the inner wall of the first groove; wherein the gate dielectric layer 50 has a concave structure and the groove depth of the gate dielectric layer 50 is greater than the thickness of the P-type gallium nitride layer 40.

[0070] In this embodiment, a gate dielectric material is deposited in the first groove, and then the gate dielectric material is etched by dry etching to make the gate dielectric layer 50 have a concave structure, and the groove depth of the gate dielectric layer 50 is greater than the thickness of the P-type gallium nitride layer 40. It can be understood that the groove of the gate dielectric layer 50 is filled with single-crystal silicon or metal material to form a gate 80, wherein the thickness of the gate 80 is greater than the thickness of the P-type gallium nitride layer 40.

[0071] In one specific embodiment, the gate dielectric layer 50 is made of silicon oxide.

[0072] Step S40 includes: referencing Figure 5 As shown, N-type doped ion implantation is performed in a portion of the first P-type gallium nitride unit 41 and the second P-type gallium nitride unit 42 to form a first N-type emitter region 60 in the first P-type gallium nitride unit 41 and a second N-type emitter region 70 in the second P-type gallium nitride unit 42; wherein, both the first N-type emitter region 60 and the second N-type emitter region 70 are in contact with the gate dielectric layer 50.

[0073] In this embodiment, under the cover of a mask, a first N-type emission region 60 and a second N-type emission region 70 are formed by ion implantation in predetermined portions of the first P-type gallium nitride unit 41 and the second P-type gallium nitride unit 42. The first N-type emission region 60 is located on the top right side of the first P-type gallium nitride unit 41, and the second N-type emission region 70 is located on the top left side of the second P-type gallium nitride unit 42. The first N-type emission region 60 and the second N-type emission region 70 are symmetrically arranged.

[0074] In one embodiment, step S40 specifically includes steps S41 and S42.

[0075] Step S41 includes performing an N-type doped ion implantation process in a portion of the first P-type gallium nitride unit 41 to form a first N-type emitter region 60 within the first P-type gallium nitride unit 41.

[0076] Step S42 includes performing an N-type doped ion implantation process in a portion of the second P-type gallium nitride unit 42 to form a second N-type emitter region 70 within the second P-type gallium nitride unit 42.

[0077] In this embodiment, reference Figure 5 As shown, under the cover of the mask, N-type doped ions are implanted at the upper right corner of the first P-type gallium nitride unit 41 to form a first N-type emitter region 60, and N-type ions are implanted at the upper left corner of the second P-type gallium nitride unit 42 to form a second N-type emitter region 70. Ion implantation can be performed at high temperatures, specifically within the range of 1000℃ to 1200℃.

[0078] In one embodiment, the N-type dopant ion can be phosphorus, and a high-temperature annealing process is performed to allow phosphorus ions to enter the first P-type gallium nitride unit 41 and the second P-type gallium nitride unit 42 to form the first N-type emitter region 60 and the second N-type emitter region 70.

[0079] In one embodiment, the concentration of N-type doped ions in the first N-type emitter region 60 and the second N-type emitter region 70 is 10-100 times the concentration of P-type doped ions in the P-type gallium nitride layer 40.

[0080] In this embodiment, the doping concentration of N-type ions in the first N-type emitter region 60 and the second N-type emitter region 70 can be 10. 20 cm -3 The concentration of P-type doped ions within the P-type gallium nitride layer 40 is 10. 19 cm -3 It is understandable that the first N-type emitter region 60 and the second N-type emitter region 70 are heavily doped, while the P-type gallium nitride layer 40 is lightly doped.

[0081] In one specific embodiment, the thickness of the first N-type emitter region 60 is one-third the thickness of the first P-type gallium nitride unit 41, and the thickness of the second N-type emitter region 70 is one-third the thickness of the second P-type gallium nitride unit 42.

[0082] Step S50 includes: referencing Figure 6 As shown, a gate 80 is formed in the first groove.

[0083] In this embodiment, a corresponding material is deposited in the first groove to form a gate 80. Specifically, after forming a gate dielectric layer 50 in the first groove, a gate 80 is formed on the gate dielectric layer 50 in the first groove.

[0084] In one specific embodiment, the gate 80 material can be polysilicon.

[0085] In one specific embodiment, the gate 80 material can be a metallic material.

[0086] Step S60 includes: referencing Figure 7 As shown, a first emitter 90 is formed on the first P-type gallium nitride unit 41 and the first N-type emitter region 60, and a second emitter 100 is formed on the second P-type gallium nitride unit 42 and the second N-type emitter region 70.

[0087] In this embodiment, reference Figure 5 As shown, corresponding metal materials are deposited on the first P-type gallium nitride unit 41 and the first N-type emitter region 60 and etched to form the first emitter 90. Corresponding metal materials are deposited on the second P-type gallium nitride unit 42 and the second N-type emitter region 70 and etched to form the second emitter 100. The first emitter 90 and the second emitter 100 have the same thickness.

[0088] In one specific embodiment, the first emitter 90 and the second emitter 100 are made of metallic materials.

[0089] In one specific embodiment, the thickness of the first emitter 90 and the second emitter 100 is 200-500 angstroms.

[0090] Step S70 includes: referencing Figure 8 As shown, a second groove is formed on the back side of the semiconductor substrate 10, extending into the N-type gallium nitride layer 30, and P-type doped ions are implanted into the N-type gallium nitride layer 30 under a first preset condition to form a P-type collector region 110 on the back side of the N-type gallium nitride layer 30.

[0091] In this embodiment, photoresist can be used as a mask to cover the back side of the semiconductor substrate 10, and then photolithography can be performed on the back side of the semiconductor substrate 10 to expose the N-type gallium nitride layer 30. After removing the photoresist, the desired result is obtained as shown below. Figure 8 The second groove is shown. Under a first preset condition, P-type dopant ions are implanted into the N-type gallium nitride layer 30 to form a P-type collector region 110 on the back side of the N-type gallium nitride layer 30. The first preset condition is a high-temperature, high-pressure condition. In this embodiment, by using a high-temperature, high-pressure method to implant P-type dopant ions into the N-type gallium nitride layer 30, the concentration of the P-type collector region 110 can reach 2.3–2.5 × 10⁻⁶. 19cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type current collector region 110. 19 cm -3 This results in a high defect density and a large resistance, which in turn leads to a large on-resistance of the IGBT device and affects its performance. The embodiments of this application can form a high concentration of P-type collector regions 110. The high concentration of P-type collector regions 110 can enable the IGBT device to have a low on-resistance when it is working, thus improving the application scenarios of the IGBT device.

[0092] In one embodiment, step S70 specifically includes steps S71 and S72.

[0093] Step S71 includes etching the back side of the semiconductor substrate 10 to form a second groove extending into the N-type gallium nitride layer 30.

[0094] Step S72 includes: implanting P-type dopant ions into the N-type gallium nitride layer 30 under a first preset condition to form a P-type collector region 110 on the back side of the N-type gallium nitride layer 30.

[0095] In this embodiment, a preset area is selected on the back side of the semiconductor substrate 10, and mask etching is performed to completely etch away the semiconductor substrate 10 and the buffer layer 20 in the selected preset area, forming a second groove and exposing the N-type gallium nitride layer 30. Then, P-type doped ions are implanted into the bottom of the N-type gallium nitride in the second groove. The ion implantation is performed under high pressure and high temperature, which can result in a higher concentration of the P-type collector region 110. The high concentration of the P-type collector region 110 can enable the IGBT device to have a lower on-resistance during operation, thus improving the application scenarios of the IGBT device.

[0096] In one embodiment, reference Figure 8 , Figure 9 As shown, etching is performed on the back side of the semiconductor substrate 10 to form a second groove extending into the N-type gallium nitride layer 30, including: etching a portion of the back side of the semiconductor substrate 10 to form a second groove opposite to the gate dielectric layer 50, dividing the semiconductor substrate 10 into a first substrate unit 11 and a second substrate unit 12, and dividing the buffer layer 20 into a first buffer unit 21 and a second buffer unit 22.

[0097] In one embodiment, reference Figure 8 , Figure 9 As shown, the width of the second groove is greater than the width of the gate dielectric layer 50 and less than the width of the buffer layer 20.

[0098] In this embodiment, it is understood that the middle region of both the semiconductor substrate 10 and the buffer layer 20 is etched away, dividing the semiconductor substrate 10 into a first substrate unit 11 and a second substrate unit 12, and the buffer layer 20 into a first buffer unit 21 and a second buffer unit 22, thereby exposing the N-type gallium nitride layer 30 in preparation for subsequent P-type ion implantation at the bottom of the N-type gallium nitride layer 30. In this embodiment, the stability of the IGBT device can be improved by etching away only part of the semiconductor substrate 10 and part of the buffer layer 20.

[0099] In one embodiment, reference Figure 10 As shown, the width of the second groove is equal to the width of the buffer layer 20. It is understood that when etching the back side of the semiconductor substrate 10, the width of the etched second groove is the same as the width of the buffer layer 20. This makes it easier to perform P-type ion implantation on the N-type gallium nitride layer 30, and the resulting P-type collector region 110 is wider. Furthermore, because the concentration of the P-type collector region 110 is higher, this significantly reduces the on-resistance of the IGBT device and improves its performance.

[0100] In one embodiment, reference Figure 10 As shown, the width of the P-type collector region 110 is the same as the width of the second groove.

[0101] In one embodiment, injecting P-type doped ions into the N-type gallium nitride layer 30 under a first preset condition includes: injecting P-type doped ions into a second groove under the first preset condition to form a P-type collector region 110 at the bottom of the second groove that is not in contact with the gate dielectric layer 50.

[0102] In this embodiment, injecting P-type doped ions into the second groove under the first preset condition can increase the ion concentration of the P-type collector region 110. It is understood that the P-type collector region 110 is located at the bottom of the N-type gallium nitride layer 30, and part of the gate dielectric layer 50 is located at the top of the N-type gallium nitride layer 30. Furthermore, the gate dielectric layer 50 and the P-type collector region 110 in the N-type gallium nitride layer 30 do not contact each other, making the N-type gallium nitride layer 30 an I-shaped structure.

[0103] In one embodiment, implanting P-type doped ions into the N-type gallium nitride layer 30 under first preset conditions includes: performing a P-type doped ion implantation process under a pressure range of 300MPa-500MPa and a temperature range of 1200℃-1300℃ to form a P-type collector region 110 on the back side of the N-type gallium nitride layer 30; wherein the P-type doped ion implantation process takes 10-20 minutes.

[0104] In this embodiment, a P-type doped ion implantation process is performed at a pressure of 500 MPa and a temperature of 1300 °C for 20 minutes, resulting in a P-type collector region 110 concentration of 2.5 × 10⁻⁶. 19 cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type current collector region 110. 19 cm -3 This results in a high defect density and significant resistance, leading to a large on-resistance in the IGBT device and negatively impacting its performance. In this embodiment, the defect density is set to 2.5*10⁻⁶. 19 cm -3 The P-type collector region 110 enables the IGBT device to have a lower on-resistance during operation, thus expanding the application scenarios of the IGBT device.

[0105] In this embodiment, a P-type doped ion implantation process is performed at a pressure of 300 MPa and a temperature of 1200°C for 20 minutes, resulting in a P-type collector region 110 concentration of 2.3 × 10⁻⁶. 19 cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type current collector region 110. 19 cm -3 This results in a high defect density and high resistance, leading to a large on-resistance in the IGBT device and affecting its performance. In this embodiment, the defect density is set to 2.4*10⁻⁶. 19 cm -3 The P-type collector region 110 enables the IGBT device to have a lower on-resistance during operation, thus expanding the application scenarios of the IGBT device.

[0106] Step S80 includes: referencing Figure 9 , Figure 10 As shown, a collector 120 is formed on the back side of the P-type collector region 110.

[0107] In this embodiment, under the cover of a mask, a metal material is deposited on the back side of the P-type collector region 110 and etched to form a collector electrode 120, wherein the width of the collector electrode 120 is smaller than the width of the P-type collector region 110.

[0108] This application also provides a novel gallium nitride IGBT device, which is prepared by the above-described preparation method.

[0109] In one embodiment, reference Figure 9As shown, the novel gallium nitride IGBT device includes: a first substrate unit 11, a second substrate unit 12, a first buffer unit 21, a second buffer unit 22, an N-type gallium nitride layer 30, a P-type gallium nitride layer 40, a gate dielectric layer 50, a first N-type emitter region 60, a second N-type emitter region 70, a gate 80, a first emitter 90, a second emitter 100, a P-type collector region 110, and a collector electrode 120.

[0110] Specifically, a first buffer unit 21 is disposed on a first substrate unit 11, a second buffer unit 22 is disposed on a second substrate unit 12, an N-type gallium nitride layer 30 is disposed on the first buffer unit 21 and the second buffer unit 22, a P-type gallium nitride layer 40 is disposed on the N-type gallium nitride layer 30, and a gate dielectric layer 50 is disposed within the P-type gallium nitride layer 40 and extends into the N-type gallium nitride layer 30, wherein the gate dielectric layer 50 has a concave structure. A first N-type emitter region 60 and a second N-type emitter region 70 are both disposed within the P-type gallium nitride layer 40, and a gate 80 is disposed within the recess of the gate dielectric layer 50. A first emitter 90 is disposed on the P-type gallium nitride layer 40 and the first N-type emitter region 60, and a second emitter 100 is disposed on the P-type gallium nitride layer 40 and the second N-type emitter region 70. The P-type collector region 110 is disposed at the bottom of the N-type gallium nitride layer 30 between the first buffer unit 21 and the second buffer unit 22, and the P-type collector region 110 is not in contact with the gate dielectric layer 50. The collector electrode 120 is disposed on the back of the P-type collector region 110.

[0111] In one embodiment, reference Figure 10 As shown, the novel gallium nitride IGBT device includes: an N-type gallium nitride layer 30, a P-type gallium nitride layer 40, a gate dielectric layer 50, a first N-type emitter region 60, a second N-type emitter region 70, a gate 80, a first emitter 90, a second emitter 100, a P-type collector region 110, and a collector electrode 120.

[0112] Specifically, a P-type gallium nitride (GaN) layer 40 is disposed on an N-type GaN layer 30, and a gate dielectric layer 50 is disposed within the P-type GaN layer 40 and extends into the N-type GaN layer 30, wherein the gate dielectric layer 50 has a concave structure. A first N-type emitter region 60 and a second N-type emitter region 70 are both disposed within the P-type GaN layer 40, and a gate 80 is disposed within a recess in the gate dielectric layer 50. A first emitter 90 is disposed on the P-type GaN layer 40 and the first N-type emitter region 60, and a second emitter 100 is disposed on the P-type GaN layer 40 and the second N-type emitter region 70. A P-type collector region 110 is disposed at the bottom of the N-type GaN layer 30, and the P-type collector region 110 is not in contact with the gate dielectric layer 50. A collector electrode 120 is disposed on the back side of the P-type collector region 110.

[0113] In one embodiment, the width of the second groove is equal to the width of the buffer layer 20. It is understood that when etching the back side of the semiconductor substrate 10, the width of the etched second groove is the same as the width of the buffer layer 20. This facilitates P-type ion implantation of the N-type gallium nitride layer 30, and results in a wider P-type collector region 110. Furthermore, the higher concentration of the P-type collector region 110 significantly reduces the on-resistance of the IGBT device, thereby improving its performance.

[0114] In one embodiment, P-type doped ions are implanted into the N-type gallium nitride layer 30 under high temperature and high pressure conditions. For example, the P-type doped ion implantation process is performed under pressure range of 300MPa-500MPa and temperature range of 1200℃-1300℃ to form a P-type collector region 110 on the back side of the N-type gallium nitride layer 30; wherein the P-type doped ion implantation process takes 10-20 minutes.

[0115] In this embodiment, a P-type doped ion implantation process is performed at a pressure of 500 MPa and a temperature of 1300 °C for 20 minutes, resulting in a P-type collector region 110 concentration of 2.5 × 10⁻⁶. 19 cm -3 However, traditional ion implantation can only achieve a concentration of 2.0*10 in the P-type current collector region 110. 19 cm -3 This results in a high defect density and significant resistance, leading to a large on-resistance in the IGBT device and negatively impacting its performance. In this embodiment, the defect density is set to 2.5*10⁻⁶. 19 cm -3 The P-type collector region 110 enables the IGBT device to have a lower on-resistance during operation, thus expanding the application scenarios of the IGBT device.

[0116] This application also provides a chip, which includes a novel gallium nitride IGBT device fabricated by any of the above methods.

[0117] This application provides a novel gallium nitride (GaN) IGBT device and its fabrication method and chip. A photoresist is used as a mask to cover the back side of a semiconductor substrate 10. Photolithography is then performed on the back side of the semiconductor substrate 10 to expose an N-type gallium nitride layer 30. After removing the photoresist, a second groove is obtained. P-type dopant ions are implanted into the N-type gallium nitride layer 30 under first preset conditions, forming a P-type collector region 110 on the back side of the N-type gallium nitride layer 30. In this embodiment, by using a high-temperature, high-pressure method to implant P-type dopant ions into the N-type gallium nitride layer 30, the concentration of the P-type collector region 110 can reach 2.3–2.5 × 10⁻⁶. 19 cm-3 This results in a high concentration of P-type collector region 110. The high concentration of P-type collector region 110 enables the IGBT device to have a lower on-resistance during operation, thus expanding the application scenarios of the IGBT device.

[0118] Those skilled in the art will clearly understand that, for the sake of convenience and brevity, the above-described division of doped regions is used as an example. In practical applications, the above-described functional areas can be assigned to different doped regions as needed, that is, the internal structure of the device can be divided into different doped regions to complete all or part of the functions described above.

[0119] In the embodiments, the doped regions can be integrated into one functional region, or each doped region can exist independently, or two or more doped regions can be integrated into one functional region. The integrated functional region can be implemented using the same type of dopant ion or multiple types of dopant ions. Furthermore, the specific names of each doped region are only for easy differentiation and are not intended to limit the scope of protection of this application. The specific working process of the doped region in the fabrication method of the above device can be referred to the corresponding process in the foregoing method embodiments, and will not be repeated here.

[0120] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A method for fabricating a novel gallium nitride IGBT device, characterized in that, The novel gallium nitride IGBT device includes: A buffer layer is formed on the front side of a semiconductor substrate, and an N-type gallium nitride layer is formed on the buffer layer; A P-type gallium nitride layer is formed on the N-type gallium nitride layer; The P-type gallium nitride layer is trenched to form a first groove extending into the N-type gallium nitride layer, and a gate dielectric layer is formed on the inner wall of the first groove; wherein, the gate dielectric layer divides the P-type gallium nitride layer into a first P-type gallium nitride unit and a second P-type gallium nitride unit; In a portion of the first P-type gallium nitride (GaN) unit and the second P-type GaN unit, an N-type doped ion implantation process is performed to form a first N-type emitter region in the first P-type GaN unit and a second N-type emitter region in the second P-type GaN unit; wherein both the first N-type emitter region and the second N-type emitter region are in contact with the gate dielectric layer; A gate is formed within the first groove; A first emitter is formed on the first P-type gallium nitride cell and the first N-type emitter region. A second emitter is formed on the second P-type gallium nitride cell and the second N-type emitter region; A second groove is formed by etching on the back side of the semiconductor substrate, extending into the N-type gallium nitride layer. P-type dopant ions are then implanted into the N-type gallium nitride layer under first preset conditions to form a P-type collector region on the back side of the N-type gallium nitride layer. The first preset conditions include: a pressure range of 300MPa-500MPa, a temperature range of 1200℃-1300℃, and a P-type dopant ion implantation process time of 10-20 minutes. A collector electrode is formed on the back side of the P-type collector region.

2. The preparation method according to claim 1, characterized in that, The step of forming a gate dielectric layer on the inner wall of the first groove includes: A gate dielectric material is filled into the first groove, and the gate dielectric material is etched to form the gate dielectric layer attached to the inner wall of the first groove; wherein the gate dielectric layer has a concave structure, and the groove depth of the gate dielectric layer is greater than the thickness of the P-type gallium nitride layer.

3. The preparation method according to claim 1, characterized in that, The step of etching the back side of the semiconductor substrate to form a second groove extending into the N-type gallium nitride layer includes: A portion of the back side of the semiconductor substrate is etched to form a second groove opposite to the gate dielectric layer, and the semiconductor substrate is divided into a first substrate unit and a second substrate unit, and the buffer layer is divided into a first buffer unit and a second buffer unit.

4. The preparation method according to claim 3, characterized in that, The implantation of P-type doped ions into the N-type gallium nitride layer under the first preset condition includes: Under a first preset condition, P-type doped ions are injected into the second groove to form a P-type collector region at the bottom of the second groove that is not in contact with the gate dielectric layer.

5. The preparation method according to any one of claims 1-4, characterized in that, The width of the second groove is greater than the width of the gate dielectric layer and less than the width of the buffer layer.

6. The preparation method according to any one of claims 1-4, characterized in that, The width of the second groove is equal to the width of the buffer layer.

7. The preparation method according to claim 1, characterized in that, The concentration of N-type doped ions in the first N-type emitter region and the second N-type emitter region is 10-100 times the concentration of P-type doped ions in the P-type gallium nitride layer.

8. A novel gallium nitride IGBT device, characterized in that, The novel gallium nitride IGBT device is prepared by the preparation method described in any one of claims 1-7.

9. A chip, characterized in that, The chip includes a novel gallium nitride IGBT device prepared by the preparation method according to any one of claims 1-7.

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