Methods and apparatus for power conversion

Abstract

This application relates to the field of electronic technology, providing a power conversion method and apparatus. The apparatus includes a controller and a power conversion circuit, with the controller connected to a power switch transistor of the power conversion circuit. The controller receives an output voltage feedback signal from the power conversion circuit and sends a control signal to the power switch transistor. The control signal is used to control the power switch transistor to periodically conduct for a constant time period. The time period between a first moment corresponding to the rising edge of a pulse of the control signal and a second moment corresponding to the falling edge of the pulse is the actual conduction time of the power switch transistor within one cycle. The second moment is after the end of the preset conduction time corresponding to the pulse, and the first moment is after the start of the preset conduction time. The embodiments of this application enable the actual conduction time to be closer to the preset conduction time, thereby improving the switching frequency accuracy.

Description

Technical Field

[0001] This application relates to the field of electronic technology, and more specifically, to a power conversion method and apparatus. Background Technology

[0002] A direct current-to-direct current (DC-DC) converter is a device that converts electrical energy from one voltage value to another in a DC circuit. DC-DC chips involve various chip control technologies, including control technologies that can generate fixed-time pulses, such as constant on-time (COT) control and constant off-time control.

[0003] Taking COT control as an example, the constant on-time of the DC-DC power switch is controlled by a chip circuit. Typically, a power switching transistor acts as the power switch, converting the input voltage into an output voltage to drive the load through its on and off states. Currently, the actual on-time of the power switch controlled by the chip circuit used for COT control is longer than the preset on-time determined by the chip's circuit parameters, thus reducing the accuracy of the switching frequency. This reduction in switching frequency accuracy can potentially decrease the performance of the load chip and even cause it to restart.

[0004] Therefore, improving the frequency accuracy of power switches is an urgent problem to be solved. Summary of the Invention

[0005] This application provides a method and apparatus for power conversion that can improve the frequency accuracy of power switches.

[0006] In a first aspect, a power conversion device is provided, comprising a controller and a power conversion circuit, wherein the controller is connected to a power switch transistor of the power conversion circuit; the controller is further configured to send a control signal to the power switch transistor, the control signal being used to control the power switch transistor to periodically conduct for a constant time interval, wherein the time interval between a first moment corresponding to the rising edge of a pulse of the control signal and a second moment corresponding to the falling edge of the pulse is the actual conduction time of the power switch transistor within one cycle; wherein the second moment is after the end of the preset conduction time corresponding to the pulse, and the first moment is after the start of the preset conduction time, the preset conduction time being the theoretical conduction time of the power switch transistor within one cycle determined according to the circuit parameters of the controller and the power conversion circuit.

[0007] In the above scheme, when the second moment is after the end of the preset conduction time, compared to the case where the first moment is the same as the start of the preset conduction time, the above scheme can reduce the length of the actual conduction time by placing the first moment after the start of the preset conduction time, making the length of the actual conduction time closer to the length of the preset conduction time, reducing the impact of the second moment being after the end of the preset conduction time on the length of the conduction time, thereby improving the switching frequency accuracy.

[0008] In one possible implementation, the time period between the second moment and the end moment is the first time period, and the time period between the first moment and the start moment is the second time period. The difference between the length of the first time period and the length of the second time period is less than or equal to a preset value. Alternatively, the error in the length of the second time period relative to the first time period is less than or equal to a preset value.

[0009] The above scheme, by limiting the difference between the length of the first time period and the length of the second time period to less than or equal to a preset value, can make the lengths of the first time period and the second time period closer, so that the conduction time is closer to the preset conduction time, further reducing the impact of the second moment after the end of the preset conduction time on the length of the conduction time, thereby further improving the accuracy of the switching frequency.

[0010] In one possible implementation, the controller is further configured to convert the output voltage feedback signal into an error signal, and convert the error signal into a first pre-control signal and a second pre-control signal, wherein the rising edge of the first pre-control signal corresponds to the same time as the start time of the preset conduction time; the controller is further configured to convert the second pre-control signal into a first pre-compensation signal, wherein the time for converting the second pre-control signal into the first pre-compensation signal is a second time period; the controller is further configured to determine a first time based on the first pre-control signal and the first pre-compensation signal.

[0011] In one possible implementation, the second time period includes a first compensation time period and a second compensation time period. The control unit is specifically used to determine the second pre-compensation signal based on the second pre-control signal and the first reference voltage. The time between the rising edge of the second pre-compensation signal and the time when the second pre-control signal and the first reference signal intersect is the first compensation time period. The control unit is specifically used to convert the second pre-compensation signal into the first pre-compensation signal. The time for converting the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

[0012] In one possible implementation, when the second pre-control signal is a rising ramp voltage signal, 0V ≤ first reference voltage ≤ first threshold; or, when the second pre-control signal is a falling ramp voltage signal, the second threshold ≤ first reference voltage ≤ supply voltage.

[0013] In one possible implementation, a controller is configured to convert the output voltage feedback signal into a first control signal, determine a first moment based on the first control signal and a second reference voltage, and determine a second moment based on the first control signal and a third reference voltage; wherein the second reference voltage is different from the third reference voltage, the first moment is delayed by a second time period relative to the moment when the first control signal and the second reference voltage intersect, and the second moment is delayed by a first time period relative to the moment when the first control signal and the third reference voltage intersect.

[0014] In one possible implementation, before the first moment, the reference voltage used for comparison with the first control signal is a second reference voltage; after the first moment and before the second moment, the reference voltage used for comparison with the first control signal is a third reference voltage.

[0015] In one possible implementation, when the first control signal is a rising ramp voltage signal, 0V ≤ second reference voltage ≤ first threshold, and third reference voltage > second reference voltage; or, when the first control signal is a falling ramp voltage signal, second threshold ≤ second reference voltage ≤ supply voltage, and third reference voltage < second reference voltage.

[0016] Secondly, a power conversion method is provided, applied to a controller in a power conversion device, the power conversion device further including a power conversion circuit, the controller being connected to a power switch transistor of the power conversion circuit, comprising: receiving an output voltage feedback signal from the power conversion circuit; sending a control signal to the power switch transistor, the control signal being used to control the power switch transistor to periodically conduct for a constant time period, wherein the time period between a first moment corresponding to the rising edge of a pulse of the control signal and a second moment corresponding to the falling edge of the pulse is the actual conduction time of the power switch transistor in one cycle; wherein the second moment is after the end of a preset conduction time corresponding to the pulse, and the first moment is after the start of the preset conduction time, the preset conduction time being the theoretical conduction time of the power switch transistor in one cycle determined according to the circuit parameters of the controller and the power conversion circuit.

[0017] The beneficial effects of the second aspect can be referenced from those of the first aspect.

[0018] The above scheme, by compensating for the first time period with a second time period, can reduce the impact of the first time period on the conduction time, thereby improving the switching frequency accuracy. In one possible implementation, the length of the first time period is equal to the length of the second time period. Thus, the actual conduction time after compensation by the second time period can be as close as possible to the preset conduction time.

[0019] In one possible implementation, the time period between the second moment and the end moment is the first time period, and the time period between the first moment and the start moment is the second time period. The difference between the length of the first time period and the length of the second time period is less than or equal to a preset value. Alternatively, the error in the length of the second time period relative to the first time period is less than or equal to a preset value.

[0020] In one possible implementation, the method further includes: converting the output voltage feedback signal into an error signal, and converting the error signal into a first pre-control signal and a second pre-control signal, wherein the pulse width of the first pre-control signal corresponds to a time period equal to the preset on-time of the power switch; converting the second pre-control signal into a first pre-compensation signal, wherein the time for converting the second pre-control signal into the first pre-compensation signal is a second time period; and determining a control signal based on the first pre-control signal and the first pre-compensation signal.

[0021] In one possible implementation, the second time period includes a first compensation time period and a second compensation time period. The method further includes: determining a second pre-compensation signal based on a second pre-control signal and a first reference voltage, wherein the time between the rising edge of the second pre-compensation signal and the time when the second pre-control signal and the first reference signal intersect is the first compensation time period; converting the second pre-compensation signal into a first pre-compensation signal, and the time for converting the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

[0022] In one possible implementation, when the second pre-control signal is a rising ramp voltage signal, 0V ≤ first reference voltage ≤ first threshold; or, when the second pre-control signal is a falling ramp voltage signal, the second threshold ≤ first reference voltage ≤ supply voltage.

[0023] In one possible implementation, the method further includes: converting the output voltage feedback signal into a first control signal, determining a first moment based on the first control signal and a second reference voltage, and determining a second moment based on the first control signal and a third reference voltage; wherein the second reference voltage is different from the third reference voltage, the first moment is delayed by a second time period relative to the moment when the first control signal and the second reference voltage intersect, and the second moment is delayed by a first time period relative to the moment when the first control signal and the third reference voltage intersect.

[0024] In one possible implementation, before the first moment, the reference voltage used for comparison with the first control signal is a second reference voltage; after the first moment and before the second moment, the reference voltage used for comparison with the first control signal is a third reference voltage.

[0025] In one possible implementation, when the first control signal is a rising ramp voltage signal, 0V ≤ second reference voltage ≤ first threshold, and third reference voltage > second reference voltage; or, when the first control signal is a falling ramp voltage signal, second threshold ≤ second reference voltage ≤ supply voltage, and third reference voltage < second reference voltage.

[0026] Thirdly, a power chip is provided for use in a power conversion device. The power conversion device further includes a power conversion circuit composed of a power switching transistor. The power chip is used to receive the output voltage feedback signal of the power conversion circuit. The power chip is also used to send a conduction time control signal to the power switching transistor. The conduction time control signal is used to control the power switching transistor to conduct within a constant conduction time. The time period corresponding to the pulse width of the conduction time control signal is the conduction time of the power switching transistor. The first moment corresponding to the falling edge of the conduction time control signal is delayed by a first time period relative to the end time of the designed conduction time of the power switching transistor. The second moment corresponding to the rising edge of the conduction time control signal is delayed by a second time period relative to the start time of the designed conduction time of the power switching transistor. The second time period is used to compensate for the first time period. Attached Figure Description

[0027] Figure 1 A schematic block diagram of a DC-DC converter with fixed pulse control is shown.

[0028] Figure 2 The circuit architecture diagram of the chip that generates fixed-time pulse control and the corresponding timing diagram are shown.

[0029] Figure 3 A schematic diagram of the power conversion method 100 provided in this application is shown.

[0030] Figure 4 This is a schematic block diagram of an example of the power conversion device provided in this application.

[0031] Figure 5 A schematic block diagram of the control circuit 1 for a power conversion device provided in this application is shown.

[0032] Figure 6 A schematic block diagram and corresponding timing diagram of the control circuit 1-1 for a power conversion device provided in this application are shown.

[0033] Figure 7 A schematic block diagram and corresponding timing diagram of the control circuit 1-2 for a power conversion device provided in this application are shown.

[0034] Figure 8A schematic block diagram of the control circuit 2 for a power conversion device provided in this application is shown.

[0035] Figure 9 A schematic block diagram and corresponding timing diagram of the control circuit 2-1 for a power conversion device provided in this application are shown.

[0036] Figure 10 A schematic block diagram of the control circuit 2-2 provided in this application and its corresponding timing diagram are shown.

[0037] Figure 11 A schematic block diagram and corresponding timing diagram of an example of the timing logic module in control circuit 2-1 and control circuit 2-2 provided in this application are shown. Detailed Implementation

[0038] DC-DC chips involve a variety of chip control technologies, including control technologies that can generate fixed time pulses, such as COT control and constant off-time control.

[0039] Figure 1 A schematic block diagram of a DC-DC converter with fixed pulse control is shown. Figure 1 The illustrated DC-DC converter is applicable to various power conversion topologies, such as buck, boost, buck-boost, and inverter topologies. This application uses a DC-DC converter with COT control as an example, but it is also applicable to constant off-time control and other DC-DC architectures utilizing fixed pulse control.

[0040] like Figure 1 As shown, in the control circuit of the constant on-time controlled switching power supply, the constant on-time control circuit is shown in the box, and the circuit outside the box is the power conversion circuit. In the power conversion circuit, power transistors (power transistor Q1 and power transistor Q2) act as switches. The power conversion circuit converts the input voltage VIN into the output voltage V by turning the power transistors on and off. O To drive the load. The conduction time of Q1 is T. on I ripple For inductor current I Lo ripples, V ripple Output voltage V O ripples, V ref I is the internal reference voltage of the chip. load The load current is related to the capacitor C. oThe series resistor is the equivalent series resistance (ESR). In a constant on-time control circuit, the feedback received at the inverting input of the high-speed comparator is V. ripple The voltage at the non-inverting input terminal is V. ref The high-speed comparator outputs an error signal. This error signal, along with the signal output from the shielding time unit, is transmitted to the switching logic unit via an AND gate. The switching logic unit also receives pulse signals from the single-trigger circuit. Based on the received signals, the switching logic unit determines whether to output a driving high level (DRVH) or a driving low level (DRVL). When the switching logic unit outputs DRVH, Q1 is on and Q2 is off; when the switching logic unit outputs DRVL, Q2 is on and Q1 is off.

[0041] This COT control technology consists of a fixed T on The conduction time of Q1 is the starting point of one cycle. After this conduction time ends, V... ripple Ripple magnitude and internal reference voltage V ref The crossing of the two phases determines the turn-off time of Q1, completing one Q1 turn-on and turn-off cycle.

[0042] Figure 2 The diagram shows the chip circuit architecture and corresponding timing diagram for generating fixed-time pulse control. (Example) Figure 2 As shown in (a), the power switch can be understood as Figure 1 Q1 and Q2 in the example. Figure 2 In (a) of the above, the units or modules other than the power switching transistors are related to... Figure 1 The units or modules within the Chinese square correspond to each other. Specifically, Figure 2 In (a) logic unit #1 and Figure 1 The switching logic unit #1 corresponds to the power switch transistor, which is driven by the pulse width modulation (PWM) signal output by the logic unit #1. The PWM signal controls the power switch transistor to turn on or off. Figure 2 The error comparator in (a) and Figure 1 The high-speed comparator in the middle corresponds to the error comparator's inverting input receiving V. ripple The positive input voltage is V ref The output terminal outputs an error signal (ERR). Figure 2 The circuit in the dashed box in (a) is... Figure 1The single-trigger circuit corresponds to this. The circuit within the dashed box includes an inverter, an N-type metal-oxide-semiconductor field-effect transistor (MOSFET), capacitor C, the circuit's supply voltage (VCC), current source, and T. on Comparator #1. Figure 2 (b) shows a time pulse of the PWM signal. The width of this time pulse is the time required for the PWM signal to maintain a high level, or it can be understood as T. on The width of the time pulse is the time interval between the rising edge of the time pulse and the falling edge of the time pulse.

[0043] Combination Figure 2 In (a) and (b), it can be understood that the error comparator in the circuit architecture outputs an error signal, which is then processed by logic unit #1 to output a PWM signal. Logic unit #1 is also used to generate the rising and falling edges of the PWM signal's timing pulse. In digital circuits, the instant (moment) when a digital level transitions from low (digital "0") to high (digital "1") is called the rising edge. In digital circuits, the instant (moment) when a digital level transitions from high (digital "1") to low (digital "0") is called the falling edge. The processing delay of logic unit #1 is Td2. Figure 2 As can be seen from (b) above, the time difference between the rising edge of the PWM signal and the rising edge of the ERR signal is Td2. On one hand, the PWM signal is used to control the power switch's on / off state; on the other hand, the circuit within the dashed box receives the PWM signal and generates a signal that rises or falls linearly according to a fixed slope, T... on_RAMP . Figure 2 In (a) of T on_RAMP The following explanation uses an ascending ramp signal as an example. on_RAMP The moment it begins to rise is also the moment corresponding to the rising edge of the PWM signal. T on_RAMP With T on_REF The circuit output T in the crossover trigger dashed box on_pulse Signal. Output T from the circuit within the dashed box. on_pulse The signal timing is when logic #1 unit receives T. on_pulse The delay between the two times is Td2, or, logic #1 unit processes T. on_pulse The signal delay is Td2. From Figure 2 As can be seen from (b) in the text, T on_pulseThe time difference between the rising edge of the signal and the falling edge of the PWM signal is Td2. Specifically, in the circuit within the dashed box, this difference needs to be determined by Td2. on Comparator #1 for T on_RAMP With T on_REF By comparing the potentials, T can be determined. on_RAMP With T on_REF Whether or not there is an overlap. T on The delay of comparator #1 is Td1. From Figure 2 As can be seen from (b) in the text, T on_RAMP With T on_REF The moment of crossing and T on_pulse The time difference between the rising edges of the two edges is Td1. Where T... on_REF Satisfy the following formula:

[0044] T on_REF =V ref • Duty Cycle (Formula 1). Where Duty Cycle is... Specifically, in the circuit within the dashed box, the PWM signal is inverterized to generate a reset signal. An N-type metal-oxide-semiconductor field-effect transistor (MOSFET) is connected in parallel with capacitor C. The N-type MOSFET receives the reset signal, and the voltage V across capacitor C is... C It increases linearly with a fixed slope. on The input signal at the positive input terminal of comparator #1 is T on_RAMP T on_RAMP This is the voltage signal across capacitor C, which appears as a rising slope signal. The circuit supplied by the current source has I = V. ref / R, where R is the resistance value of the current source; Figure 2 The voltage value of VCC in the middle is V VCC In one possible implementation, VCC in this application can be replaced with the chip's operating voltage, such as the drain power voltage (VDD), where the chip's operating voltage is V. VDD Accordingly, V in this application VCC It can be replaced with V VDD .

[0045] based on Figure 2 The circuit architecture shown has a preset conduction time, namely T. ideal It satisfies the following formula: T ideal = R·C·Duty Cycle (Formula 2). Where R is the resistance of the current source, and C is the resistance of the current source. on_RAMPThe capacitance value, R and C are both fixed values ​​preset internally by the chip, and the Duty Cycle is... It is understandable that when designing the above circuit architecture, the circuit parameters are known to the designer. These circuit parameters include, but are not limited to, resistance, capacitance, inductance, and voltage. IN V O As shown in Formula 2, the preset conduction time can be determined based on R, C, and V. IN V O The preset on-time can be understood as the time during which the PWM signal remains at a high potential when the circuit is in an ideal state (e.g., no time delay). Furthermore, the start and end times of the preset on-time corresponding to one or more pulses of the PWM signal can also be obtained through calculation or simulation.

[0046] In the circuit architecture described above, the conduction time, i.e., T on It satisfies the following formula: T on = R·C·Duty Cycle + Td1 + Td2 (Formula 3). Where R is the resistance of the current source, C is the resistance of the current source, and Td1 is the current generated by the current source. on_RAMP The capacitance value, R and C are both fixed values ​​preset internally by the chip, and the Duty Cycle is... Therefore, according to V O and V IN Send change, T on The value will also change accordingly. The conduction time can be understood as the time during which the PWM signal is maintained at a high level in the specific implementation.

[0047] Combining formulas 2 and 3, it can be seen that the conduction time, affected by delay times Td1 and Td2, will be longer than the preset conduction time, thus leading to a decrease in the switching frequency accuracy of the DC-DC converter. Furthermore, the switching frequency accuracy also varies with... Variations in temperature, manufacturing process, etc. Insufficiently low switching frequency accuracy can easily lead to excessive ripple, large fluctuations in efficiency and thermal performance in DC-DC products, or negatively impact the load circuitry downstream of the power supply (which is sensitive to frequency accuracy).

[0048] In view of this, the power conversion method and apparatus provided in this application can improve the accuracy of switching frequency.

[0049] Figure 3 A schematic diagram of the power conversion method 100 provided in this application is shown. This method can be applied to a power conversion device, which includes a controller and a power conversion circuit; specifically, the controller and the power switching transistor of the power conversion circuit are connected. In one possible implementation, the power conversion device here can be understood as a DC-DC converter.

[0050] S101, the power conversion circuit sends an output voltage feedback signal to the controller, and the controller receives the output voltage feedback signal from the power conversion circuit accordingly.

[0051] In one possible implementation, the output voltage feedback signal can be understood as the V mentioned above. ripple .

[0052] S102, the controller sends a control signal to the power switch transistor, and the power switch transistor receives the control signal from the controller accordingly.

[0053] The control signal is used to control the power switch to conduct periodically for a constant time interval. The time interval between the first moment corresponding to the rising edge of a control signal pulse and the second moment corresponding to the falling edge of the pulse is the actual conduction time of the power switch within one cycle. The second moment is after the end of the preset conduction time corresponding to the pulse, and the first moment is after the start of the preset conduction time. The preset conduction time is the theoretical conduction time of the power switch within one cycle, determined by the circuit parameters of the controller and the power conversion circuit. For example, the determination method of the preset conduction time can be found in Formula 2. The time interval between the second moment and the end of the preset conduction time can be called the first time interval. In one possible implementation, the second moment can be understood as... Figure 2 The falling edge of the PWM signal in (b) is the time corresponding to the first time interval. Figure 2 In (b) of the diagram, Td1 and Td2. The first moment occurs after the start of the preset conduction time. It can be understood that this first moment is related to... Figure 2 The rising edge of the PWM signal in (b) differs in timing. Specifically, Figure 2 In (b) of the diagram, the rising edge of the PWM signal occurs at the same time as the start of the preset conduction time. In this case, the conduction time of the power switch (hereinafter referred to as conduction time #1 for convenience) is longer than the preset conduction time. However, the first moment occurs after the start of the preset conduction time. In this case, the conduction time of the power switch (i.e., the actual conduction time mentioned above, hereinafter referred to as conduction time #2 for convenience) is shorter than conduction time #1, and the influence of the first time period on the actual conduction time of the power switch is reduced, thereby improving the switching frequency accuracy. The time period between the first moment and the start of the preset conduction time can be called the second time period. In other words, the second time period can partially or completely compensate for the influence of the first time period on the actual conduction time.

[0054] In one possible implementation, the difference between the length of the first time period and the length of the second time period is less than or equal to a preset value. For example, the preset value is 5ms, and the second time period = the first time period ± 5ms. Alternatively, the preset value can be other specific values, which are not limited in this application. In another possible implementation, the error of the length of the second time period relative to the first time period is less than or equal to a preset value. This error can be understood as a relative error. For example, if the preset value is 5%, the absolute error of the second time period relative to the first time period is less than or equal to 5% of the first time period. Alternatively, the preset value can be other specific values, which are not limited in this application. By limiting the relationship between the lengths of the first and second time periods, the lengths of the first and second time periods can be made closer, allowing the actual conduction time of the power switch to be closer to the preset conduction time. This further reduces the impact of the second moment after the end of the preset conduction time on the actual conduction time, thereby further improving the switching frequency accuracy.

[0055] The following provides two possible implementations for method 100.

[0056] Implementation Method 1:

[0057] Step a1: The controller converts the output voltage feedback signal into an error signal, and then converts the error signal into a first pre-control signal and a second pre-control signal. The rising edge of the first pre-control signal corresponds to the same time as the start time of the preset conduction time.

[0058] Step a2: The controller converts the second pre-control signal into the first pre-compensation signal.

[0059] The time taken to convert the second pre-control signal into the first pre-compensation signal is the second time period.

[0060] Step a3: The controller determines the first moment based on the first pre-control signal and the first pre-compensation signal.

[0061] Understandably, the controller first acquires the second pre-control signal, and then acquires the first pre-compensation signal after the second time period. Subsequently, it determines the first moment based on the first pre-control signal and the first pre-compensation signal. Specifically, the first moment is the moment that is delayed by the second time period relative to the moment corresponding to the rising edge of the first pre-control signal.

[0062] In one possible implementation, the second time period includes a first compensation time period and a second compensation time period, and step a3 can be implemented according to the following steps.

[0063] Step a3-1: The controller determines the second pre-compensation signal based on the second pre-control signal and the first reference voltage.

[0064] The time between the rising edge of the second pre-compensation signal and the intersection of the second pre-control signal and the first reference signal is the first compensation time period.

[0065] Step a3-2: The controller converts the second pre-compensation signal into the first pre-compensation signal. The time taken to convert the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

[0066] In this possible implementation, when the second pre-control signal is a rising ramp voltage signal, 0V ≤ first reference voltage ≤ first threshold (condition 1). For example, the first threshold here can be a reference voltage close to 0V. Optionally, 0 < first reference voltage ≤ first threshold. For example, the first reference voltage can be 0.01V, 0.02V, or 0.015V, or other voltage values ​​that satisfy condition 1. Alternatively, when the second pre-control signal is a falling ramp voltage signal, the second threshold ≤ first reference voltage ≤ supply voltage (condition 2). Optionally, the second threshold ≤ first reference voltage < supply voltage. For example, the first reference voltage can be supply voltage -0.01V, -0.02V, or -0.015V, or other voltage values ​​that satisfy condition 2.

[0067] Implementation Method Two:

[0068] Step b1: The controller converts the output voltage feedback signal into a first control signal, determines a first moment based on the first control signal and a second reference voltage, and determines a second moment based on the first control signal and a third reference voltage.

[0069] The second reference voltage differs from the third reference voltage. The first moment is delayed by a second time interval relative to the moment when the first control signal and the second reference voltage intersect. The second moment is delayed by a first time interval relative to the moment when the first control signal and the third reference voltage intersect.

[0070] In one possible implementation, before the first time step, the reference voltage used for comparison with the first control signal is a second reference voltage. After the first time step and before the second time step, the reference voltage used for comparison with the first control signal is a third reference voltage. For example, the switching of the reference voltage is controlled by a controller.

[0071] In this possible implementation, if the first control signal is a rising ramp voltage signal, then 0V ≤ second reference voltage ≤ first threshold, and the third reference voltage > second reference voltage. Alternatively, if the first control signal is a falling ramp voltage signal, then the second threshold ≤ second reference voltage ≤ supply voltage, and the third reference voltage < second reference voltage. The explanations of the first and second thresholds can be found in the description of implementation method one.

[0072] Figure 4 This is a schematic block diagram of an example of the power conversion device provided in this application. Figure 10 As shown, the power conversion device includes a controller and a power conversion circuit. The controller here can be used to perform the method 100 described above.

[0073] For example, the power conversion device can be a product applied in different fields such as consumer electronics, mobile carriers, and information and communication technology. For instance, a mobile carrier can be a vehicle, in a broad sense, including transportation vehicles (such as commercial vehicles, passenger cars, motorcycles, flying cars, trains, etc.), industrial vehicles (such as forklifts, trailers, tractors, etc.), engineering vehicles (such as excavators, bulldozers, cranes, etc.), agricultural equipment (such as lawnmowers, harvesters, etc.), amusement equipment, toy vehicles, etc. This application does not specifically limit the type of vehicle. As another example, a mobile carrier can be a means of transportation such as an airplane or a ship.

[0074] For example, the method 100 described above can be performed by a power chip. Optionally, the power chip can be an unpackaged bare die. For example, the power chip here can also be replaced by a power package module or a power management unit.

[0075] The following provides possible examples of the control circuits corresponding to the controllers described in implementation methods one and two, respectively. Specifically, Figures 5 to 7 Corresponding to implementation method one, Figures 8 to 10 This corresponds to implementation method two.

[0076] Figure 5 A schematic block diagram of the control circuit 1 for a power conversion device provided in this application is shown. Figure 5As shown, control circuit 1 is connected to power conversion circuit. Control circuit 1 mainly includes compensation unit 11. Compensation unit 11 is used to receive the output voltage feedback signal of power conversion circuit. The output terminal of compensation unit 11 is connected to the power switch of power conversion circuit and is used to send a control signal to the power switch. The control signal is used to control the power switch to conduct within a constant conduction time, and the pulse width of the control signal corresponds to the conduction time #2 of the power switch. The conduction time of the power switch includes a first time period Td. Specifically, the second time #1 corresponding to the falling edge of the control signal is delayed by the first time period relative to the end time of the preset conduction time of the power switch. For example, the first time period here can be understood as Td1 and Td2 mentioned above. Compensation unit 11 is also used to obtain a second time period Tc based on the output voltage feedback signal. The second time period Tc is used to compensate for the first time period Td. Specifically, the first time #1 corresponding to the rising edge of the control signal is delayed by Tc. In other words, the first moment #1 corresponding to the rising edge of the control signal sent by the compensation unit is after the start time of the preset conduction time, and the time difference between the first moment #1 and the start time of the preset conduction time is equal to the second time period Tc.

[0077] Therefore, T on =T ideal +Td-Tc. Where T on For conduction time #2, T ideal The designed conduction time or the preset conduction time.

[0078] The above scheme reduces the impact of the first time period on the actual conduction time by partially or completely offsetting it with the second time period, thereby improving the switching frequency accuracy. In one possible implementation, the length of the second time period is equal to the length of the first time period, i.e., Tc = Td. Therefore, the length of conduction time #2 can be as close as possible to the designed conduction time (or the preset conduction time).

[0079] In one possible implementation, the compensation unit 11 includes a pre-control unit 111, a pre-compensation unit 112, and a timing logic unit 113. The timing logic unit involved in this application can be a logic unit that uses timing logic circuits to implement timing-related logic functions, such as a set-reset (SR) flip-flop, a D-type flip-flop, a single-trigger circuit, etc.

[0080] The pre-control unit 111 is used to receive error signals and send a first pre-control signal to the timing logic unit 113 and a second pre-control signal to the pre-compensation unit 112. The error signal is obtained based on the output voltage feedback signal. For example, the compensation unit 11 also includes an error processing module that receives the output voltage feedback signal from the power conversion circuit and sends the error signal to the pre-control unit 111. The first pre-control signal is the control signal before compensation, which can be understood as, for example, as... Figure 2 The PWM signal involved.

[0081] The pre-compensation unit 112 is used to receive the second pre-control signal, process the second pre-control signal to obtain the first pre-compensation signal, and send the first pre-compensation signal to the timing logic unit 113. The pre-compensation unit 112 processes the second pre-control signal for a second time period, and the rising edge of the first pre-control signal corresponds to the start time of the preset conduction time.

[0082] Optionally, the second time period Tc includes a first compensation time period Tc1 and a second compensation time period Tc2. The pre-compensation unit 112 includes a first pre-compensation module 1121 and a second pre-compensation module 1122. The first pre-compensation module 1121 receives a second pre-control signal and, after the second pre-control signal and the first reference voltage crossover, sends a second pre-compensation signal to the second pre-compensation module 1122. The time between the moment the first pre-compensation module 1121 sends the second pre-compensation signal and the moment the second pre-control signal crosses over to the first reference signal is the first compensation time period Tc1. The second pre-compensation module 1122 processes the second pre-compensation signal to obtain the first pre-compensation signal, and the time for the second pre-compensation module to process the second pre-compensation signal is the second compensation time period Tc2. Optionally, Td1 = Tc1, Td2 = Tc2.

[0083] Therefore, T on =T ideal +Td1+Td2-Tc1-Tc2. Where, T on For conduction time #2, T ideal The designed conduction time or the preset conduction time.

[0084] The timing logic unit 113 is used to receive a first pre-control signal, and after a second time period, to receive a first pre-compensation signal and send a control signal to the power switch. The timing logic unit 113 also obtains the time corresponding to the rising edge of the control signal based on the time corresponding to the rising edge of the first pre-control signal and the second time period. The output of the timing logic unit is connected to the power conversion circuit.

[0085] The following are combined with Figure 6 and Figure 7 , give Figure 5 Two possible specific examples. Among them, Figure 6 The following explanation uses the second pre-control signal as an example of an ascending ramp signal. Figure 7 The following explanation uses the second pre-control signal as a descending ramp signal as an example.

[0086] Figure 6 A schematic block diagram and corresponding timing diagram of the control circuit 1-1 for a power conversion device provided in this application are shown. Figure 6 As shown in (a), the control circuit 1-1 for the power conversion device can be understood as a specific example of the time delay compensation unit 1. Specifically, in the control circuit 1-1 for the power conversion device, the timing logic unit 113 is illustrated using an SR latch as an example; the pre-control unit 111 is illustrated using the circuit within the dashed box as an example; and the pre-compensation unit 112 is illustrated using a T... on The comparator #2 and logic #2 unit will be used as examples for explanation. Specifically, in the control circuit 1 for the power conversion device, the first pre-compensation unit 1121 and the second pre-compensation unit 1122 respectively use T on The comparator #2 and logic #2 unit will be used as examples for explanation. Additionally, the error processing unit in the control circuit 1 of the power conversion device will be explained using an error comparator. For example... Figure 6 As shown in (b) above, ERR and PWM old T on_pulse T on_REF#1 and T on_RAMP The signals can be found in the following references: Figure 2 The corresponding explanations for ERR, PWM, and T on_pulse T on_REF and T on_RAMP Description of signals such as...

[0087] like Figure 6 As shown in (a), in the control circuit 1-1 used for the power conversion device, except for the SR latch and T on For units or modules other than comparator #2 and logic #2, please refer to [link / reference]. Figure 2 The following is a description of the chip circuit controlled by the fixed-time pulse shown. The following mainly focuses on T. on The comparator #2, logic #2 unit, and SR latch are described in detail.

[0088] T on Comparator #2 and T on Comparator #1 uses the same circuitry and layout design, allowing the two comparators to produce mutually matched delay times. onThe delay time of comparator #2 is Tc1, T on The delay time of comparator #1 is Td1, where Td1 = Tc1. on Comparator #2 and T on The non-inverting input of comparator #1 is all input to T. on_RAMP T on The threshold of comparator #2 and T on The thresholds of comparator #1 are different, i.e., T on Comparator #2 and T on The voltages at the inverting input of comparator #1 are different. Specifically, T on The threshold of comparator #1, i.e., the T value at the inverting input terminal. on_REF#1 Determined according to Formula 3. And T on The threshold of comparator #2, i.e., the first reference voltage at the inverting input (i.e., T) on_REF#2 The following condition must be met: 0 ≤ first reference voltage ≤ first threshold (condition 1). In one possible implementation, the first threshold can be less than or equal to T. on_REF#1 For example, the first reference voltage can be less than or equal to T. on_REF#1 The voltage. In another possible implementation, the first reference voltage can be a reference voltage close to 0V. Optionally, 0 < first reference voltage ≤ first threshold. It is understood that T on Comparator #2 may experience offset in practical use. A first reference voltage > 0V can prevent T from being affected by this offset. on Comparator #2 cannot accurately determine T on_RAMP With T on_REF#2 At the moment of crossover, in other words, a first reference voltage > 0V can improve T. on Comparator #2 determines T on_RAMP With T on_REF#2 The accuracy of the crossing time. For example, the first reference voltage can be 0.01V, 0.02V, or 0.015V, or other voltage values ​​that satisfy condition 1.

[0089] Logic unit #2 and logic unit #1 use the same circuitry and layout design, allowing the two logic units to produce mutually matched delay times. The delay time of logic unit #2 is Tc2, and the delay time of logic unit #1 is Td2, where Tc2 = Td2.

[0090] The SR latch receives a reset input signal from logic unit #1 and a set input signal from logic unit #2, and determines the output PWM based on the reset input signal and the set input signal. newThe timing pulse. The function table of the SR latch timing is shown in Table 1. Different input timings of the Reset input and Set input of the SR latch determine whether the output is 0 or 1. Table 1 is described in detail below. In Table 1, the reset bar (RB) has a higher priority than the set bar (SB). For example, in the second and third rows of Table 1, if RB is a low-order reset or a low level, or in other words, the RB input is 0, then the Q output of the SR latch is 0. In the fourth row of Table 1, if RB is a high level and SB is a low-order set or a low level, then the Q output of the SR latch is 1. In the fifth row of Table 1, if both RB and SB inputs are high, the Q output retains the previous state.

[0091] Table 1

[0092] RB (Reset Input) SB (Set Input) Q(Output) 0 0 0 0 1 0 1 0 1 1 1 Previous state

[0093] It is understandable that the SR latch does not determine the PWM solely based on the time pulses input to the RB. new The rising edge of the PWM signal is not used to determine the PWM, but rather by combining the signals from the RB and SB inputs. new The rising edge of the signal. The signal input to RB is the PWM output from logic #1 unit. old The signal input to SB is composed of T. on The pre-compensation unit 11 of comparator #2 and logic #2 receives PWM. old Following the signal, the signal is output by logic unit #2. Because T on The delay times of comparator #2 and logic #2 unit are Tc1 and Tc2, respectively. The signal output by logic #2 unit is compared to the PWM signal. old The signal delay time is Tc1 + Tc2. It can be understood that T... on Comparator #2 and logic #2 unit determine PWM new The rising edge of the signal. For example... Figure 6 As shown in (b) above, PWM new The rising edge of the signal corresponds to the time T. on_RAMP With T on_REF#2 After the moment of crossing, and the difference between these two moments is Tc1+Tc2.

[0094] It is also understandable that T on_RAMP With T on_REF#2 Crossover triggered PWM new The falling edge of the signal, in other words, T on Comparator #1 and logic #1 unit determine the PWM new The falling edge of the signal. T onThe processing delay of comparator #1 and logic #1 unit is Td1+Td2.

[0095] Therefore, Tc1+Tc2 is used to cancel out part or all of the time in Td1+Td2, enabling PWM to new The corresponding T on_new The length should be as close as possible to the preset conduction time T. ideal The length of. Specifically, via T on Comparator #1 and T on Matching the delay time of comparator #2 can eliminate T on The effect of comparator #1 delay. By matching the delay times of logic #1 and logic #2, the effect of logic #1 delay can be eliminated.

[0096] Additionally, since logic #2 and logic #1 use the same circuitry and layout design, T on Comparator #2 and T on Comparator #1 uses the same circuit and layout design, resulting in a high degree of consistency in the compensation effect of the control circuit used in the power conversion device, which does not fluctuate with the influence of voltage, temperature, or process. Furthermore, the delay compensation unit provided in this application does not introduce additional engineering means (such as adjusting to internal parameter values, such as resistance values, capacitance values, or voltage values) or circuits (such as frequency locking loops), resulting in lower design complexity and circuit processing complexity.

[0097] Figure 7 A schematic block diagram and corresponding timing diagram of the control circuit 1-2 for a power conversion device provided in this application are shown. Figure 7 As shown in (a), the control circuit 1-2 for the power conversion device can be understood as a specific example of the delay compensation unit 1. In the delay compensation unit 1-2, the timing logic unit in the control circuit 1 for the power conversion device is illustrated using an SR latch as an example, and the pre-control unit in the control circuit 1 for the power conversion device is illustrated using... Figure 7 The circuit within the dashed box will be used as an example for explanation. The pre-compensation unit in the control circuit 1 of the power conversion device is described using T. on The comparator #2 and logic #2 unit will be used as examples for explanation. Specifically, in the control circuit 1 for the power conversion device, the first pre-compensation unit and the second pre-compensation unit are respectively based on T... on The comparator #2 and logic #2 unit will be used as examples for explanation. Additionally, the error processing unit in the control circuit 1 of the power conversion device will be explained using an error comparator. For example... Figure 7 As shown in (b) above, ERR and PWM old T on_pulse T on_REF#1 and Ton_RAMP The signals can be found in the following references: Figure 2 The corresponding explanations for ERR, PWM, and T on_pulse T on_REF and T on_RAMP Description of signals such as...

[0098] The difference between control circuit 1-2 for power conversion equipment and control circuit 1-1 for power conversion equipment is:

[0099] In the control circuit 1-1 used in the power conversion device, T on_RAMP For a rising ramp signal from low to high potential, T on_RAMP Voltage value = V C Therefore, T on_RAMP The initial voltage value is 0V. In the control circuit 1-2 used in the power conversion device, T on_RAMP For a falling-slope signal from high to low potential, T on_RAMP Voltage value = V VCC –V C Therefore, T on_RAMP The initial voltage value is V VCC .

[0100] In control circuit 1-1 for power conversion equipment, capacitor C and N-type MOSFET are grounded, and current source is connected to VCC; in control circuit 1-2 for power conversion equipment, capacitor C and N-type MOSFET are connected to VCC, and current source is grounded.

[0101] Compared to control circuit 1-1 for power conversion devices, control circuit 1-2 for power conversion devices has modified T. on The polarity of comparator #1. In the control circuit 1-2 used in the power conversion device, T... on The inverting input of comparator #1 is used to receive T. on_RAMP The voltage at the non-inverting input terminal is T. on_REF#1 T on_REF#1 It can be determined according to Formula 3.

[0102] Compared to control circuit 1-1 for power conversion devices, control circuit 1-2 for power conversion devices has modified T. on The polarity of comparator #2. In the control circuit 1-2 used in the power conversion device, T... on The inverting input of comparator #2 is used to receive T. on_RAMP The voltage at the non-inverting input terminal is the first reference voltage T. on_REF#2 T on_REF#2 Satisfying: Second threshold ≤ T on_REF#2 ≤V VCC(Condition 2). In one possible implementation, the second threshold here can be greater than or equal to T. on_REF#1 For example, the first reference voltage can be greater than or equal to T. on_REF#1 The voltage. In another possible implementation, T on_REF#2 It can be close to V VCC The reference voltage. Optionally, the second threshold ≤ T on_REF#2 <V VCC Understandably, T on Comparator #2 may have a bias in actual use; the first reference voltage is < V. VCC This can avoid T due to offset. on Comparator #2 cannot accurately determine T on_RAMP With T on_REF#2 The moment of crossing, in other words, the first reference voltage < V VCC Able to improve T on Comparator #2 determines T on_RAMP With T on_REF#2 The accuracy of the crossing timing. For example, the first reference voltage could be V. VCC -0.01V or V VCC -0.02V or V VCC -0.015V, or other voltage values ​​that satisfy condition 2.

[0103] Figure 8 A schematic block diagram of the control circuit 2 for a power conversion device provided in this application is shown. Figure 8 As shown, control circuit 2 is connected to the power conversion circuit. Control circuit 2 mainly includes control unit 21. Control unit 21 is used to receive the output voltage feedback signal from the power conversion circuit. Control unit 21 is connected to the power switch of the power conversion circuit and is also used to send control signals to the power switch. The control signal is used to control the power switch to conduct for a constant conduction time, and the pulse width of the control signal corresponds to the conduction time of the power switch. Control unit 21 is also used to determine the first time #2 corresponding to the rising edge of the control signal and the second time #2 corresponding to the falling edge of the control signal based on the output voltage feedback signal. The length of the first time period generated when control unit 21 determines the second time #2 is equal to the length of the second time period generated when control unit 21 determines the first time #2. It can be understood that the second time period here can be understood as the processing time required for control unit 21 to determine the rising edge of the control signal. The first time period here can be understood as the processing time required for control unit 21 to determine the falling edge of the control signal. Since the processing time of the same control unit 21 is fixed, the first time period = the second time period.

[0104] Therefore, Ton =T ideal Among them, T on For conduction time #2, T ideal This refers to the designed conduction time or the preset conduction time. Alternatively, the "=" here can be replaced with "≈".

[0105] The above scheme uses the same control unit 21 to determine the first time #2 corresponding to the rising edge of the control signal and the second time #2 corresponding to the falling edge, ensuring that the delay time generated when determining the first time #2 and the second time #2 is the same. Therefore, the length of the conduction time can be as close as possible to the designed conduction time (or the preset conduction time), thus avoiding the situation where the switching frequency accuracy is reduced due to an excessively long conduction time.

[0106] Control unit 21 is used to obtain a first control signal based on the output voltage feedback signal. Specifically, control unit 21 is used to obtain a first moment #2 after a second time period following the intersection of the first control signal and the second reference voltage. Exemplarily, the second time period includes a first delay time period and a second delay time period. Control unit 21 includes a first control module 211 and a second control module 212. First control module 211 is used to obtain the first control signal based on the output voltage feedback signal and send a second control signal based on the first control signal. Specifically, the moment after the intersection of the first control signal and the second reference voltage, following the first delay time period, is the moment corresponding to the rising edge of the i-th pulse of the second control signal, where i ≥ 1 and i is an integer. It can be understood that the first delay time period is the time required for first control module 211 to determine the intersection of the first control signal and the second reference voltage. Second control module 212 is used to receive the second control signal and send a control signal based on the second control signal. The moment after the rising edge of the i-th pulse of the second control signal, following the second delay time period, is the first moment #2. It can be understood that the second delay time period is the time required for first control module 211 to determine the first moment #2.

[0107] The control unit 21 is further configured to obtain the second time point #2 after a first time interval following the intersection of the first control signal and the third reference voltage. Specifically, the first time interval includes a third delay time interval and a fourth delay time interval. The control unit 21 includes a first control module 211 and a second control module 212. The first control module 211 is configured to obtain the first control signal based on the output voltage feedback signal and send the second control signal based on the first control signal. Specifically, the time after the intersection of the first control signal and the third reference voltage, following the third delay time interval, is the time corresponding to the rising edge of the (i+1)th pulse of the second control signal, where i ≥ 1 and i is an integer. It can be understood that the third delay time interval is the time required for the first control module 211 to determine the intersection of the first control signal and the third reference voltage. The second control module 212 is configured to receive the second control signal and send the control signal based on the second control signal. The time after the rising edge of the (i+1)th pulse of the second control signal, following the fourth delay time interval, is the second time point #2. It can be understood that the fourth delay time interval is the time required for the first control module 211 to determine the second time point #2. Optionally, the length of the first delay period is equal to the length of the third delay period; the length of the second delay period is equal to the length of the fourth delay period.

[0108] It is understood that the second reference voltage is different from the third reference voltage. Optionally, the control unit 21 further includes a third control module for providing the second reference voltage or the third reference voltage to the first control module. Specifically, the third control module is used to provide the second reference voltage to the first control module 211 before the first time #2; the third control module is also used to provide the third reference voltage to the first control module 211 after the first time #2 and before the second time #2.

[0109] Figure 9 A schematic block diagram and corresponding timing diagram of the control circuit 2-1 for a power conversion device provided in this application are shown. Figure 9 As shown in (a), control circuit 2-1 can be understood as a specific example of control circuit 2. In control circuit 2-1, the control unit 21 of control circuit 2 is illustrated using the circuit within the dashed box as an example. Specifically, the first control module 211 and the second control module 212 in control circuit 2 are respectively represented by T... on The following explanation uses comparator #3 and the sequential logic module as examples. Optionally, if the control circuit 2 includes a third control module, the third control module will be explained using the two transmission gates within the dashed box as examples. Figure 9 As shown in (b) above, ERR and PWM old and T on_RAMP The signals can be found in the following references: Figure 2The corresponding explanations for ERR, PWM, and T on_RAMP Description of signals such as [signals]. The second control signal involved in control circuit 2 is [signal name]. Figure 9 T in on_pulse Taking this as an example, the i-th time pulse of the second control signal is T. on_pulse#1 The (i+1)th time pulse of the second control signal is T on_pulse#2 The second reference voltage involved in control circuit 2 is T on_REF#4 Taking T as an example, the third reference voltage involved in control circuit 2 is described as T on_REF#3 Let's take an example to illustrate.

[0110] like Figure 9 As shown in (a) above, in control circuit 2-1, except for T on Comparator #3, the sequential logic module, and all units or modules other than the two transmission gates can be found in [reference needed]. Figure 2 The following is a description of the chip circuit controlled by the fixed-time pulse shown. The following mainly focuses on T. on The comparator #3, the sequential logic module, and the two transmission gates are described in detail.

[0111] T on The non-inverting input of comparator #3 is all input to T. on_RAMP T on The inverting input of comparator #3 can be set with multiple different thresholds, or in other words, T on The inverting input of comparator #3 can accept multiple different voltages. Figure 9 In (a) of the middle, T on Comparator #3 can accept two different input voltages, namely T on_REF#3 and T on_REF#4 Let's take an example to illustrate. During the first time period, T... on The voltage input to the inverting input terminal of comparator #3 is T. on_REF#4 T on_REF#4 Satisfy: 0≤T on_REF#4 ≤ First threshold (Condition 3). Regarding T on_REF#4 For a detailed explanation of condition 3 and the first threshold, please refer to section 1-1 of the control circuit for T. on_REF#2 The difference between the description of condition 1 and the first threshold is that T... on_REF#2 Replace with T on_REF#4 Replace condition 1 with condition 3. The start time of this first time period can be... Figure 9 PWM in (b) new The time corresponding to the falling edge of the time pulse of the previous cycle, or after that time. The end time of this first period is... Figure 9 PWM in (b) newThe rising edge of the current period's time pulse corresponds to the time of the first moment #2. During the second time period, T... on The voltage input to the inverting input terminal of comparator #3 is T. on_REF#3 T on_REF#3 Satisfying: Second threshold ≤ T on_REF#3 ≤V VCC (Condition 4). Regarding T on_REF#3 For details regarding condition 4 and the second threshold, please refer to section 1-2 of the control circuit for T. on_REF#2 The difference between condition 2 and the description of the second threshold is that T... on_REF#2 Replace with T on_REF#3 Replace condition 2 with condition 4. The start time of this second time period is the first time period #2. The end time of this second time period is... Figure 9 PWM in (b) new The time corresponding to the falling edge of the current period's time pulse, i.e., the second time #2. Let T... on Comparator #3 and Figure 2 T in on Taking the comparator using the same circuit and layout design as an example, T on The processing delay of comparator #3 is Td1. Additionally, T... on_REF#3 and T on_REF#4 Satisfy: T on_REF#3 >T on_REF#4 (Condition 5)

[0112] The main function of the timing logic module is to target T on The pulse output from comparator #3 is used for logical judgment to determine the first time step #2 and the second time step #2. The processing delay of the sequential logic module is Td3. The following will combine... Figure 11 The implementation method of the timing logic module is explained.

[0113] In control circuit 2-1, two transmission gates, T, are used. on Comparator #3 provides T on_REF#4 and T on_REF#3 Implemented in PWM new The rising and falling edges of the transmission gates are used to switch different reference voltages. For example, in PWM... new The rising edge timing logic module is triggered to provide T on_REF#4 The transmission gate is turned on, for example in PWM. new The falling edge timing logic module is triggered to provide T on_REF#3 The transmission gate is turned on. Figure 9 In the circuit within the dashed box in (a) of the diagram, the inverter ensures that at most one of the two transmission gates is conducting at any given time.

[0114] In addition, Figure 9 In (a) of the diagram, logic unit #1 is not connected to the power switch, but is connected to the sequential logic module. Logic unit #1 outputs PWM. old Signals and PWM RB Signals. Among them, PWM old Signals are used to control T on_RAMP The start and end of the signal's time pulse. Specifically, logic unit #1 processes the error signal output by the error comparator to determine T. on_RAMP The start of the signal's time pulse, i.e., PWM. old The time corresponding to the rising edge of the signal is T. on_RAMP The moment the signal begins to rise. The sequential logic module sends T to logic unit #1. on_Reset Signal, logic #1 unit according to T on_Reset Signal Determination PWM old The falling edge of the signal is used to determine T. on_RAMP The signal ends at the moment when logic unit #1 sends a PWM signal to the timing logic module. RB PWM RB Can be used with PWM old It's the same signal, or PWM. RB It can be PWM old The signal obtained after error processing. In PWM old When the signal is at a low level, PWM RB The signal is used to reset the sequential logic module.

[0115] Figure 10 A schematic block diagram and corresponding timing diagram of the control circuit 2-2 provided in this application are shown. Figure 10 As shown in (a), control circuit 2-2 can be understood as a specific example of control circuit 2. In control circuit 2-2, the control unit 21 in control circuit 2 is illustrated using the circuit within the dashed box as an example. Specifically, the first control module 211 and the second control module 212 in control circuit 2 are respectively represented by T... on The following explanation uses comparator #3 and the sequential logic module as examples. Optionally, if the control circuit 2 includes a third control module, the third control module will be explained using the two transmission gates within the dashed box as examples. Figure 10 As shown in (b) above, ERR and PWM old and T on_RAMP The signals can be found in the following references: Figure 2 The corresponding explanations for ERR, PWM, and T on_RAMP Description of signals such as [signals]. The second control signal involved in control circuit 2 is [signal name]. Figure 9 T inon_pulse Taking this as an example, the i-th time pulse of the second control signal is T. on_pulse#1 The (i+1)th time pulse of the second control signal is T on_pulse#2 The second reference voltage involved in control circuit 2 is T on_REF#4 Taking T as an example, the third reference voltage involved in control circuit 2 is described as T on_REF#3 Let's take an example to illustrate.

[0116] The difference between control circuit 2-2 and control circuit 1-1 is:

[0117] In control circuit 2-1, T on_RAMP For a rising ramp signal from low to high potential, T on_RAMP Voltage value = V C Therefore, T on_RAMP The initial voltage value is 0V. In control circuit 2-2, T on_RAMP For a falling-slope signal from high to low potential, T on_RAMP Voltage value = V VCC –V C Therefore, T on_RAMP The initial voltage value is V VCC .

[0118] In control circuit 2-1, capacitor C and N-type MOSFET are grounded, and the current source is connected to VCC; in control circuit 2-2, capacitor C and N-type MOSFET are connected to VCC, and the current source is grounded.

[0119] Compared to control circuit 2-1, control circuit 2-2 modifies T. on The polarity of comparator #3. In control circuit 2-2, T on The inverting input of comparator #3 is used to receive T. on_RAMP The voltage at the non-inverting input terminal is T. on_REF#3 or T on_REF#4 T in control circuit 2-2 on_REF#3 Condition 4 is satisfied, T on_REF#4 Condition 3 is satisfied, T on_REF#3 and T on_REF#4 Satisfy: T on_REF#3 <T on_REF#4 (Condition 6)

[0120] Figure 11 A schematic block diagram and corresponding timing diagram of an example of the timing logic module in control circuit 2-1 and control circuit 2-2 provided in this application are shown.

[0121] like Figure 11As shown in (a), the sequential logic module may include three D flip-flops and one SR latch. The two inputs of the sequential logic module receive PWM signals respectively. RB Signal and T on_pulse The signal and timing logic module outputs PWM signals at its two output terminals respectively. new Signal and T on_Reset Signal. For ease of explanation, the three D flip-flops from left to right are referred to as D flip-flop #1, D flip-flop #2, and D flip-flop #3, respectively. For the three D flip-flops, the input V at the data (D) terminal is a logic high level, i.e., V = 1, which can be, for example, the power supply voltage on the chip.

[0122] The D flip-flop #1 receives a clock pulse (CP) input. on_pulse Signal, in T on_pulse#1 At the rising edge of the circuit, the output Q of D flip-flop #1 is also logically high, Q1 = 1, and the output of D flip-flop #1... The voltage is low, Q1B = 0. The CP input of D flip-flop #2 receives T. on_pulse Signal, in T on_pulse#1 At the rising edge of the signal, since D flip-flop #2 has not yet received the Q1 signal from D flip-flop #1, the D terminal of D flip-flop #2 is still at a low potential, i.e., the input is 0; therefore, the output Q of D flip-flop #2 is also logically low, Q2 = 0, Q2B = 1. The CP input terminal of D flip-flop #3 receives the T signal. on_pulse The signal after being processed by the inverter, at T on_pulse#1 At the rising edge of the signal, the Q output of D flip-flop #3 is logically low, Q3 = 0. The inputs of the NOR gate are Q1B, Q2, and Q3, and the output is the Set signal. From the above, it can be seen that at T... on_pulse#1 At the rising edge of the signal, Q1B = 0, Q2 = 0, and Q3 = 0, thus the Set signal output by the NOR gate is logically high. The inputs of the AND gate are Q2 and PWM. RB The output is a Reset signal. As can be seen from the above, at T... on_pulse#1 At the moment corresponding to the rising edge of the signal, Q2 = 0, thus the Reset signal is logically low. For example... Figure 11 As shown in (b) above, T on_pulse#1 The rising edge of the signal corresponds to the rising edge of the Set signal at the same time. For the SR latch, the Set signal is input at the S terminal, the Reset signal is input at the R terminal, and the PWM signal is output at the Q terminal. new Signals. The Set signal is high, the Reset signal is low, and the PWM signal is active. new The signal is high. For example... Figure 11 As shown in (b) above, PWM newThe rising edge of the signal corresponds to the time T. on_pulse#1 The time difference between the rising edge and the time corresponding to the rising edge is Td3, which can be understood as the processing delay of the SR latch.

[0123] In T on_pulse#2 At the rising edge of the signal, D flip-flop #2 has received Q1, meaning the D input is high and the Q2 output is also high (Q2 = 1). The inputs to the NOR gate are Q1B, Q2, and Q3, and the output is the Set signal. When Q2 = 1, the Set signal is low. The inputs to the AND gate are Q2 and PWM. RB The output is a Reset signal. Due to PWM... RB If the current level is high, then the Reset signal is also high. For the SR latch, the S terminal receives the Set signal, the R terminal receives the Reset signal, and the Q terminal outputs PWM. new Signals. The Set signal is low, the Reset signal is high, and the PWM signal is low. new The signal is low. For example... Figure 11 As shown in (b) above, PWM new The falling edge of the signal corresponds to the time T on_pulse#2 The time difference between the rising edge and the time corresponding to the rising edge is Td3, which can be understood as the processing delay of the SR latch.

[0124] The output of the AND gate also outputs T. on_Reset Signal, T on_Reset Signal used to trigger PWM old The falling edge of the signal. (By PWM) old PW obtained from the signal RB The signal is used to reset the three D flip-flops.

[0125] It should be noted that the timing logic modules in control circuit 2-1 and control circuit 2-2 can also be implemented by other design methods that achieve similar functions, and this application does not limit this.

Claims

1. A power conversion device, characterized in that, The power conversion device includes a controller and a power conversion circuit, wherein the controller is connected to the power switching transistor of the power conversion circuit; The controller is used to receive the output voltage feedback signal from the power conversion circuit; The controller is further configured to send a control signal to the power switch, the control signal being configured to control the power switch to periodically conduct for a constant time period, wherein the time period between the first moment corresponding to the rising edge of a pulse of the control signal and the second moment corresponding to the falling edge of the pulse is the actual conduction time of the power switch in one cycle. The second time point is after the end of the preset conduction time corresponding to the pulse, and the first time point is after the start of the preset conduction time. The preset conduction time is the theoretical conduction time of the power switch in one cycle, which is determined according to the circuit parameters of the controller and the power conversion circuit.

2. The power conversion device according to claim 1, characterized in that, The time period between the second time point and the end time point is the first time period, the time period between the first time point and the start time point is the second time period, and the difference between the length of the first time period and the length of the second time period is less than or equal to a preset value.

3. The power conversion device according to claim 2, characterized in that, The controller is further configured to convert the output voltage feedback signal into an error signal, and convert the error signal into a first pre-control signal and a second pre-control signal, wherein the rising edge of the first pre-control signal corresponds to the same time as the start time of the preset conduction time. The controller is further configured to convert the second pre-control signal into a first pre-compensation signal, wherein the time for converting the second pre-control signal into the first pre-compensation signal is the second time period; The controller is further configured to determine the first moment based on the first pre-control signal and the first pre-compensation signal.

4. The power conversion device according to claim 3, characterized in that, The second time period includes the first compensation time period and the second compensation time period. The controller is specifically used to determine a second pre-compensation signal based on the second pre-control signal and the first reference voltage, wherein the time between the rising edge of the second pre-compensation signal and the time when the second pre-control signal and the first reference signal intersect is the first compensation time period; The controller is specifically configured to convert the second pre-compensation signal into the first pre-compensation signal, and the time for converting the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

5. The power conversion device according to claim 4, characterized in that, When the second pre-control signal is a rising ramp voltage signal, 0V ≤ the first reference voltage ≤ the first threshold; or, When the second pre-control signal is a falling slope voltage signal, the second threshold ≤ the first reference voltage ≤ the supply voltage.

6. The power conversion device according to claim 2, characterized in that, The controller is configured to convert the output voltage feedback signal into a first control signal, determine the first moment based on the first control signal and a second reference voltage, and determine the second moment based on the first control signal and a third reference voltage. Wherein, the second reference voltage is different from the third reference voltage, the first moment is delayed by the second time period relative to the moment when the first control signal and the second reference voltage intersect, and the second moment is delayed by the first time period relative to the moment when the first control signal and the third reference voltage intersect.

7. The power conversion device according to claim 6, characterized in that, Before the first moment, the reference voltage used for comparison with the first control signal is the second reference voltage; The reference voltage used for comparison with the first control signal after the first time point and before the second time point is the third reference voltage.

8. The power conversion device according to claim 6 or 7, characterized in that, When the first control signal is a rising ramp voltage signal, 0V ≤ the second reference voltage ≤ the first threshold, and the third reference voltage > the second reference voltage; or, When the first control signal is a falling slope voltage signal, the second threshold ≤ the second reference voltage ≤ the supply voltage, and the third reference voltage < the second reference voltage.

9. A power conversion method, applied to a controller in a power conversion device, the power conversion device further comprising a power conversion circuit, the controller being connected to a power switching transistor of the power conversion circuit, characterized in that, include: Receive the output voltage feedback signal of the power conversion circuit; A control signal is sent to the power switch, the control signal being used to control the power switch to be turned on periodically for a constant time period. The time period between the first moment corresponding to the rising edge of a pulse of the control signal and the second moment corresponding to the falling edge of the pulse is the actual time the power switch is turned on in one cycle. The second time point is after the end of the preset conduction time corresponding to the pulse, and the first time point is after the start of the preset conduction time. The preset conduction time is the theoretical conduction time of the power switch in one cycle, which is determined according to the circuit parameters of the controller and the power conversion circuit.

10. The method according to claim 9, characterized in that, The time period between the second time point and the end time point is the first time period, the time period between the first time point and the start time point is the second time period, and the difference between the length of the first time period and the length of the second time period is less than or equal to a preset value.

11. The method according to claim 10, characterized in that, The method further includes: The output voltage feedback signal is converted into an error signal, and the error signal is converted into a first pre-control signal and a second pre-control signal. The time period corresponding to the pulse width of the first pre-control signal is equal to the preset on-time of the power switch. The second pre-control signal is converted into a first pre-compensation signal, wherein the time for converting the second pre-control signal into the first pre-compensation signal is the second time period; The control signal is determined based on the first pre-control signal and the first pre-compensation signal.

12. The method according to claim 11, characterized in that, The second time period includes a first compensation time period and a second compensation time period, and the method further includes: The second pre-compensation signal is determined based on the second pre-control signal and the first reference voltage, wherein the time between the rising edge of the second pre-compensation signal and the time when the second pre-control signal and the first reference signal intersect is the first compensation time period. The second pre-compensation signal is converted into the first pre-compensation signal, and the time for converting the second pre-compensation signal into the first pre-compensation signal is the second compensation time period.

13. The method according to claim 12, characterized in that, When the second pre-control signal is a rising ramp voltage signal, 0V ≤ the first reference voltage ≤ the first threshold; or, When the second pre-control signal is a falling slope voltage signal, the second threshold ≤ the first reference voltage ≤ the supply voltage.

14. The method according to claim 10, characterized in that, The method further includes: The output voltage feedback signal is converted into a first control signal, and the first moment is determined based on the first control signal and the second reference voltage, and the second moment is determined based on the first control signal and the third reference voltage. Wherein, the second reference voltage is different from the third reference voltage, the first moment is delayed by the second time period relative to the moment when the first control signal and the second reference voltage intersect, and the second moment is delayed by the first time period relative to the moment when the first control signal and the third reference voltage intersect.

15. The method according to claim 14, characterized in that, Before the first moment, the reference voltage used for comparison with the first control signal is the second reference voltage; The reference voltage used for comparison with the first control signal after the first time point and before the second time point is the third reference voltage.

16. The method according to claim 14 or 15, characterized in that, When the first control signal is a rising ramp voltage signal, 0V ≤ the second reference voltage ≤ the first threshold, and the third reference voltage > the second reference voltage; or, When the first control signal is a falling slope voltage signal, the second threshold ≤ the second reference voltage ≤ the supply voltage, and the third reference voltage < the second reference voltage.

17. A power chip, used in a power conversion device, the power conversion device further comprising a power conversion circuit composed of power switching transistors, characterized in that, include: The power chip is used to receive the output voltage feedback signal of the power conversion circuit; The power chip is further configured to send a conduction time control signal to the power switch transistor. The conduction time control signal is used to control the power switch transistor to conduct for a constant conduction time. The pulse width of the conduction time control signal corresponds to the time period of the power switch transistor's conduction time. Wherein, the first moment corresponding to the falling edge of the conduction time control signal is delayed by a first time period relative to the end time of the designed conduction time of the power switch, and the second moment corresponding to the rising edge of the conduction time control signal is delayed by a second time period relative to the start time of the designed conduction time of the power switch, and the second time period is used to compensate for the first time period.

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