Analog-to-digital conversion circuit and method with remaining time measurement mechanism

Abstract

The present application relates to an analog-to-digital conversion circuit and method with a remaining time measurement mechanism. An analog-to-digital conversion circuit with a remaining time measurement mechanism. The digital-to-analog conversion circuit samples the positive and negative input voltages and outputs a positive output voltage and a negative output voltage. A comparator compares the positive and negative output voltages to generate a comparison result. A control circuit switches the configuration of the digital-to-analog conversion circuit using a digital code based on the comparison result. After the comparison result is generated, the comparison judgment circuit places a stage indication signal in a completion state. The comparison stage counting circuit accumulates the number of completions based on the stage indication signal, so that the conversion indication signal is in a completion state after reaching a preset number. The time accumulation circuit starts accumulating the remaining time when the conversion indication signal is in the completion state, and completes the accumulation when the sampling indication signal is in the sampling state.

Description

Technical Field

[0001] The present invention relates to analog-to-digital conversion technology, and more particularly to an analog-to-digital conversion circuit and method with a residual time measurement mechanism. Background Art

[0002] Analog-to-digital conversion circuits convert continuous analog signals or physical quantities (usually voltage) into digital signals. Analog-to-digital conversion circuits can be implemented using a variety of different architectures. Among them, continuous and progressive analog-to-digital conversion circuits rely on different configurations of digital-to-analog circuits and the operation of comparators to process and compare the input analog signals, thereby achieving the purpose of tracking the input signal. However, the operating time of digital-to-analog circuits and comparators often varies due to factors such as temperature, process, and voltage. Operating times that are too close to or too far from the system's set conversion time can result in poor performance. Summary of the Invention

[0003] In view of the problems of the prior art, one object of the present invention is to provide an analog-to-digital conversion circuit and method with a residual time measurement mechanism to improve the prior art.

[0004] The present invention includes an analog-to-digital conversion (ADC) circuit with a remaining time measurement mechanism, comprising: a digital-to-analog conversion circuit, a comparator, a control circuit, a comparison judgment circuit, a comparison stage counting circuit, and a time accumulation circuit. The digital-to-analog conversion circuit samples the positive input voltage and the negative input voltage when a sampling indication signal is in a sampling state, and outputs a positive output voltage and a negative output voltage when the sampling indication signal is in a sampling completion state. The comparator compares the positive output voltage and the negative output voltage in a plurality of comparison stages to generate a comparison result, wherein the number of comparison stages is a predetermined number. The control circuit switches the configuration of the digital-to-analog conversion circuit using a set of digital codes based on the comparison result in each comparison stage, and outputs the corresponding digital code as a digital output signal when a conversion completion condition is met. The comparison judgment circuit sets the stage indication signal to a comparison stage incomplete state before a comparison result is generated in each comparison stage, and sets the stage indication signal to a comparison stage complete state after a comparison result is generated. The comparison stage counting circuit accumulates the number of completions during each comparison stage when the stage indication signal is in the comparison stage completion state. When the number of completions reaches a preset number, the conversion indication signal is set to the conversion incomplete state. After reaching the preset number, the conversion indication signal is set to the conversion complete state. The time accumulation circuit begins accumulating the remaining time when the conversion indication signal is in the conversion complete state and completes the accumulation the next time the sampling indication signal is in the sampling state.

[0005] The present invention also includes an analog-to-digital conversion method with a remaining time measurement mechanism, comprising: causing a digital-to-analog conversion circuit to sample a positive input voltage and a negative input voltage when a sampling indication signal is in a sampling state, and outputting a positive output voltage and a negative output voltage when the sampling indication signal is in a sampling completion state; causing a comparator to compare the positive output voltage and the negative output voltage in each of a plurality of comparison stages to generate a comparison result, wherein the number of comparison stages is a preset number; causing a control circuit to switch the configuration of the digital-to-analog conversion circuit with a set of digital codes according to the comparison result in each comparison stage, and outputting a corresponding digital code as a digital code when a conversion completion condition is met. a word output signal; causing the comparison judgment circuit to set the stage indication signal to a comparison stage incomplete state before a comparison result is generated in each comparison stage, and to set the stage indication signal to a comparison stage complete state after the comparison result is generated; causing the comparison stage counting circuit to accumulate the number of completions when the stage indication signal is in the comparison stage complete state in each comparison stage, and to set the conversion indication signal to a conversion incomplete state before the number of completions reaches a preset number, and to set the conversion indication signal to a conversion complete state after the number reaches the preset number; and causing the time accumulation circuit to start accumulating the remaining time when the conversion indication signal is in the conversion complete state, and to complete the accumulation when the sampling indication signal is in the sampling state next time.

[0006] The features, implementation and effects of the present application are described in detail below with reference to preferred embodiments with reference to the drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] [ Figure 1 ] shows a block diagram of an analog-to-digital conversion circuit with a remaining time measurement mechanism in one embodiment of the present invention;

[0008] [ Figure 2 ] shows a circuit diagram of a comparator in one embodiment of the present invention;

[0009] [ Figure 3 ] shows a circuit diagram of a comparison phase counting circuit in one embodiment of the present invention;

[0010] [ Figure 4 ] shows a circuit diagram of a time accumulation circuit in one embodiment of the present invention; and

[0011] [ Figure 5 ] shows a flow chart of an analog-to-digital conversion method with a residual time measurement mechanism in one embodiment of the present invention. DETAILED DESCRIPTION

[0012] An object of the present invention is to provide an analog-to-digital conversion circuit and method with a residual time measurement mechanism. The residual time difference between the system's set conversion time and the actual operating time is measured, thereby adjusting system operating parameters based on the residual time to improve the performance of the analog-to-digital conversion circuit.

[0013] Please refer to Figure 1 . Figure 1 FIG2 is a block diagram illustrating an analog-to-digital conversion circuit 100 with a remaining time measurement mechanism according to an embodiment of the present invention. The analog-to-digital conversion circuit 100 includes a digital-to-analog conversion circuit 110, a comparator 120, a control circuit 130, a comparison determination circuit 140, a comparison phase counter circuit 150, and a time accumulation circuit 160.

[0014] In operation, each time the digital-to-analog conversion circuit 110 performs an analog-to-digital conversion, it samples the positive input voltage Vip and the negative input voltage Vin and outputs a positive output voltage Va and a negative output voltage Vb. The comparator 120 compares the positive output voltage Va with the negative output voltage Vb to generate a comparison result CR. The control circuit 130 generates a digital code DC based on the comparison result CR to switch the configuration of the digital-to-analog conversion circuit 110.

[0015] The digital-to-analog converter circuit 110, the comparator 120, and the control circuit 130 form a loop to repeatedly perform the above-mentioned process in multiple comparison phases. When the conversion completion condition is met, the control circuit 130 outputs the corresponding digital code DC as the digital output signal DOUT.

[0016] The number of comparison phases is a fixed, preset number. When the analog-to-digital conversion circuit 100 executes the preset number of comparison phases, one analog-to-digital conversion is completed. Therefore, in one embodiment, when the difference between the positive output voltage Va and the negative output voltage Vb is less than a preset level and the number of comparison phases completed reaches a preset number, the control circuit 130 determines that the conversion completion condition is met and outputs the corresponding digital code DC as the digital output signal DOUT.

[0017] In one embodiment, the aforementioned preset level is the amount of the least significant bit (LSB).

[0018] The analog-to-digital conversion circuit 100 system sets a conversion time to perform analog-to-digital conversion within each conversion time. However, the actual operation time required for the circuit elements included in the analog-to-digital conversion circuit 100 to generate a conversion result through comparison and switching is not equal to the conversion time and varies with factors such as temperature, voltage, and process. The comparison and judgment circuit 140, the comparison stage counter circuit 150, and the time accumulation circuit 160 operate to measure the remaining time RT between the conversion time and the actual operation time.

[0019] The operation of each circuit element in the analog-to-digital conversion circuit 100 will be described in more detail below.

[0020] The digital-to-analog conversion circuit 110 samples the positive input voltage Vip and the negative input voltage Vin when the sampling indication signal SIS is in the sampling state, and outputs the positive output voltage Va and the negative output voltage Vb when the sampling indication signal SIS is in the sampling completion state. The sampling indication signal SIS can be generated by, for example, but not limited to, a circuit external to the analog-to-digital conversion circuit 100.

[0021] In one embodiment, the digital-to-analog conversion circuit 110 may include, for example, but not limited to, a positive capacitor array, a negative capacitor array, and a switching circuit (not shown), and the positive capacitor array and the negative capacitor array may be connected to the analog signal source via a switch Sip and a switch Sin, respectively.

[0022] In one embodiment, the sampling state of the sampling indication signal SIS is high, and the sampling completion state is low. The sampling state of the sampling indication signal SIS enables switches Sip and Sin, allowing the positive capacitor array and the negative capacitor array to receive the positive input voltage Vip and the negative input voltage Vin, respectively. The sampling completion state of the sampling indication signal SIS disables switches Sip and Sin, disconnecting the positive capacitor array and the negative capacitor array from the analog signal source, respectively. The switching circuit switches the configuration of the positive capacitor array and the negative capacitor array by receiving a digital code DC during each comparison phase, thereby outputting different positive output voltages Va and negative output voltages Vb.

[0023] Therefore, the time length between two consecutive times when the sampling indication signal SIS is in the sampling state is the conversion time set by the system.

[0024] The comparator 120 compares the positive output voltage Va and the negative output voltage Vb during each comparison phase to generate a comparison result CR. The number of comparison phases is a predetermined number. Specifically, the analog-to-digital conversion circuit 100 performs a predetermined number of comparison phases to achieve a single analog-to-digital conversion.

[0025] Please refer to Figure 2 . Figure 2 FIG. 2 is a circuit diagram of a comparator 120 according to an embodiment of the present invention. In one embodiment, the comparator 120 includes a plurality of transistors M1 - M7 and two inverters INV1 and INV2 .

[0026] The gates of P-type transistors M1 and M2 receive a positive output voltage Va and a negative output voltage Vb, respectively. The drain and gate of N-type transistor M3 are electrically coupled to the drains of P-type transistors M1 and M2, respectively, and the source is grounded. The drain and gate of N-type transistor M4 are electrically coupled to the drains of P-type transistors M2 and M1, respectively, and the source is grounded. The drain and gate of N-type transistor M5 are electrically coupled to the drain of P-type transistor M1 and receive an enable signal CLKC, respectively, and the source is grounded. The drain and gate of N-type transistor M6 are electrically coupled to the drain of P-type transistor M2 and receive an enable signal CLKC, respectively, and the source is grounded.

[0027] P-type transistors M6 and M7 are connected in series between a voltage source VDD and the sources of P-type transistors M1 and M2. The gate of P-type transistor M6 receives a bias voltage Via, and the gate of P-type transistor M7 receives an enable signal CLKC. Two inverters INV1 and INV2 are electrically coupled to the drains of P-type transistors M1 and M2, respectively, to generate output results OR1 and OR2 based on the inputs of a positive output voltage Va and a negative output voltage Vb.

[0028] In one embodiment, the analog-to-digital conversion circuit 100 further includes an enable logic circuit 170, which is a NOR gate. The enable logic circuit 170 generates the enable signal CLKC based on the different states of the sampling indication signal SIS, the phase indication signal TIS, and the conversion indication signal CIS. The generation of the phase indication signal TIS and the conversion indication signal CIS will be described in more detail in the following paragraphs.

[0029] As described above, the sampling indication signal SIS indicates whether sampling is complete, depending on whether it is in the sampling state or the sampling completed state. The sampling state is high, while the sampling completed state is low. The phase indication signal TIS indicates whether the comparison phase is complete, depending on whether it is in the comparison phase incomplete state or the comparison phase completed state. The comparison phase incomplete state is low, while the comparison phase completed state is high. The conversion indication signal CIS indicates whether analog-to-digital conversion is complete, depending on whether it is in the conversion incomplete state or the conversion completed state. The conversion incomplete state is low, while the conversion completed state is high.

[0030] Therefore, when the analog-to-digital conversion circuit 100 begins analog-to-digital conversion, the sampling indication signal SIS is in the sampling state, the stage indication signal TIS is in the comparison stage incomplete state, and the conversion indication signal CIS is in the conversion incomplete state. The enable logic circuit 170 accordingly generates a low enable signal CLKC to disable the comparator 120. At this point, both the output result OR1 and the output result OR2 are low, and the comparison result CR has not yet been generated.

[0031] Then, the sampling indication signal SIS is in the sampling completion state to complete sampling, the phase indication signal TIS is still in the comparison phase incomplete state, and the conversion indication signal CIS is still in the conversion incomplete state. The enable logic circuit 170 generates a high enable signal CLKC to enable the comparator 120 to perform comparison.

[0032] Then, when one of the output results OR1 and OR2 is high and the other is low, Figure 1 The comparison result CR is shown, and the phase indication signal TIS is in the comparison phase complete state due to the generation of the comparison result CR. At this time, the sampling indication signal SIS is in the sampling complete state (low state), the phase indication signal TIS is in the comparison phase complete state (high state), and the conversion indication signal CIS is in the conversion incomplete state (low state). The enable logic circuit 170 will generate a low enable signal CLKC to disable the comparator 120.

[0033] The disabled comparator 120 will make the output results OR1 and OR2 low again, so that the comparison result CR returns to the state where it has not yet been generated. The enable logic circuit 170 will then generate a high enable signal CLKC to enable the comparator 120 to perform comparison again.

[0034] Therefore, the comparator 120 repeatedly performs the above-mentioned operation in each comparison phase after sampling is completed until all comparison phases are completed and the analog-to-digital conversion is completed. The conversion indication signal CIS is in the conversion completion state to disable the comparator 120, and the above-mentioned operation is used to sample again for the next analog-to-digital conversion.

[0035] The control circuit 130 switches the configuration of the digital-to-analog conversion circuit 110 with a set of digital codes DC according to the comparison result CR in each comparison phase, and outputs the corresponding digital code DC as the digital output signal DOUT when the conversion completion condition is met.

[0036] Comparison and determination circuit 140 receives output results OR1 and OR2. Before a comparison result CR is generated in each comparison phase (output results OR1 and OR2 are both low), phase indication signal TIS is set to a comparison phase incomplete state. After a comparison result CR is generated (one of output results OR1 and OR2 is high and the other is low), phase indication signal TIS is set to a comparison phase complete state. In one embodiment, comparison and determination circuit 140 can be implemented by an exclusive OR (XOR) gate.

[0037] The comparison phase counter circuit 150 counts the number of completions corresponding to one of the comparison phases when the phase indication signal TIS is in the comparison phase completed state. When the number of completions reaches a predetermined number, the conversion indication signal CIS is set to the conversion incomplete state. After the number of completions reaches the predetermined number, the conversion indication signal CIS is set to the conversion completed state. In one embodiment, the conversion incomplete state is low, and the conversion completed state is high.

[0038] Please refer to Figure 3 . Figure 3 FIG1 shows a circuit diagram of a comparison phase counting circuit 150 in an embodiment of the present invention. The comparison phase counting circuit 150 includes a plurality of counting D-type flip-flops DFC1 to DFC2 connected in series. M Counting D-type flip-flops DFC1~DFC M They respectively include an input terminal D, an output terminal Q and a clock input terminal CK.

[0039] The input terminal D of the first counting D-type flip-flop DFC1 receives the driving signal DVS, and the driving signal DVS is in a high state. The output terminal Q of each counting D-type flip-flop is electrically coupled to the input terminal D of the next counting D-type flip-flop. The clock input terminal CK receives the stage indication signal TIS.

[0040] In one embodiment, the counting D-type flip-flops DFC1 to DFC M The output terminal of is reset to a low state each time the analog-to-digital conversion circuit 100 starts analog-to-digital conversion (for example, when sampling). M The comparison phase completion state (high state) of one of the comparison phases is sequentially driven according to the phase indication signal TIS, so as to output the driving signal DVS from the output terminal Q.

[0041] More specifically, the comparison judgment circuit 140 switches the stage indication signal TIS from the comparison incomplete state to the comparison stage complete state (i.e., from a low state to a high state) according to the comparison result CR at each comparison stage. Each time the stage indication signal TIS is in the comparison stage complete state, it sequentially triggers a counting D-type flip-flop, causing the driving signal DVS to flow along the series-connected counting D-type flip-flops DFC1 to DFC M Pass one by one. The last count D-type flip-flop DFC M The output terminal Q outputs the conversion indication signal CIS in the conversion incomplete state (low state) before being driven, and outputs the driving signal DVS as the conversion indication signal CIS in the conversion complete state (high state) only after being driven.

[0042] In one embodiment, the number of counted D-type flip-flops is equivalent to the preset number in the comparison stage, and each driving of one counted D-type flip-flop is equivalent to accumulating the number of completions once.

[0043] For example, when the analog-to-digital conversion circuit 100 requires four comparison stages to complete the analog-to-digital conversion, four counting D-type flip-flops can be triggered in sequence, and the output end of the fourth counting D-type flip-flop is driven to output the conversion indication signal CIS in the conversion completion state, thereby achieving the purpose of accumulating four completion times.

[0044] The time accumulation circuit 160 starts accumulating the remaining time RT when the conversion indication signal CIS is in the conversion completion state, and completes the accumulation when the sampling indication signal SIS is in the sampling state next time.

[0045] Please refer to Figure 4 . Figure 4 FIG. 4 is a circuit diagram of a time accumulation circuit 160 according to an embodiment of the present invention. The time accumulation circuit 160 includes a delay circuit 400 , a trigger circuit 410 , and a determination circuit 420 .

[0046] The delay circuit 410 includes a plurality of delay units DU1 to DU2 connected in series. N , configured to transmit the conversion indication signal CIS. In one embodiment, the delay units DU1-DU N Each of the delay units DU1 to DU N The output conversion indication signals CIS are all in phase. In this embodiment, two inverters IV1 and IV2 are connected in series as an example for illustration. However, the present invention is not limited thereto.

[0047] The trigger circuit 420 includes a plurality of trigger D-type flip-flops DFT1 to DFT2 connected in series. N+1 . Trigger D-type flip-flop DFT1~DFT N+1They respectively include an input terminal D, an output terminal Q and a clock input terminal CK.

[0048] The first trigger D-type flip-flop DFT1 directly receives the conversion indication signal CIS at its input terminal D, and the other trigger D-type flip-flops DFT2 to DFT N The input terminal D is electrically coupled to one of the delay units DU1-DU N To receive delay units DU1~DU N In this embodiment, the D-type flip-flops DFT2 to DFT3 are triggered. N+1 The number of delay units DU1~DU N The clock input terminal CLK receives the sampling indication signal SIS.

[0049] The judgment circuit 420 is electrically coupled to each of the triggered D-type flip-flops DFT1 to DFT N The output terminal Q.

[0050] In one embodiment, the delay units DU1-DU N The output terminal of is reset to a low state each time the analog-to-digital conversion circuit 100 starts analog-to-digital conversion (e.g., when sampling), and then transmits the conversion indication signal CIS in sequence during the conversion process. N The output terminal Q of the MOSFET outputs the conversion indication signal CIS when the sampling indication signal SIS is in the sampling state (high state) next time.

[0051] The determination circuit 420 determines the total delay time length of the corresponding delay units transmitting the conversion indication signal CIS in the conversion completion state as the remaining time RT according to the number of trigger D-type flip-flops that output the conversion indication signal CIS in the conversion completion state (high state).

[0052] For example, after the comparison judgment circuit 140 judges that the conversion is completed and outputs the conversion indication signal CIS from the conversion incomplete state to the conversion completed state, the delay units DU1 to DU N When the sampling indication signal SIS is in the sampling state next time (i.e., the next analog-to-digital conversion is performed), the conversion indication signal CIS in the conversion completion state is transmitted to the fourth delay unit DU4, and the other delay units DU5 to DU N The conversion indication signal CIS in the conversion incomplete state is still output.

[0053] At this time, the output terminals Q of the D-type flip-flops DFT1 to DFT5 are triggered to output the conversion indication signal CIS in the conversion completion state under the driving of the sampling indication signal SIS, and the D-type flip-flops DFT6 to DFT5 are triggered.N+1 The output terminal Q of the CMOS outputs the conversion indication signal CIS in the conversion incomplete state under the driving of the sampling indication signal SIS.

[0054] Therefore, the determination circuit 420 determines the number of delay units DU1-DU4 (four) that transmit the conversion indication signal CIS based on the number of D-type flip-flops DFT1-DFT5 (five) that trigger the conversion completion status. The determination circuit 420 then multiplies the unit delay time length of the signal transmitted by each delay unit by the number of delay units to obtain the total delay time length, which is used as the residual time RT. In one numerical example, the unit delay time length of each delay unit is 0.1-0.2 nanoseconds. Taking 0.1 nanosecond as an example, the total delay time length of the four delay units is 0.4 nanoseconds.

[0055] Since the time length between two consecutive sampling states of the sampling indication signal SIS is the conversion time set by the system, and the corresponding operation time when the conversion indication signal CIS is in the conversion completion state is not equal to the conversion time, the analog-to-digital conversion circuit 100 measures the remaining time RT, which is the difference between the conversion time and the actual operation time, through the above mechanism.

[0056] In one embodiment, the analog-to-digital conversion circuit 100 can adjust at least one operating parameter based on the remaining time RT. The operating parameter includes, for example, but not limited to, loop speed, operating voltage, operating current of the digital-to-analog conversion circuit 110, or a combination thereof. The operating parameter can be adjusted by, for example, but not limited to, the control circuit 130.

[0057] Therefore, the analog-to-digital conversion circuit of the present invention with a residual time measurement mechanism can measure the residual time difference between the system-set conversion time and the actual operation time, thereby achieving the purpose of adjusting the system operation parameters according to the residual time to improve the performance of the analog-to-digital conversion circuit.

[0058] It should be noted that the above circuit structure and the number of components included in each circuit are merely examples. In different embodiments, the circuit structure and the number of components can be adjusted according to actual needs without affecting performance. Furthermore, the above logic circuits and the related state levels are merely examples. Other logic circuits can also be used, or operations based on opposite states can be used without affecting performance. The present invention is not limited to the above embodiments.

[0059] Please refer to Figure 5 . Figure 5 FIG. 1 is a flow chart illustrating an analog-to-digital conversion method 500 with a residual time measurement mechanism according to an embodiment of the present invention.

[0060] In addition to the aforementioned device, the present invention further discloses an analog-to-digital conversion method 500 with a residual time measurement mechanism, which is applied to, for example, but not limited to Figure 1 In the analog-to-digital conversion circuit 100. One embodiment of the analog-to-digital conversion method 500 is as follows: Figure 5 As shown, the following steps are included:

[0061] In step S510 , it is determined whether the sampling indication signal SIS is in a sampling state.

[0062] In step S515 , when the sampling indication signal SIS is in the sampling state, the accumulation of the remaining time RT of the previous analog-to-digital conversion is completed, and the digital-to-analog conversion circuit 110 performs a new sampling of the positive input voltage Vip and the negative input voltage Vin.

[0063] In step S520 , when the sampling indication signal SIS is in the sampling completion state, the digital-to-analog conversion circuit 110 outputs the positive-end output voltage Va and the negative-end output voltage Vb.

[0064] In step S525 , the comparator 120 is enabled to compare the positive-end output voltage Va and the negative-end output voltage Vb.

[0065] In step S530 , the comparison judgment circuit 140 determines whether a comparison result CR is generated.

[0066] In step S535, before the comparison result CR is generated, the comparison judgment circuit 140 sets the stage indication signal TIS to the comparison stage incomplete state, and the process returns to step S525 to continue the comparison.

[0067] In step S540 , after the comparison result CR is generated, the comparison judgment circuit 140 sets the stage indication signal TIS to the comparison stage completion state, and the comparison stage counting circuit 150 accumulates the completion times according to the stage indication signal TIS in the comparison stage completion state.

[0068] In step S545 , the comparison phase counting circuit 150 is enabled to determine whether the number of completion times reaches a preset number.

[0069] In step S550 , when the number of completions does not reach the preset number, the control circuit 130 further determines whether the difference between the positive-end output voltage Va and the negative-end output voltage Vb is less than a preset level.

[0070] In step S555, if the difference between the positive-end output voltage and the negative-end output voltage is not less than a predetermined level, the comparison phase counter circuit 150 sets the conversion indication signal CIS to the conversion incomplete state. The control circuit 130 switches the configuration of the digital-to-analog conversion circuit 110 using a set of digital codes DC based on the comparison result CR. The process then returns to step S525 for the next comparison phase.

[0071] In step S560, when the difference between the positive output voltage Va and the negative output voltage Vb is less than a predetermined level, the comparison phase counter circuit 150 sets the conversion indication signal CIS to a conversion incomplete state. In one embodiment, the control circuit 130 can still switch the configuration of the digital-to-analog conversion circuit 110 using a digital code DC based on the comparison result CR.

[0072] In step S565, when the number of completions reaches a predetermined value, the comparison phase counter circuit 150 sets the conversion indication signal CIS to the conversion completion state. The time accumulation circuit 160 begins accumulating the remaining time RT. The control circuit 130 determines whether the conversion completion condition has been met and outputs the corresponding digital code DC as the digital output signal DOUT. The process returns to step S510, and the accumulation is completed the next time the sampling indication signal SIS is in the sampling state.

[0073] It should be noted that the above-mentioned implementation is only an example. In other embodiments, those skilled in the art may make changes without departing from the spirit of the present invention.

[0074] In summary, the analog-to-digital conversion circuit and method with a residual time measurement mechanism in the present invention can measure the residual time difference between the system-set conversion time and the actual operation time, thereby achieving the purpose of adjusting the system operating parameters according to the residual time to improve the performance of the analog-to-digital conversion circuit.

[0075] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. A person skilled in the art may modify the technical features of the present application based on the explicit or implicit contents of the present application. All such modifications may fall within the scope of the patent protection sought by the present application. In other words, the scope of patent protection of the present application shall be subject to the scope of the patent application defined in this specification.

[0076]

Explanation of symbols

[0077] 100: Analog to digital conversion circuit

[0078] 110: Digital to analog conversion circuit

[0079] 120: Comparator

[0080] 130: Control circuit

[0081] 140: Comparison and judgment circuit

[0082] 150: Comparison stage counting circuit

[0083] 160: Time accumulation circuit

[0084] 170: Enable logic circuit

[0085] 400: Delay circuit

[0086] 410: Trigger Circuit

[0087] 420: Judgment circuit

[0088] 500: Analog to Digital Conversion Methods

[0089] S510~S565: Steps

[0090] CK: clock input

[0091] CLKC: enable signal

[0092] CIS: conversion indication signal

[0093] CR: Comparison results

[0094] D: Input terminal

[0095] DC: Digital Code

[0096] DFC1~DFC M :Counting D-type flip-flop

[0097] DFT1~DFT N+1 :Trigger D-type flip-flop

[0098] DOUT: digital output signal

[0099] DU1~DU N : Delay unit

[0100] DVS: driving signal

[0101] INV1, INV2: Inverters

[0102] IV1, IV2: Inverters

[0103] M1~M7:Transistors

[0104] OR1, OR2: output results

[0105] Q: Output

[0106] RT: Remaining time

[0107] Sip, Sin: switch

[0108] SIS: Sampling Indication Signal

[0109] TIS: Phase Indication Signal

[0110] Va: positive output voltage

[0111] Vb: negative output voltage

[0112] VDD: voltage source

[0113] Via: Bias

[0114] Vip: positive input voltage

[0115] Vin: Negative input voltage.

Claims

1. An analog-to-digital conversion circuit with a remaining time measurement mechanism, comprising: a digital-to-analog conversion circuit configured to sample a positive input voltage and a negative input voltage when a sampling indication signal is in a sampling state, and output a positive output voltage and a negative output voltage when the sampling indication signal is in a sampling completion state; a comparator configured to compare the positive output voltage and the negative output voltage in a plurality of comparison stages to generate a comparison result, wherein the number of the plurality of comparison stages is a predetermined number; a control circuit configured to switch a configuration of the digital-to-analog conversion circuit using a set of digital codes according to the comparison results in each of the plurality of comparison stages, and output the corresponding set of digital codes as a digital output signal when a conversion completion condition is satisfied; a comparison judgment circuit configured to set a stage indication signal to a comparison stage incomplete state before the comparison result in each of the plurality of comparison stages is generated, and to set the stage indication signal to a comparison stage complete state after the comparison result is generated; a comparison stage counting circuit configured to accumulate a completion count when the stage indication signal is in a comparison stage completion state in each of the plurality of comparison stages, set a conversion indication signal in a conversion incomplete state when the completion count reaches a preset number, and set the conversion indication signal in a conversion complete state after the completion count reaches the preset number; as well as A time accumulation circuit is configured to start accumulating a remaining time when the conversion indication signal is in the conversion completion state, and complete the accumulation when the sampling indication signal is in the sampling state next time.

2. The analog-to-digital conversion circuit according to claim 1 , further comprising: An enabling logic circuit is configured to enable the comparator when the sampling indication signal is in the sampling completed state, the phase indication signal is in the comparison phase incomplete state, and the conversion indication signal is in the conversion incomplete state.

3. The analog-to-digital conversion circuit according to claim 1 , wherein the comparison phase counting circuit comprises: A plurality of counting D-type flip-flops connected in series include: an input terminal, wherein the input terminal of the first of the plurality of counting D-type flip-flops is configured to receive a driving signal; an output terminal electrically coupled to the input terminal of the next of the plurality of counting D-type flip-flops; and a clock input terminal configured to receive the phase indication signal; wherein each of the plurality of counting D-type flip-flops is driven in sequence according to the stage indication signal corresponding to the comparison stage completion state of one of the plurality of comparison stages, so as to output the driving signal from the output end, and the output end of the last of the plurality of counting D-type flip-flops outputs the driving signal as the conversion indication signal in the conversion completion state only after being driven; and The number of the plurality of counting D-type flip-flops is equal to the preset number.

4. The analog-to-digital conversion circuit according to claim 1 , wherein the time accumulation circuit comprises: a delay circuit comprising a plurality of delay units connected in series and configured to transmit the conversion indication signal; A trigger circuit includes a plurality of trigger D-type flip-flops connected in series, each including: an input terminal, wherein a first one of the plurality of trigger D-type flip-flops is configured to directly receive the conversion indication signal, and the other plurality of trigger D-type flip-flops are respectively electrically coupled to one of the plurality of delay units to receive the conversion indication signal transmitted by one of the plurality of delay units; an output terminal; as well as a clock input terminal configured to receive the sampling indication signal; and a judgment circuit electrically coupled to the output end of each of the plurality of triggered D-type flip-flops; The output end of each of the plurality of triggered D-type flip-flops outputs the conversion indication signal when the sampling indication signal is in the sampling state next time, so that the determination circuit determines, based on the number of the plurality of triggered D-type flip-flops that output the conversion indication signal in the conversion completion state, a total delay time length of the plurality of delay units corresponding to transmitting the conversion indication signal in the conversion completion state as the remaining time. 5 . The analog-to-digital conversion circuit according to claim 4 , wherein each of the plurality of delay units comprises an even number of inverters connected in series.

6. The analog-to-digital conversion circuit according to claim 1 , wherein at least one operating parameter of the analog-to-digital conversion circuit is adjusted according to the remaining time, the operating parameter comprising a loop speed, an operating voltage, an operating current of the digital-to-analog conversion circuit, or a combination thereof. 7 . The analog-to-digital conversion circuit according to claim 1 , wherein the conversion completion condition is satisfied when a difference between the positive-end output voltage and the negative-end output voltage is less than a preset level and the completion count reaches the preset number.

8. An analog-to-digital conversion method with a residual time measurement mechanism, comprising: A digital-to-analog conversion circuit samples a positive input voltage and a negative input voltage when a sampling indication signal is in a sampling state, and outputs a positive output voltage and a negative output voltage when the sampling indication signal is in a sampling completion state; enabling a comparator to compare the positive output voltage and the negative output voltage in each of a plurality of comparison stages to generate a comparison result, wherein the number of the plurality of comparison stages is a preset number; causing a control circuit to switch a configuration of the digital-to-analog conversion circuit using a set of digital codes according to the comparison results in each of the plurality of comparison stages, and outputting the corresponding set of digital codes as a digital output signal when a conversion completion condition is satisfied; causing a comparison judgment circuit to set a stage indication signal to a comparison stage incomplete state before the comparison result in each of the plurality of comparison stages is generated, and to set the stage indication signal to a comparison stage complete state after the comparison result is generated; causing a comparison stage counting circuit to accumulate a completion count when the stage indication signal is in a comparison stage completion state in each of the plurality of comparison stages, causing a conversion indication signal to be in a conversion incomplete state when the completion count reaches a preset number, and causing the conversion indication signal to be in a conversion complete state after the completion count reaches the preset number; as well as A time accumulation circuit starts accumulating a remaining time when the conversion indication signal is in the conversion completion state, and completes the accumulation when the sampling indication signal is in the sampling state next time.

9. The analog-to-digital conversion method according to claim 8, further comprising: An enabling logic circuit enables the comparator when the sampling indication signal is in the sampling completed state, the phase indication signal is in the comparison phase incomplete state, and the conversion indication signal is in the conversion incomplete state.

10. The analog-to-digital conversion method according to claim 8 , wherein the comparison phase counting circuit comprises a plurality of counting D-type flip-flops connected in series, each of the counting D-type flip-flops comprising an input terminal, an output terminal electrically coupled to the input terminal of a next one of the plurality of counting D-type flip-flops, and a clock input terminal configured to receive the phase indication signal, wherein the number of the plurality of counting D-type flip-flops is equal to the predetermined number, and the analog-to-digital conversion method comprises: enabling the input end of the first of the plurality of counting D-type flip-flops to receive a driving signal; driving each of the plurality of counting D-type flip-flops in sequence according to the stage indication signal corresponding to the comparison stage completion state of one of the plurality of comparison stages, so as to output the driving signal from the output terminal; and The output terminal of the last one of the plurality of counting D-type flip-flops is enabled to output the driving signal as the conversion indication signal in the conversion completion state only after being driven.

Images