A gate regulated lateral neuromorphic device doped with ion salt and a preparation method thereof

Abstract

The application provides a gate-regulated lateral neuromorphic device doped with an ionic salt and a preparation method thereof.The whole device comprises a substrate, an electrolyte functional layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate and source-drain electrodes, the electrolyte functional layer is arranged on the substrate, the charge trapping layer is arranged on the side of the electrolyte functional layer away from the substrate, and the organic semiconductor layer is arranged on the side of the charge trapping layer away from the electrolyte functional layer; the organic semiconductor layer is separated, and the horizontal gate and the source-drain electrodes are arranged above the organic semiconductor layer respectively, the semiconductor below the source-drain electrodes serves as a channel layer, and the semiconductor below the horizontal gate serves as a floating gate layer.The neuromorphic device has good electrical performance, has higher stability in an air environment compared with a hydrogen ion electrolyte device, and has a significant light response and a clear hysteresis phenomenon under the action of a negative gate voltage.The device has simple process and low cost, and can be widely applied in neuromorphic circuits.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of neuromorphic devices in the semiconductor industry, in particular to a gate-controlled lateral neuromorphic device doped with ion salt and a preparation method thereof. BACKGROUND

[0002] Computers using traditional von Neumann architecture have the characteristic of separation of memory and calculation, and when processing information, data needs to be transmitted back and forth between the processor and the memory unit, which can seriously limit the computing speed of the system, causing delay and high energy consumption. With the rapid development of information technology, the amount of information needed to be processed daily has increased dramatically, and most of the information has complex spatiotemporal characteristics. How to quickly and real-time process such information has become a popular research direction. The human brain is a parallel computing biological computer that can efficiently process various complex tasks and has the characteristics of low power consumption and small size. Therefore, based on new structures, new principles and new materials, electronic devices with brain-like neuromorphic computing characteristics are developed, and artificial neural networks are constructed to simulate the structure and function of biological neural networks. The development of neuromorphic chips that can real-time and efficiently process information and integrate sensing, storage and calculation is an important development direction of future artificial intelligence chips.

[0003] The key to developing neuromorphic chips is electronic devices that can simulate the neural behavior of the human brain, and artificial synapses are the basic building blocks of neuromorphic systems. Researchers have proposed many devices to simulate the behavior and function of synapses, including two-terminal devices such as memristors and phase change memories, and three-terminal devices such as field effect transistors and ferroelectric transistors. Artificial synapse devices based on transistors have the advantages of simple and diverse structure, controllable test parameters, clear mechanism, and can easily achieve coordinated control of a device, signal transmission and autonomous learning, which is suitable for simulating synaptic behavior and function. Among them, the gate-controlled transistor based on electrolyte has the advantages of low energy consumption, good stability, high linearity and symmetry. Under the action of the gate voltage, the ion migration in the electrolyte is similar to the release process of neurotransmitters in the biological synapses of the nervous system. The gate of the electrolyte transistor is equivalent to the presynaptic membrane, the semiconductor channel is equivalent to the postsynaptic membrane, and the channel conductance is equivalent to the synaptic weight, which can simulate the plasticity behavior of biological synapses and is one of the ideal elements for synaptic simulation.

[0004] Currently, the mobile ions in the electrolyte layer of traditional electrolyte gate-controlled neuromorphic devices are mostly hydrogen ions, which are easily affected by water vapor in the air, resulting in unstable device performance. In addition, the device structure is generally bottom gate top contact or top gate bottom contact, which is not conducive to device integration.

[0005] Therefore, it is necessary to design a stable gate-controlled lateral neuromorphic device. SUMMARY

[0006] The application aims to provide an electrolyte gate-controlled transverse neuromorphic device capable of maintaining stable performance in air and excellent electrical properties and a preparation method thereof.

[0007] To achieve the above-mentioned application purposes, the technical scheme of the application is as follows:

[0008] The application discloses a gate-controlled transverse neuromorphic device doped with ion salt, which comprises a substrate, an electrolyte functional layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate and source-drain electrodes. The electrolyte functional layer is arranged on the substrate, the charge trapping layer is arranged on the side of the electrolyte functional layer away from the substrate, and the organic semiconductor layer is arranged on the side of the charge trapping layer away from the electrolyte functional layer. The organic semiconductor layer is separated and the horizontal gate and the source-drain electrodes are arranged above the organic semiconductor layer, respectively. The semiconductor below the source-drain electrodes serves as a channel layer, and the semiconductor below the horizontal gate serves as a floating gate layer. The moving ions of the electrolyte layer of the device are sodium ions, potassium ions or lithium ions, which replace the traditional hydrogen ions, so that the device has better stability in an air atmosphere. The device adopts a horizontal gate structure, which is convenient for large-scale integration.

[0009] Further, the substrate is Si / SiO2, and the thickness of SiO2 is 50 nm.

[0010] Further, the material of the electrolyte functional layer is polyvinylidene fluoride doped with ion salt, and the material of the charge trapping layer is polystyrene.

[0011] Further, the material of the organic semiconductor layer is pentacene, and the thickness of the thin film is 30 nm.

[0012] Further, the material of the horizontal gate and the source-drain electrodes is one of copper or gold, and the thickness of the source-drain electrodes is 50 nm.

[0013] Further, the electrolyte functional layer and the charge trapping layer are prepared by adopting a solution method to spin and anneal to form a film. The preparation method of the organic semiconductor layer, the horizontal gate and the source-drain electrodes is selected to adopt a vacuum evaporation method.

[0014] Further, the ion salt is selected from one or more of sodium chloride, potassium chloride and lithium chloride.

[0015] The application further provides a preparation method of the gate-controlled transverse neuromorphic device doped with ion salt.

[0016] Step 1: Prepare a Si / SiO2 substrate, ultrasonic clean and dry for standby use;

[0017] Step 2: Prepare NaCl, KCl and LiCl aqueous solution; prepare a polyvinylidene fluoride (PVDF) solution, and the solvent is N-methyl pyrrolidone (NMP);

[0018] Step 3: take the polyvinylidene fluoride solution, add the aqueous solution prepared in step 2, and ultrasonically mix;

[0019] Step 4: prepare a polystyrene (PS) solution, and the solvent is toluene;

[0020] Step 5: first, UV treat the substrate; then, spin coat the mixed solution prepared in step 3 on the substrate, and perform thermal annealing treatment; then, continue to spin coat the PS solution prepared in step 4, and perform thermal annealing treatment;

[0021] Step 6: place the completed sample above into a vacuum evaporation system, evaporate pentacene, horizontal gate and source-drain electrode in sequence; after evaporation is completed, place the device into a dry nitrogen cabinet for storage, and thus a gate-controlled lateral neural morphological device doped with ion salt is prepared.

[0022] Further, in step 2, the NaCl, KCl and LiCl aqueous solution is prepared, and the solution concentration is 50 mg / ml; when the polyvinylidene fluoride solution is prepared, the polyvinylidene fluoride is completely dissolved by magnetic stirring for 10 h, and the mass ratio of polyvinylidene fluoride is 5%; in step 3, 3 ml of the polyvinylidene fluoride solution is taken, 0.15 ml of the aqueous solution in step 2 is added, and ultrasonic mixing is performed for 1 h; in step 4, the polystyrene solution is prepared, the solvent is toluene, and the solution concentration is 6 mg / ml.

[0023] Further, in step 6, the evaporation rate of pentacene in the vacuum evaporation is The vacuum degree is controlled below 5*10 - 4 Pa, the film thickness is monitored and controlled to be 30 nm by using a crystal oscillator film thickness instrument; in step 6, the evaporation rate of the source-drain electrode in the vacuum evaporation is The film thickness is monitored and controlled to be 30 nm by using a crystal oscillator film thickness instrument.

[0024] The beneficial effects of the present application are as follows:

[0025] 1. The device electrolyte layer moves the conductive ions, which are sodium ions, potassium ions or lithium ions, etc., and is different from most devices based on hydrogen ion electrolyte, and has high stability in an air atmosphere;

[0026] 2. The device adopts a lateral horizontal gate structure, and is convenient for integration;

[0027] 3. The device has a simple structure, is mostly prepared by a solution method, has low cost, and is easy to promote and research on a large scale;

[0028] 4. The present application is a neural morphological device, which can be used for integrated neural morphological circuit, simulates synaptic behavior, and replaces the role of part of peripheral circuit simulation. BRIEF DESCRIPTION OF DRAWINGS

[0029] Figure 1A structural schematic diagram of the neuromorphic device according to the present application.

[0030] Figure 2 A transfer characteristic curve diagram of the sodium chloride doped device under dark condition according to the present application.

[0031] Figure 3 A transfer characteristic curve diagram of the sodium chloride doped device under white light illumination condition according to the present application.

[0032] Figure 4 A unidirectional scanning transfer characteristic curve diagram of the sodium chloride doped device according to the present application.

[0033] Figure 5 A transfer characteristic curve diagram of the potassium chloride doped device according to the present application. DETAILED DESCRIPTION

[0034] In order to make the technical solutions and beneficial effects of the present application more obvious, the present application will be described in detail below in combination with the drawings and specific embodiments.

[0035] As shown in Figure 1 , a gate-regulated lateral neuromorphic device doped with ionic salt, the device structure comprising a substrate, an electrolyte functional layer formed on the substrate, a charge trapping layer covering the electrolyte functional layer, an organic semiconductor layer formed on the charge trapping layer, and a horizontal gate above the organic semiconductor layer and source-drain electrodes on both sides of the channel on the surface of the organic semiconductor layer.

[0036] In specific embodiments, heavily doped silicon and 50 nm silicon dioxide are used as the substrate; the electrolyte functional layer uses sodium ion doped PVDF, which is spin-coated into a film; a layer of PS is spin-coated on the electrolyte functional layer as a charge trapping layer; a 30 nm thick pentacene layer is evaporated on the charge trapping layer as an organic semiconductor layer; metal copper is evaporated on both sides of the channel and above the organic semiconductor layer as a horizontal gate and source-drain electrodes, respectively.

[0037] The electrolyte functional layer based on the mixed solution is mixed from the NMP solution of PVDF and the aqueous solution of sodium chloride. In the actual preparation process, the room temperature in the laboratory is kept at about 20℃, and the relative humidity is kept below 50%.

[0038] The specific preparation steps of the device according to the specific embodiments are as follows:

[0039] Step (1): Prepare a silicon / silicon dioxide substrate, ultrasonic clean, put it into a forced air drying machine at 80℃ for 1h, and put it into a nitrogen cabinet for storage for standby use.

[0040] Step (2): Prepare a sodium chloride solution, take 0.5 g of sodium chloride and add to 10 ml of water, stir until completely dissolved; prepare a PVDF solution, take 1 g of PVDF and add to 19 ml of NMP, put into a magnetic stirrer and stir for 10 h until completely dissolved; take 90 mg of PS and add to 15 ml of toluene, put into a magnetic stirrer and stir for 10 h until completely dissolved.

[0041] Step (3): Take 3 ml of the PVDF solution in step (2) and add 0.15 ml of the sodium chloride aqueous solution, ultrasonically mix for 1 h.

[0042] Step (4): Perform ultraviolet ozone treatment on the cleaned substrate, then spin coat the mixed solution prepared in step (3) onto the substrate at a spin coating speed of 1000 r / min for 1 min, and perform thermal annealing at 150°C for 30 min on a hot stage.

[0043] Step (5): Spin coat the prepared PS solution onto the above sample at a spin coating speed of 1000 r / min for 1 min, and perform thermal annealing at 150°C for 30 min on a hot stage. If storage is required, it should be placed in a nitrogen cabinet with a relative humidity of less than 10%.

[0044] Step (6): Put the above sample into a vacuum evaporation system, evaporate an organic semiconductor layer and pentacene on the surface of the prepared thin film, rotate the substrate during evaporation, the vacuum degree is below 5 x 10 -4 Pa, the evaporation rate is below; control the film thickness to be 30 nm; continue to evaporate copper as a horizontal gate and source-drain electrode on the surface, do not rotate the substrate during evaporation, the vacuum degree is below 5 x 10 -4 Pa, the evaporation rate is Control the film thickness to be 50 nm. The channel width of the mask plate is 2000 μm and the length is 200 μm.

[0045] After the device is prepared, its electrical properties are characterized using a Keithley 2636B, and the test data is processed to draw Figure 2 , Figure 3 , Figure 4 and Figure 5 .

[0046] Figure 2 is the transfer characteristic curve of the device under dark conditions, the source-drain voltage V DS = -5 V, the horizontal gate voltage scanning range is 10 V to -25 V, and the hysteresis window is small. Figure 3 is the transfer characteristic curve of the device under white light illumination conditions, the source-drain voltage V DS= -5V, the horizontal gate voltage is bidirectional scanning in the range of 10V~ -25V, when the gate voltage is scanned from -25V to 10V, there is an obvious hysteresis window, and the light condition has a great influence on the device.

[0047] Figure 4 Fig. 6 is a transfer characteristic curve of the device doped with sodium chloride for unidirectional scanning, the gate voltage is scanned from 10V to -25V, and the source-drain voltage is set to -5V, and the device has a high on-off current ratio. Figure 5 Fig. 7 is a transfer characteristic curve of the device doped with potassium chloride, the source-drain voltage V DS = -5V, the horizontal gate voltage is bidirectional scanning in the range of 10V~ -25V, when the gate voltage is scanned from -25V to 10V, there is an obvious hysteresis window, and the light condition has a great influence on the device. DS = -5V, the horizontal gate voltage is bidirectional scanning in the range of 10V~ -25V, when the gate voltage is scanned from -25V to 10V, there is an obvious hysteresis window, and the light condition has a great influence on the device.

[0048] The above examples are only used to illustrate the technical solutions of the present application and not to limit the present application, and those skilled in the art should understand that any modification or equivalent replacement of the technical solutions should not deviate from the spirit and scope of the present application.

Claims

1. A gated transverse neuromorphic device doped with an ionic salt, characterized by: The device comprises a substrate, an electrolyte functional layer, a charge trapping layer, an organic semiconductor layer, a horizontal gate and a source-drain electrode, the electrolyte functional layer is arranged on the substrate, the charge trapping layer is arranged on the side of the electrolyte functional layer away from the substrate, and the organic semiconductor layer is arranged on the side of the charge trapping layer away from the electrolyte functional layer; The organic semiconductor layer is separated and provided with the horizontal gate and the source-drain electrode respectively, the semiconductor under the source-drain electrode serves as a channel layer, and the semiconductor under the horizontal gate serves as a floating gate layer; The preparation method of the device comprises the following steps: Step 1: preparing a Si / SiO2 substrate, ultrasonic cleaning and drying for standby; Step 2: preparing NaCl, KCl and LiCl aqueous solution; preparing polyvinylidene fluoride solution, and the solvent is N-methyl pyrrolidone; Step 3: taking the polyvinylidene fluoride solution, adding the aqueous solution prepared in step 2, and ultrasonic mixing; Step 4: preparing polystyrene solution, and the solvent is toluene; Step 5: first UV treatment of the substrate; spin coating the mixed solution prepared in step 3 on the substrate, heat annealing treatment; then spin coating the PS solution prepared in step 4, heat annealing treatment; Step 6: placing the completed sample into a vacuum evaporation system, sequentially evaporating pentacene, the horizontal gate and the source-drain electrode; after evaporation, the device is placed in a dry nitrogen cabinet for storage, and the device is prepared.

2. The gated ionically doped salt-based neuromorphic device of claim 1, wherein: The substrate is Si / SiO2, and the thickness of SiO2 is 50 nm.

3. The gated ionically doped salt-based neuromorphic device of claim 1, wherein: The material of the electrolyte functional layer is ion salt doped polyvinylidene fluoride, and the material of the charge trapping layer is polystyrene.

4. The gated ionically doped salt-based neuromorphic device of claim 1, wherein: The material of the organic semiconductor layer is pentacene, and the thickness of the thin film is 30 nm.

5. The gated ionically doped salt-based neuromorphic device of claim 1, wherein: The material of the horizontal gate and the source-drain electrode is one of copper or gold, and the thickness of the electrode is 50 nm.

6. The gated ionically doped salt-based neuromorphic device of claim 1, wherein: The electrolyte functional layer and the charge trapping layer are formed into films by spin coating and annealing by using a solution method; the organic semiconductor layer, the horizontal gate and the source-drain electrode are prepared by using a vacuum evaporation method.

7. The gated ionically doped salt-based neuromorphic device of claim 3, wherein: The ion salt comprises one or more of sodium chloride, potassium chloride and lithium chloride.

8. A method for fabricating a gated transverse neuro morphic device doped with an ionic salt as claimed in any one of claims 1 to 7, characterized in that, The preparation method comprises the following steps: Step 1: preparing a Si / SiO2 substrate, ultrasonic cleaning and drying for standby; Step 2: preparing NaCl, KCl and LiCl aqueous solution; preparing polyvinylidene fluoride solution, and the solvent is N-methyl pyrrolidone; Step 3: taking the polyvinylidene fluoride solution, adding the aqueous solution prepared in step 2, and ultrasonic mixing; Step 4: preparing polystyrene solution, and the solvent is toluene; Step 5: first UV treatment of the substrate; spin coating the mixed solution prepared in step 3 on the substrate, heat annealing treatment; then spin coating the PS solution prepared in step 4, heat annealing treatment; Step 6: placing the completed sample into a vacuum evaporation system, sequentially evaporating pentacene, the horizontal gate and the source-drain electrode; after evaporation, the device is placed in a dry nitrogen cabinet for storage, and the device is prepared.

9. The method of claim 8, wherein the method further comprises: The NaCl, KCl, LiCl aqueous solution is prepared in step 2, and the solution concentration is 50 mg / ml; when the polyvinylidene fluoride solution is prepared, magnetic stirring should be performed for 10 h, so that the polyvinylidene fluoride is completely dissolved, and the mass ratio of the polyvinylidene fluoride is 5%; in step 3, 3 ml of the polyvinylidene fluoride solution is taken, 0.15 ml of the aqueous solution in step 2 is added, and ultrasonic mixing is performed for 1 h; in step 4, the polystyrene solution is prepared, the solvent is toluene, and the solution concentration is 6 mg / ml.

10. The method of claim 8, wherein the method further comprises: The evaporation rate of pentacene in step 6 is The vacuum degree is controlled at 5x10 -4 Pa, and the film thickness is monitored and controlled at 30 nm by using a crystal oscillator film thickness meter; the evaporation rate of the source drain electrode in step 6 is The film thickness is monitored and controlled at 30 nm by using a crystal oscillator film thickness meter.

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