Formation of semiconductor devices for unsealed environments

Abstract

This document describes a method (700) for forming an optical device (600) from a semiconductor wafer (401), wherein the optical device has facets (602, 603) at one end of an optical waveguide (601). The method includes: etching (701) the wafer to form an etched portion (402) having sidewalls (403) and a base, the sidewalls defining the facets; and applying a coating (604) to (702) the wafer (401). This facilitates the formation of a semiconductor device using a cost-effective method, which can operate in an unsealed environment and has conformal coatings on the facets and the upper surface of the chip.

Description

Technical Field

[0001] This invention relates to semiconductor devices that can be manufactured for extremely challenging environments. Background Technology

[0002] Standard lasers, electroabsorption modulated lasers (EMLs), Mach-Zehnder modulators, and waveguide photodetectors are widely used in telecommunications applications. These devices have waveguide structures and typically have front and rear facets.

[0003] A typical distributed feedback (DFB) laser structure includes optical waveguides with facets at opposite ends of the waveguide. A high-reflection (HR) coating can be applied to the rear facet. The rear facet acts as a rear mirror, and the front facet can act as a front mirror. An HR coating or an anti-reflection (AR) coating can be applied to the front facet. Light is emitted from the laser cavity on the front facet. The laser cavity typically includes an active layer inserted between p-type and n-type semiconductor material layers. The laser's waveguide comprises a material with a refractive index n, which is greater than the refractive index of the surrounding substrate. Light is emitted from the waveguide end on the front side of the laser.

[0004] HR facets can improve output power. AR facets can help reduce light reflection and can also improve output power. Typically, the upper surface of a laser has no additional coating except for the metal contacts at the top. Atomic layer deposition (ALD) coatings can be applied after bonding to the carrier.

[0005] A typical EML structure includes a DFB coupled to an electroabsorption modulator (EAM). The EAM section is typically docked to the DFB laser section. HR-coated facets on the DFB section can improve output power. AR-coated facets on the EAM section can reduce light reflection. Electrically, the DFB and EAM sections are isolated by ion implantation or etching.

[0006] Such equipment requires use in unsealed environments with humidity levels reaching 85% and temperatures reaching 85°C. For example, data center applications. However, the "gold box" packaging typically required for such applications is usually expensive and time-consuming to manufacture.

[0007] The characteristics of a laser or EML can change rapidly under conditions of 85% humidity and 85°C. EAM absorption characteristics may change, and laser characteristics may also change if the device is not properly protected. Figure 1(a) shows the change in output power over time when the EML device has no upper surface protection.

[0008] To enable these devices to operate effectively in unsealed environments, they are typically protected by various methods. ALDs can be used to deposit coatings on facets or on top of the chip surface. Alternatively, after the chip is bonded to a carrier, ALDs can be used to deposit various layers to protect the chip-on-carrier (COC) mount.

[0009] Typically, ALD layers are deposited on wafers to cover the top surface. Using ALD layers for AR / HR facet coatings is challenging because the deposition process can take approximately 3 hours to deposit a 20nm thick coating. Typical AR coatings for 1300nm-range lasers are approximately 800nm ​​thick, making this approach unsuitable for mass production. Furthermore, the high density of ALD layers leads to higher stress on the chip / device, potentially causing other reliability failure modes.

[0010] Another known approach involves depositing an ALD layer on the top surface of the chip and using a properly designed unsealed AR / HR coating to protect the facets. In this approach, the seam area between the facets and the top surface needs proper protection because any defects in the seam area are susceptible to water intrusion, especially if the reinforcing bars were mechanically cut to form the facets.

[0011] When coating the top surface with SiO2, using plasma-enhanced chemical vapor deposition (PECVD) or physical vapor deposition (PVD) may result in smaller changes in EML characteristics and potentially longer device lifetime, such as... Figure 1 As shown in (b). However, PECVD or PVD coatings may not be conformal, and pinholes may exist on the surface, such as... Figure 2 As shown. Figure 3 As shown, such chips may fail due to water intrusion. The weakest point is the seam area between the top ALD coating and the AR / HR coating.

[0012] The device also needs to withstand 2000 to 5000 hours at 85°C / 85% humidity. This requires very high quality facet cutting and excellent protection of the seam area between the top surface and the AR / HR coating, which is difficult to guarantee during mass production if standard strip cutting methods are used.

[0013] The hope is to develop new methods for producing these devices so that they can operate in unsealed or similar environments at a reduced cost. Summary of the Invention

[0014] According to one aspect, a method for forming an optical device from a semiconductor wafer is provided, wherein the optical device has a facet at one end of an optical waveguide, the method comprising: etching the wafer to form an etched portion having sidewalls and a base, the sidewalls of the etched portion defining the facet; and applying a coating onto the wafer.

[0015] This facilitates the use of a cost-effective method to form semiconductor devices that can operate in an unsealed environment, with conformal coatings on the upper surface and facets of the chip.

[0016] The method may further include applying stress to the wafer to cause it to be cut, the cutting being performed along the base of the etched portion. The cutting may begin at the base of the etched portion. The wafer may be cut into strips. Cutting the wafer along the bottom of the etched portion prevents damage to the facets and the coating.

[0017] The coating can be applied to the facets and the upper surface of the wafer. This allows the coating to conform to the upper surface and the facets, creating a conformal, continuous coating across the entire wafer.

[0018] The coating can form a continuous layer between the upper surface and the facets, allowing the device to operate in a non-sealed environment.

[0019] The coating can be applied to both the upper surface and the facet simultaneously. This allows for efficient device fabrication by enabling the coating to be applied across the entire wafer and can facilitate the formation of continuous coatings.

[0020] Applying a coating to the wafer can include applying the coating to the entire upper surface of the wafer. This facilitates simultaneously applying the coating to multiple chips formed from a single wafer before the wafer is diced into individual strips comprising chips.

[0021] The coating can be a sealing coating. This helps the device operate under conditions of 85% humidity and 85°C. The sealing coating can be substantially airtight and / or watertight. Therefore, the coating provides an external seal, and the portion of the device beneath the coating can be protected in a humid and / or damp environment.

[0022] The sealing coating can form part of an anti-reflective coating or a high-reflective coating. This prevents cuts between coatings and water intrusion.

[0023] The method may also include applying an anti-reflective coating or a high-reflective coating to the facets. This allows each facet to be coated individually, where appropriate.

[0024] The process of applying a coating to the wafer can be performed using atomic layer deposition (ALD). This can be a convenient way to provide the necessary coating properties for devices used in unsealed environments.

[0025] The coating thickness can range from 10 nm to 250 nm. This can provide appropriate protection for the device in its operating environment.

[0026] The coating may include one or more of Al2O3, SiN, Ta2O5, and SiO2. This coating material can provide protection for the device in its operating environment.

[0027] The base can be deeper in the wafer than it is in the facets. This prevents damage to the facets during the dicing of the wafer into strips, each strip including one or more semiconductor devices.

[0028] The etching step of the wafer can be performed using dry etching or wet-dry etching processes. Such processes can conveniently perform etching steps on the semiconductor wafer.

[0029] The depth of the sidewall of the etched portion can be between 1.0 μm and 10.0 μm. This allows for suitable dimensions for the facet.

[0030] The sidewall may be perpendicular to the longitudinal axis of the waveguide. The sidewall can effectively function as a facet during operation of the device.

[0031] The step of applying stress to the wafer to cleave it can form a semiconductor chip including the device. The wafer can be cleaved into multiple chips. Therefore, the top surfaces and facets of multiple chips or devices can be coated simultaneously before the wafer is cleaved into individual chips or devices.

[0032] According to another aspect, a semiconductor device formed by the above method is provided, wherein the device is a Fabry-Perot laser, a DFB laser, a DBR laser, a tunable laser, an electro-absorption modulated laser, a Mach-Zehnder modulator, or a waveguide photodetector. Therefore, all methods can be used to manufacture a range of optical devices.

[0033] The semiconductor device can be used to operate in unsealed environments. This is desirable for applications such as data centers.

[0034] According to another aspect, an optical device is provided, formed on a semiconductor wafer having an upper surface, a lower surface, and a side surface. The optical device has an optical waveguide, a facet defined at an end of the optical waveguide, and a diced surface adjoining the facet. The diced surface intersects the upper surface, the lower surface, and the side surface, and includes a fracture initiation region offset from the upper surface, the lower surface, and the side surface and spatially offset from the facet. Attached Figure Description

[0035] The invention will now be described by way of example with reference to the accompanying drawings.

[0036] In the attached diagram:

[0037] Figure 1 (a) shows the percentage change in output power over time when the EML device has no upper surface protection;

[0038] Figure 1 (b) shows the percentage change in output power over time when the upper surface of the EML device is coated with SiO2 using PECVD or PVD.

[0039] Figure 2 The defects that may occur in coated devices are shown;

[0040] Figure 3 An example of a chip with a failed protective coating is shown;

[0041] Figure 4 (a) shows a scanning electron microscope (SEM) image of a wafer with the etched portion described herein;

[0042] Figure 4 (b) shows a SEM image of the cross-section of the etched portion;

[0043] Figure 5 The coating applied to the upper surface of the device and facets is shown;

[0044] Figure 6 (a) shows a schematic top view of the EML formed by the method described herein;

[0045] Figure 6 (b) A schematic diagram of the cross-section of the EML formed by the method described herein is shown;

[0046] Figure 6 (c) Shows a SEM image of the EML back facet cross section having a sealed ALD coating and multiple HR coatings formed by the method described herein;

[0047] Figure 7An example of a method for forming optical devices from semiconductor wafers is shown. Detailed Implementation

[0048] The method described in this paper uses a combination of wafer-on-wafer etching and wafer-on-wafer coating to produce optical devices suitable for operation in unsealed environments.

[0049] Figure 4 (a) shows an SEM image of a semiconductor wafer, shown in 401. The semiconductor wafer may be made of one or more semiconductor materials, including but not limited to InP, GaAs, Si, and GaN / AlN. The semiconductor wafer has a top surface, a bottom surface, and side surfaces.

[0050] At least one small facet of the optical device is formed using a wafer-level etching process. The etched portion is formed on the wafer. Figure 4 (a) is shown as 402. The wafer can be etched using processes such as dry etching or wet-dry etching. Multiple etched portions can be formed on the wafer. This facilitates the formation of multiple devices from a single wafer. Therefore, the etching process is performed before the wafer is diced into strips.

[0051] The etched facets are located at one end of the device's waveguide. The waveguide comprises a material with a refractive index n, which is greater than the refractive index of the surrounding material. Light propagates along the waveguide. The device preferably includes facets at opposite ends of the waveguide. During operation, light is emitted from the front facet of the device. The rear facet receives the incident light signal and can act as a rear reflector.

[0052] The etched portion includes a sidewall 403. The sidewall may be parallel to the side surface of the wafer. The sidewall of the etched portion defines a facet of a semiconductor device formed from the wafer. The facet is preferably perpendicular to the longitudinal axis of the waveguide of the device. The etching depth of the facet (corresponding to the height of the sidewall) is preferably between 1.0 and 10.0 μm. The etched portion may also include a second sidewall opposite to the first sidewall. Figure 4 (b) is shown as 404. The second sidewall is preferably parallel to the first sidewall. The second sidewall may define a facet of another semiconductor device formed when the wafer is diced into strips. Each strip includes one or more semiconductor device chips. Thus, the etched portion including the two sidewalls may be formed at the interface between two regions of the wafer that will be formed as two separate devices or chips.

[0053] The etched portion also includes a base. The base is preferably formed by etching simultaneously with and / or in the same etching step as the sidewalls. The base and sidewalls can also be formed by processes other than etching (i.e., another suitable material removal process).

[0054] The base is located deeper in the wafer than in the facet (and therefore deeper than the sidewalls). The base of the etched portion preferably has a maximum depth extending more than 10% of the total planar area of ​​the base. This maximum depth can be defined by a base wall or line that is not parallel to the upper surface of the wafer.

[0055] Conveniently, a portion of the base is offset from a facet parallel to the main plane of the wafer and / or perpendicular to the facet. Figure 4 In the examples shown in (a) and 4(b), the base is defined by a pair of walls 405, 406, which are adjacent to their respective sidewalls 403, 404 and converge at an edge 407 that extends into the wafer beyond the deepest edge of the facet. The base may be tapered. Figure 4 In the examples shown in (a) and 4(b), the base of the etched portion is typically V-shaped in cross-section. The base includes and / or is defined by two bases 405, 406 intersecting at vertex 407. Bases 405, 406 may be walls. Bases 405, 406 are planar and intersect along a linear region 407 at the deepest part of the base (maximum depth). The line of the region preferably extends parallel to the plane of one or both of the sidewalls 403, 404. The linear region at maximum depth is deeper in the wafer than in the facet. The V-shape of the etched portion base helps the wafer to be mechanically cut into strips by initiating a cut away from the facet. This avoids damage to the coating in the facet and facet region, as well as in the seam region between the facet and the top surface. In other words, sidewalls 403, 404 are located on either side of the channel in the wafer. The base region defined by walls 405, 406 defines the base of the channel. Due to the base region, the deepest portion of the channel (407) is spatially offset from the facet defined by the sidewall 403. Furthermore, the deepest portion of the channel is defined by the acute-angled edge where walls 405 and 406 intersect. Each of these features means that when the wafer is subjected to stress, such as appropriate bending stress through the channel, wafer cutting will typically begin at a point offset from facet 403 and extend through the wafer to a depth away from facet 403. This makes wafer cutting easier without damaging facet 403.

[0056] Alternatively, the base can be U-shaped. The base can have a region or point where the distance between the deepest point of the base (the region or point of maximum depth) and the lower surface of the wafer is smaller than that of the region closer to the facet, i.e., the wafer is thinner at that point or region, so that the cut begins from the thinnest part of the base.

[0057] The base can have other suitable shapes or contours.

[0058] Therefore, the base includes the portion where cutting begins preferentially when stress is applied to the base of the etched portion, as will be described in more detail below. This portion is away from the facet so that the facet and the coating applied to it, as will be described in more detail below, are not damaged by the cutting process.

[0059] After the etched portions are formed in the wafer, a coating is applied to the wafer. The coating is applied to the entire wafer so that if the wafer has multiple etched portions, the coating will cover the top surface of the wafer and each sidewall (defining the facet of the semiconductor device manufactured from the wafer) and the base of the etched portions. Therefore, the coating can be applied to the entire wafer in one step, rather than to individual portions of the wafer.

[0060] The coating is preferably a sealing coating. The sealing coating is essentially airtight and / or watertight. Therefore, the coating provides an external seal, and portions of the device beneath the coating are protected from humid and / or damp environments. Furthermore, a sealing HR or AR coating can be applied over the sealing coating, either before or after the wafer is diced, as will be described in more detail below.

[0061] Once coated in this way, the device can operate in an unsealed environment and does not need to be packaged in a "gold box". The chip itself can withstand humid conditions, high temperatures, contamination, etc.

[0062] In a preferred embodiment, atomic layer deposition (ALD) is used to coat the wafer. ALD is a chemical vapor deposition method based on sequential, self-saturating surface reactions. Two or more precursor chemicals, each containing a different element of the material to be deposited, are introduced onto the substrate surface, one at a time. Each precursor saturates the surface, forming a monolayer material. The resulting film is very dense, highly conformable, and free of pinholes, making it an ideal method for depositing surface coatings to improve hermeticity.

[0063] Following the etching process used to form facets, a coating is applied at the wafer level. Coating processes, such as ALD, are used to deposit thin layers of material, or combinations of materials. Coating materials can include, but are not limited to, one or more of Al₂O₃, SiN, Ta₂O₅, and SiO₂. Conveniently, the coating thickness can be between 10 nm and 250 nm. When using ALD, the ALD layer is preferably between approximately 10 nm and 100 nm to minimize stress on the wafer and protect the device surface from water intrusion during operation.

[0064] Therefore, the coating is applied to both the upper surface of the wafer and the facet simultaneously, and as... Figure 5As shown, coating 501 forms a continuous layer between the upper surface 502 and the facet 503.

[0065] After etching and coating, the wafer is diced into strips, each strip including at least one semiconductor device. Stress is applied to the wafer to cause it to be diced along the base of the etched portion. The dicing begins at the base of the etched portion.

[0066] exist Figure 4 In the preferred implementations shown in (a) and 4(b), the V-shape of the base formed during the facet etching process helps to mechanically dicing the wafer into strips by concentrating stress at the vertex 407 where the base portions 405 and 406 meet. Therefore, the dicing is performed along the line defining the deepest part of the base. During dicing, the facets are not subjected to impact, i.e., no mechanical force is applied directly to the facets, minimizing potential damage. Therefore, since the base is far from the facets, the facets may not be affected by stress during dicing.

[0067] Because the dicing begins away from the facet and extends along the base of the etched portion, there are no weaknesses in the coating near the facet. The coating and facet are relatively undisturbed during dicing because the wafer is diced along the base of the etched portion away from the facet.

[0068] After dicing, the optical device includes a diced surface that intersects with the upper, lower, and side surfaces of the wafer, and includes a fracture initiation region that is offset from the upper, lower, and side surfaces of the wafer and spatially deviates from the facets.

[0069] After applying the ALD sealing coating and after dicing, a properly designed sealing AR or HR coating can be applied to the facet using conventional coating methods to further protect the chip under unsealed conditions. The design of this AR or HR coating can take into account the influence of the thin ALD layer on the coating's reflective properties.

[0070] Alternatively, an AR or HR coating (or a further AR / HR coating) can be applied to the wafer after the sealant coating and before dicing the wafer into strips. The AR / HR coating can be applied to the facets and the top surface of the wafer. The AR / HR coating can form a continuous layer between the top surface and the facets. The AR / HR coating can be applied to both the top surface and the facets simultaneously. The AR / HR coating can also be applied to the base of the etched portion.

[0071] The sealing ALD layer previously applied to the small surface can be further protected by AR or HR coating.

[0072] The device formed by the method described herein may have a second facet at the end of the waveguide opposite to the first facet described above. The second facet may be defined by the sidewall of the second etched portion. During wafer coating, a coating may be applied to the second facet. Stress may be applied to the wafer, causing the wafer to be cut along the base of the second etched portion. Strips comprising semiconductor devices may be formed, wherein each facet at the opposite end of the waveguide has been formed by the method described herein. Each facet may optionally have other coatings. For example, the facet at the emitting surface of the semiconductor device (front facet) may be further coated with an AR coating, and the facet at the light-entering surface of the device (rear facet) may be coated with an HR coating, as described above.

[0073] Preferably, the two facets of the device are formed by etching as described herein, so that a coating can then be applied continuously across the upper surface of the wafer and the front and rear facets of the device. Using this facet etching process, the facets are formed prior to dicing, which avoids the need for mechanical dicing processes to form the facets.

[0074] Alternatively, the method may also include forming a second facet at opposite ends of the waveguide using conventional cutting. Thus, only one facet of the device (i.e., the rear facet or the front facet) can be formed by the etching process described above.

[0075] Figure 6 (a) to Figure 6 (c) shows an example for implementing the EML described herein. The EML includes a DFB laser optically coupled to the EAM, with an intermediate isolation region. The waveguide of the device is shown at 601. The waveguide of the device comprises a material with a refractive index n, which is greater than the refractive index of the surrounding substrate. The rear (HR) facet is shown at 602, and the front (AR) facet is shown at 603. Light is emitted from the waveguide end of the front facet 603 of the device. Both the DFB and the EAM include active layers of multi-quantum-well material (MQW1 / 2) interposed between layers of p-type and n-type semiconductor material. The layers extend in a direction extending between the rear and front facets. The DFB laser also includes a Bragg grating.

[0076] The ALD coating is shown in 604. As described above, the coating is deposited during wafer processing, prior to dicing. The coating is applied to the upper surface of the wafer and also to the facets 602, 603 formed by etching. Thus, a continuous, conformal, dense, and sealing thin ALD layer 604 covers the facets and the upper surface of the chip.

[0077] This allows for the convenient elimination of weaknesses in the coating. The coating can be watertight. Furthermore, only a thin ALD layer is required. Therefore, deposition time is manageable, and stress can be minimized.

[0078] After the strip is cut, the ALD coating 604 is integrated with the sealing HR and AR coatings, as shown in 605 and 606 respectively. Thus, the ALD layer forms part of the HR and AR coatings.

[0079] Figure 6 (c) shows a SEM image of the cross-section of the EML back facet 602 with a sealed ALD coating 604 and multiple HR coatings 605.

[0080] The device is well protected from humid / thermal environments due to the sealing coating applied to the upper and facet surfaces, and optionally an additional AR / HR coating applied to at least the facet surfaces and optionally the upper surface. In some implementations, the upper surface and surface seam area can withstand an environment of 85°C / 85% humidity for at least 2000-5000 hours.

[0081] Figure 7 An example of a method 700 for forming an optical device from a semiconductor wafer is shown, wherein the optical device has a facet at one end of an optical waveguide. In step 701, the method includes etching the wafer to form an etched portion having sidewalls and a base, the sidewalls defining the facet. In step 702, the method includes applying a coating onto the wafer. The wafer can then be cut along the base of the etched portion to form strips, each strip including a corresponding semiconductor device.

[0082] In this way, a sealing ALD layer can be deposited, which covers not only the top surface of the device, but also the front facet and / or the rear facet.

[0083] After the wafer is diced, the ALD layer can be integrated with the AR / HR coating (depending on the situation) by adjusting the coating design, and the device is well protected in humid and hot environments. The ALD layer can form part of both the HR and AR coatings. Because the ALD layer is conformal, the seam area between the top surface and the facets is not considered a weakness. However, if necessary, the ALD layer can be etched away from the gold wire bonding area on the chip.

[0084] The method described herein allows for high-quality facet cutting and excellent protection of the seam area between the upper surface and the facet coating. The combination of wafer etching to form facets and wafer-level ALD coating can enable chips to withstand 85% humidity and 85°C temperatures for over 2000 hours.

[0085] This method can be used to fabricate a range of optical semiconductor devices, such as Fabry-Perot lasers, DFB lasers, DBR lasers, tunable lasers, electro-absorption modulated lasers, Mach-Zehnder modulators, and waveguide photodetectors. These devices can operate efficiently and reliably under unsealed conditions. The semiconductor chip can function as an on-board chip, eliminating the need for a "gold box" package, allowing for low-cost solutions in unsealed environments. The process is suitable for mass production and allows many devices to be coated onto a wafer in a single step.

[0086] The applicant hereby separately discloses each individual feature described herein, as well as any combination of two or more such features. In this sense, given the common knowledge of those skilled in the art, such features or combinations can be implemented as a whole according to this specification, regardless of whether such features or combinations of features solve any problem disclosed herein, and without limiting the scope of the claims. This application demonstrates that aspects of the invention can be constituted by any such individual features or combinations of features. Various modifications that can be made within the scope of the invention will be apparent to those skilled in the art in light of the foregoing description.

Claims

1. A method (700) for forming an optical device (600) from a semiconductor wafer (401), characterized in that, The optical device has facets (602, 603) at one end of the optical waveguide (601), and the method includes: The wafer is etched (701) to form an etched portion (402), the etched portion having a sidewall (403) and a base, the sidewall defining the facet, and the base being located deeper in the wafer (401) than in the facet (602, 603); A coating (604) is applied (702) onto the wafer (401); the coating (604) is applied to the facets (602, 603) and the upper surface of the wafer (401), and the coating (604) forms a continuous layer between the upper surface and the facets; Stress is applied to the wafer (401) to cut it, the cutting being performed along the base of the etched portion (402).

2. The method according to claim 1, characterized in that, The coating (604) is applied to both the upper surface and the facet.

3. The method according to any one of claims 1-2, characterized in that, Applying the coating (604) to the wafer (401) includes applying the coating to the entire upper surface of the wafer.

4. The method according to claim 1, characterized in that, The coating (604) is a sealing coating.

5. The method according to claim 4, characterized in that, The sealing coating (604) forms part of an anti-reflective coating or a high-reflective coating (605).

6. The method according to claim 4, characterized in that, The method further includes applying an anti-reflective coating or a high-reflective coating (605) to the small surface.

7. The method according to claim 1, characterized in that, The step of applying the coating (604) onto the wafer is performed using an atomic layer deposition process.

8. The method according to claim 1, characterized in that, The thickness of the coating is between 10 nm and 250 nm.

9. The method according to claim 1, characterized in that, The coating (604) includes one or more of Al2O3, SiN, Ta2O5 and SiO2.

10. The method according to claim 1, characterized in that, The etching (701) step of the wafer (401) is performed using a dry etching or dry-wet etching process.

11. The method according to claim 1, characterized in that, The depth of the sidewall (403) of the etched portion (402) is between 1.0 μm and 10.0 μm.

12. The method according to claim 1, characterized in that, The sidewall (403) is perpendicular to the longitudinal axis of the waveguide.

13. The method according to claim 1, characterized in that, Stress is applied to the wafer (401) to cut it to form a semiconductor chip including the device.

14. A semiconductor device formed by the method of any one of the preceding claims, characterized in that, The device is a Fabry-Perot laser, a DFB laser, a DBR laser, a tunable laser, an electroabsorption modulated laser, a Mach-Zehnder modulator, or a waveguide photodetector.

15. The semiconductor device according to claim 14, characterized in that, The device is designed for operation in unsealed environments.

16. An optical device (600), characterized in that, Formed on a semiconductor wafer (401) having an upper surface, a lower surface, and a side surface, the optical device has an optical waveguide (601), facets (602, 603) defined at the ends of the optical waveguide, and a diced surface adjoining the facets, the diced surface intersecting the upper surface, the lower surface, and the side surface, and including a fracture initiation region offset from the upper surface, the lower surface, and the side surface and spatially offset from the facets; The wafer is formed with an etched portion (402), the etched portion having a sidewall (403) and a base, the sidewall of the etched portion defining the facet, and the base being located deeper in the wafer (401) than in the facet (602, 603); The wafer (401) is coated with a coating (604), which is a sealing coating; the coating (604) is applied to the facets (602, 603) and the upper surface of the wafer (401), and the coating (604) forms a continuous layer between the upper surface and the facets.

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