Method and apparatus for determining current of a motor or generator

Abstract

According to an embodiment, a method for determining a current of a motor or a generator is provided, comprising the steps of: obtaining a characteristic of a filter that filters noise generated in determining the current of the motor or the generator; determining a time delay generated by the filter based on a phase change of the characteristic of the filter that is determined by a change of an operating frequency of the motor or the generator; and determining the current of the motor or the generator by compensating for the time delay.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to a method and apparatus for determining current of a motor or generator, and more particularly, to a method and apparatus for controlling current of a motor or generator by effectively compensating for time delay generated by a filter. BACKGROUND

[0002] Generally, a control system of a 3-phase synchronous motor / generator is composed of a power conversion section using pulse width modulation (PWM) and a real-time control section for controlling torque / current / speed / position, etc. Most basically, in order to control torque, a current signal of the motor / generator is measured, and after converting a 3-phase rotating coordinate system into a 2-phase stationary coordinate system, current control is performed according to position information of a rotor, thereby generating a required torque. At this time, in order to measure current of the 3-phase synchronous motor / generator, a non-contact sensor such as a Hall sensor is used, and in order to remove electric noise and harmonic noise signals such as PWM contained in the current signal, a low-pass filter must be used, and the low-pass filter used to measure the current signal can be composed of various forms such as an analog filter and a digital filter. However, due to the influence of the filter, the output signal of the filter generates time delay compared to the input signal. This time delay is called group delay, and there is a difference equal to the group delay in the synchronization of the measured current signal and the position information of the rotor, resulting in a phase distortion of d-q axes of the 2-phase stationary coordinate system of the synchronous motor / generator control system, thereby resulting in a result that optimal performance cannot be obtained.

[0003] In order to solve the above problem, a technology is proposed in which when measuring current, a bandwidth of a filter is set to be greater than a basic driving frequency of a motor / generator to reduce group delay to a controllable level, or in a case where group delay cannot be easily obtained in a simple first-order RC filter, compensation is made using a look-up table.

[0004] However, this method has an aspect that it is difficult to use in a high-speed instrument in which the synchronous resistance and inductance of the motor are very small, and has a problem that high-frequency noise generated by PWM and switching noise of a power conversion device cannot be effectively removed. To solve this problem, at least a filter of two or more stages is provided at a current measurement sensor, and an anti-aliasing filter (AAF) is provided at a front end of an analog-digital converter (ADC) used for a digital motor control algorithm operation, and a digital filter such as a FIR filter should be used to remove electrical noise from a signal passing through the ADC, but as described above, if the performance of the filter is improved, the result is that the delay time caused by the filter also increases, which is a cause of reducing the control performance of the motor / generator.

[0005] Thus, the demand for a technology for solving the above-described problems is gradually increasing. SUMMARY

[0006] TECHNICAL PROBLEM

[0007] An embodiment of the disclosure for solving the foregoing problems of the related art can provide a method and apparatus for controlling the current of a motor or the above-described generator, which can effectively compensate for the time delay caused by a filter.

[0008] The object of the disclosure is not limited to the above-mentioned objects, and other objects not mentioned can be clearly understood from the following description.

[0009] TECHNICAL SOLUTION

[0010] The method for determining the current of a motor or a generator according to the first aspect of the disclosure can include the steps of obtaining a characteristic of a filter that filters noise generated in determining the current of the motor or the generator, determining a time delay caused by the filter based on a phase change of the characteristic of the filter determined based on a change in an operating frequency of the motor or the generator, and determining the current of the motor or the generator by compensating for the time delay.

[0011] Also, the magnitude of the characteristic of the filter and the phase of the characteristic of the filter can be determined based on the operating frequency.

[0012] Also, the filter can include at least one of a low-pass filter, an anti-aliasing filter, and a finite impulse response (FIR) filter.

[0013] Also, the filter includes a low-pass filter, an anti-aliasing filter, and an FIR filter, and the time delay can be determined by adding a first time delay generated by the low-pass filter, a second time delay generated by the anti-aliasing filter, and a third time delay generated by the FIR filter.

[0014] Also, in the step of determining the current of the generator, the current phase of the motor or the generator can be updated according to a value obtained by multiplying the time delay by the operating frequency.

[0015] Also, in the step of determining the time delay, the time delay can be determined by using a phase of a transfer function representing characteristics of the filter using the operating frequency as a variable input.

[0016] Also, when the transfer function (G2(s)) satisfies the following mathematical expression (1), the time delay (p2) can satisfy the following mathematical expression (2).

[0017]

[0018]

[0019] The apparatus for determining a current of a motor or a generator according to the second aspect of the present disclosure can include a filter that filters noise generated in a process of determining the current of the motor or the generator, and a processor that obtains characteristics of the filter, determines a time delay generated by the filter based on a phase change representing the characteristics of the filter determined by a change in an operating frequency of the motor or the generator, and determines the current of the motor or the generator by compensating for the time delay.

[0020] Also, a magnitude representing the characteristics of the filter and a phase representing the characteristics of the filter can be determined by the operating frequency.

[0021] Also, the filter can include at least one of a low-pass filter, an anti-aliasing filter, and an FIR filter.

[0022] Also, the filter includes a low-pass filter, an anti-aliasing filter, and an FIR filter, and the time delay can be determined by adding a first time delay generated by the low-pass filter, a second time delay generated by the anti-aliasing filter, and a third time delay generated by the FIR filter.

[0023] Also, the processor can update the current phase of the motor or the generator according to a value obtained by multiplying the time delay by the operating frequency.

[0024] Also, the processor determines the time delay by using a phase of a transfer function of the filter representing a characteristic of the filter at the operation frequency, the phase of the transfer function using the operation frequency as a variable input.

[0025] Also, when the transfer function (G2(s)) satisfies the following mathematical expression (1), the time delay (p2) can satisfy the following mathematical expression (2).

[0026]

[0027]

[0028] A third aspect of the present disclosure can provide a computer-readable recording medium recording a program for executing the method of the first aspect on a computer. Alternatively, a fourth aspect of the present disclosure can provide a computer program stored in a recording medium to implement the method of the first aspect.

[0029] Advantageous Effects

[0030] According to an embodiment of the present disclosure, the time delay generated by the filter is effectively compensated for, thereby making it possible to control the current of the motor or the generator.

[0031] Also, based on a characteristic analysis of various filters that can be used in the motor / generator control system, optimal compensation for the time delay of the filter can be performed.

[0032] Also, according to the effective time delay compensation, the mechanical output, the rotational speed, the torque in the same current, etc. can be significantly improved.

[0033] The effects of the present disclosure are not limited to the above-mentioned effects, and should be understood to include all possible effects derived from the detailed description of the present disclosure or the invention recited in the claims. BRIEF DESCRIPTION OF DRAWINGS

[0034] Figure 1 A block diagram briefly showing the structure of the current determination device of an embodiment.

[0035] Figure 2 A block diagram more specifically showing an example of the structure of the current determination device of an embodiment.

[0036] Figure 3 A block diagram showing the filter of the sixth embodiment.

[0037] Figure 4 A schematic diagram showing the operation of the device for explaining the sixth embodiment.

[0038] Figure 7A circuit diagram of a Sallen-key type low-pass filter of the fourth embodiment is shown.

[0039] Figures 8 to 9 A graph showing simulation results of the size characteristics and the time delay characteristics of the device of the fourth embodiment for a plurality of types of filters is shown.

[0040] Figure 10 A graph showing simulation results of the frequency response characteristics of the device of the sixth embodiment for a plurality of types of filters is shown.

[0041] Figure 11 A flowchart of a method for determining the current of a motor or a generator for a device of an embodiment is shown.

[0042] Figures 12 to 15 A graph showing simulation results of the device of an embodiment improved by effectively compensating for the time delay is shown. DETAILED DESCRIPTION

[0043] The terms used in the embodiments take into account the functions in the present disclosure and are chosen as much as possible from the conventional terms widely used at present, but this can differ according to the intention or judgment of one of ordinary skill in the art, the appearance of new technology, etc. Also, in a specific case, there is a term arbitrarily chosen by the applicant, in which case the meaning thereof is described in detail in the description part of the corresponding invention. Therefore, the terms used in the present disclosure should not be mere names of terms, but should be defined according to the meaning thereof and the entire contents of the present disclosure.

[0044] Throughout the specification, when a part "includes" a structural element, unless there is a special note to the contrary, it means that other structural elements are further included, not excluded. Also, the terms "… section", "… module" and the like described in the specification mean a unit that processes at least one function or action, which can be implemented by hardware or software, or can be implemented by a combination of hardware and software.

[0045] Hereinafter, the embodiments of the present disclosure are described in detail with reference to the accompanying drawings so that one of ordinary skill in the art to which the present disclosure pertains can easily practice the embodiments of the present disclosure. However, the present disclosure can be implemented in various different forms and is not limited to the embodiments described herein.

[0046] Hereinafter, the embodiments of the present disclosure are described in detail with reference to the accompanying drawings.

[0047] Figure 1 A block diagram briefly showing the structure of the current determination device 1000 of an embodiment is shown.

[0048] Reference Signs Figure 1The current determination device 1000 can include a filter 100 and a processor 200.

[0049] The filter 100 can filter noise generated in determining the current of the motor or generator 10. For example, the filter 100 can receive a current signal from a current sensing part (not shown) configured to measure a current signal of the motor or generator 10 at a front end of the filter 100, and output after removing noise included in the current signal.

[0050] In an embodiment, the filter 100 can include at least one of a low pass filter 110, an anti-aliasing filter 120, and a finite impulse response (FIR) filter 130, but is not limited thereto, and can include various filters required in controlling the current of the motor or generator 10, and can be configured in various forms such as an analog filter and a digital filter.

[0051] In an embodiment, the filter 100 can be implemented by including one or more filters having an order of one or more stages. For example, the low pass filter 110 can be configured by a first order filter or a second order filter, or a combination of one or more first order filters and second order filters, and thus can be designed to have a specific order.

[0052] The processor 200 can obtain a characteristic of the filter 100. In an embodiment, a magnitude representing the characteristic of the filter 100 and a phase representing the characteristic of the filter 100 can be determined according to an operating frequency. For example, the processor 200 can determine a magnitude function and a phase function in a frequency domain using a transfer function representing the characteristic of the filter 100 that has been stored. In an embodiment, information (e.g., a transfer function, order information, a circuit implementation, a circuit design parameter, etc.) representing the characteristic of the filter 100 can be stored in a memory according to a user setting, or can be received from a user interface or an external device.

[0053] The processor 200 can determine a time delay generated by the filter 100 based on a phase change representing the characteristic of the filter 100 determined by a change in the operating frequency of the motor or generator 10. In an embodiment, the time delay can be determined by using a phase of a transfer function representing the characteristic of the filter 100 using a differential of the operating frequency as a variable input.

[0054] The processor 200 can determine the current of the motor or generator 10 by compensating for the time delay. In one embodiment, the processor 200 can update the phase of the current of the motor or generator 10 according to a value obtained by multiplying the time delay by the operating frequency. For example, the processor 200 can obtain the product of w calculated according to the position information of the rotor after compensating for the attenuation ratio of the gain function by adding the first to third time delays generated by the low-pass filter 110, the anti-aliasing filter 120, and the FIR filter 130, respectively, after the time delay.

[0055] Hereinafter, a detailed description will be given of the current determination apparatus 1000 according to an embodiment of the present application with reference to the accompanying drawings. Figures 2 to 9 Various embodiments of determining and compensating for the time delay generated by the filter 100 will be further described.

[0056] Figure 2 A block diagram of an example of the structure of the current determination apparatus 1000 according to an embodiment of the present application will be described in more detail.

[0057] Referring to FIG. 10, Figure 2 , the current determination apparatus 1000 can be divided into a first portion 1000a that determines the time delay generated by the filter 100 according to the characteristics of the filter 100 and a second portion 1000b that determines and controls the current of the motor or generator 10 according to the determined time delay.

[0058] In one embodiment, with respect to the first portion 1000a, the processor 200 can include a differentiator 210 and a time delay calculator 220.

[0059] In one embodiment, the differentiator 210 can differentiate the phase of the transfer function representing the characteristics of the filter 100 using the operating frequency, for example, can receive the phase angle θ from a rotor position detection unit (not shown) configured to detect the position of the rotor of the motor or generator 10 at the front end of the differentiator 210, and differentiate the phase function determined according to the transfer function of the low-pass filter 110 using the operating frequency w to determine a time delay function (p(t)) representing the characteristics of the time delay p.

[0060] In one embodiment, the time delay calculator 220 determines the time delay (e.g., T g ) according to the time delay function (p(t)) determined by the differentiator 210, and can determine a phase compensation value θ d for time delay compensation by multiplying the determined time delay by the operating frequency of the motor or generator 10.

[0061] In one embodiment, with respect to the second portion 1000b, the processor 200 can update the phase θ of the current of the motor or generator 10 according to the phase compensation value θ dThe current of the motor or generator 10 is determined, and the drive of the motor or generator 10 can be controlled according to the determined current.

[0062] The above operations can be performed in different ways depending on the characteristics of filter 100. The following describes the specific methods for more accurately determining and compensating for time delay based on various filter orders and filter implementation methods.

[0063] In the first embodiment, the low-pass filter 110 included in the filter 100 is a first-order filter. When the first transfer function (G1(s)) of the low-pass filter 110 satisfies mathematical formula 1, the first time delay (ρ1) can satisfy mathematical formula 4. More specifically, the first transfer function of the low-pass filter 110 contains the gain and phase information of the input or output signal, which can be represented by mathematical formula 1. The processor 200 can use the frequency domain operator (s = jw) to replace the first transfer function of mathematical formula 1 to determine the first magnitude function (M1) and the first phase function (Ψ1) of the low-pass filter 110 as mathematical formula 2 and mathematical formula 3, respectively. Differentiating the first phase function (Ψ1) of mathematical formula 3 for frequency w, the first time delay (ρ1) representing the instantaneous delay time of the frequency is thus determined as mathematical formula 4.

[0064] Mathematical Formula 1

[0065]

[0066] Mathematical formula 2

[0067]

[0068] Mathematical Formula 3

[0069]

[0070] Mathematical expression 4

[0071]

[0072] The frequency gain and time delay curves of the first embodiment are shown in the figure below. Figure 5 As shown, it can be confirmed that the maximum time delay varies depending on the frequency, with w being the highest. n -1 , in (0.1*w n ~w n In the region, the change in time delay per unit frequency is the largest, and at the position of -3dB gain, it becomes 1 / 2 of the maximum time delay.

[0073] In the second embodiment, the low-pass filter 110 included in the filter 100 is a second-order filter, and when the second transfer function (G2(s)) of the low-pass filter 110 satisfies the mathematical expression 5, the second time delay (p2) can satisfy the mathematical expression 8. More specifically, the second transfer function of the low-pass filter 110 can be expressed by the mathematical expression 5, the processor 200 can determine the second magnitude function (M2) and the second phase function (Ψ2) of the low-pass filter 110 as the mathematical expressions 6 and 7, respectively, by substituting the second transfer function of the mathematical expression 5 with a frequency domain operator (s = jw), and differentiate the second phase function (Ψ2) of the mathematical expression 7 with respect to the frequency w, whereby the second time delay (p2) representing the instantaneous time delay of the frequency can be determined as the mathematical expression 8.

[0074] Mathematical expression 5

[0075]

[0076] Mathematical expression 6

[0077]

[0078] Mathematical expression 7

[0079]

[0080] Mathematical expression 8

[0081]

[0082] In the second embodiment, the processor 200 can determine the relationship between the frequency w and the second time delay (p2) as the mathematical expression 9 according to the mathematical expression 8. In an embodiment, the damping factor (ζ) can be set to an integer of 0 or more and less than 1, and in the case of ζ = 1, it can be confirmed that the frequency differs by 2 times in the range of (0 ~ w n ) and the group delay is increased by 2 times compared to the first-order filter.

[0083] Mathematical expression 9

[0084]

[0085] Among the plurality of damping factors (ζ) of the second embodiment, the magnitude of the frequency and the group delay are graphed as shown in Figure 6 , the damping factor can be applied to a value of 0 < ζ < 1, the group delay is smaller in the case of ζ < 0.7 than in the case of ζ = 1, has a maximum value near the cutoff frequency, and if the damping factor becomes smaller, it can be confirmed that the gain and the time delay in the cutoff frequency w n are greatly increased.

[0086] In the second embodiment, the processor 200 can calculate the peak value of the gain function according to mathematical formula 6, as shown in mathematical formula 10. Furthermore, the processor 200 can also calculate the peak value of the group delay, with a denominator of a fourth-degree polynomial and a numerator of a second-degree polynomial. Therefore, in the case of the differential frequency, the denominator term is an eighth-degree polynomial and the numerator term is a fifth-degree polynomial, resulting in multiple solutions. However, since the group delay is greater than 0, mathematical formula 11 can be used.

[0087] Mathematical formula 10

[0088]

[0089] Mathematical formula 11

[0090]

[0091] In the second embodiment, the processor 200 is based on the fact that (1-2ζ) must hold true to calculate the real value according to mathematical formula 10. 2 The condition that ζ > 0 is used to define the attenuation factor ζ of a second-order low-pass filter. The relationship can be determined according to mathematical formula 6, which is w n The gain function in the equation is determined as shown in mathematical formula 12.

[0092] Mathematical expression 12

[0093]

[0094] In the second embodiment, the processor 200 can determine the attenuation factor ζ such that the cutoff frequency w n The gain value in the equation becomes -3 [dB]. For example, ζ can be designed to be 0.707, so that the output value of equation 12 becomes -3 [dB].

[0095] In the third embodiment, the low-pass filter 110 included in the filter 100 may be composed of a combination of one or more first-order filters and second-order filters. For example, one or more of mathematical formulas 1 to 8 may be used as a high-order filter design.

[0096] In the fourth embodiment, the analog filter included in filter 100 may include an anti-aliasing filter 120. In one embodiment, the analog filter may be determined based on the circuit implementation and circuit parameters, for example, according to a Sallen-Key design or a multiful feedback design. The Sallen-Key design can be used to amplify signals with single gain or below 20 dB, while the multiful feedback design can be used to amplify signals above 20 dB.

[0097] The circuit diagram of the Salen-Kay low-pass filter 110 in the fourth embodiment is as follows: Figure 7 As shown, the third transfer function (A(s)) of the Salen-Kay low-pass filter 110 can be determined according to mathematical formula 13. In this case, the processor 200 can calculate the third time delay (ρ) using mathematical formula 13 in the same manner as in the embodiment described above. S Specifically, when the third transfer function (A(s)) of the low-pass filter 110 satisfies mathematical formula 13, the third magnitude function (M) of the low-pass filter 110... S ) and the third phase function (Ψ) S ) respectively satisfy mathematical expressions 14 and 15, the third time delay (ρ S It can satisfy mathematical expression 16.

[0098] Mathematical formula 13

[0099]

[0100] Mathematical formula 14

[0101]

[0102] Mathematical formula 15

[0103]

[0104] Mathematical formula 16

[0105]

[0106] In the fourth embodiment, the processor 200 can use mathematical formula 8 to obtain the filter coefficients and gain characteristic values ​​as shown in Table 1. In one embodiment, the resistance value of the circuit is set to R1 = R2 = R, thereby the capacitors C1 and C2 can be determined as shown in mathematical formula 17, but it is not limited to this. The user can also select specific input values ​​to set the resistance values.

[0107] Table 1

[0108] Type ​ <k2> Zeta Butt. 1.0 1.4142 0.7071 C 0.01 [dB] 1.0469 1.4118 0.6899 C 0.1 [dB] 1.2182 1.3695 0.6203 C 0.25 [dB] 1.2081 1.3581 0.6178 C 0.5 [dB] 1.2738 1.3066 0.5788 C 1 [dB] 1.3448 1.2125 0.5227 Bessel 0.6164 1.3599 0.8660 LP 0.05 [deg] 0.6832 1.3783 0.8337 LP 0.5 [deg] 0.8161 1.4022 0.7760 Ellipse 0.1076 0.4639 0.7071 Gaussian 0.0100 0.1847 0.9238

[0109] (Where Butt. refers to Butterworth, C refers to Chebyshev, and LP refers to Linear Phase.)

[0110] Mathematical formula 17

[0111]

[0112]

[0113] In the fourth embodiment, the processor 200 can obtain the magnitude (M2(0.5w n ) in the half cutoff frequency (=0.5w n ), the frequency (w Mp ) having the maximum magnitude, and the maximum magnitude value (M2(w Mp ) using Table 1 as shown in Table 2, and can confirm that the gain characteristics in the half cutoff frequency of the Butterworth filter, the Chebyshev filter, and the Elliptic filter do not vary much, but the gain characteristics of the Bessel filter, the Linear phase filter, and the Gaussian filter decrease as the frequency gradually increases.

[0114] Table 2

[0115] Type M1(0.5w n )]]> [M2(w Mp )]]> w Mp ]]> Zeta 0.97014 1.00000 0 Butt. 0.98129 1.00116 0.21915 C 0.01 [dB] 1.02739 1.02760 0.47982 C 0.1 [dB] 1.02912 1.02922 0.48641 C 0.25 [dB] 1.05551 1.05928 0.57431 C 0.5 [dB] 1.00383 1.12195 0.67336 C 1 [dB] 0.87287 1.15472 0 Bessel 0.89171 1.08613 0 LP 0.05 [deg] 0.92658 1.02159 0 LP 0.5 [deg] 0.97014 1.00000 0 Ellipse 0.84035 1.41421 0

[0116] In the fourth embodiment, the processor 200 can determine the group delay using Table 2, and can obtain the time delay characteristics shown in the frequency domain as shown in Table 3 and Gaussian Table 4. As described above, the time delay characteristics have a large difference according to the various filter types, the Butterworth filter, the Chebyshev filter, and the Gaussian filter show a large time delay variation rate, the Bessel filter, the Linear phase filter, and the Elliptic filter show the smallest time delay variation rate in the half cutoff frequency, and in particular, it can be confirmed that the Elliptic filter shows the smallest time delay up to 0.5w n .

[0117] Table 3

[0118] Figure 8 [ρ2(0)] ρ2(0.5w n )]]> ρ2(w n )]]> Type 1.414 1.664 1.414 Zeta 1.38 1.661 1.449 Butt. 1.241 1.637 1.612 C 0.01 [dB] 1.236 1.636 1.619 C 0.1 [dB] 1.158 1.612 1.728 C 0.25 [dB] 1.046 1.564 1.913 C 0.5 [dB] 1.732 1.65 1.155 C 1 [dB] 1.668 1.658 1.2 Bessel 1.552 1.666 1.289 LP 0.05 [deg] 0.464 0.546 0.464 LP 0.5 [deg] 1.848 1.631 1.082

[0119] In the fourth embodiment, the filter 100 can include an anti-aliasing filter 120, and the anti-aliasing filter 120 can include an Elliptic filter, for example, the anti-aliasing filter 120 can include an Elliptic filter configured in the front end of an Analog-Digital Converter (ADC) used for control algorithm operation of the motor or generator 10, and in this case, as shown in Table 3 and Ellipse Table 4, the characteristics of the Elliptic filter are relatively small in the difference through the frequency band and the time delay up to 0.5w ncharacteristics of the analog filter. In one embodiment, the IIR filter converts the mathematical expression 5 into a continuous state equation, and converts the converted expression into a discrete state equation to implement, for example, the discrete state equation of the IIR filter can be implemented using the mathematical expression 18, where, the mathematical expression f s denotes a sampling frequency, u(k) is an input signal of the filter, y(k) is an output signal of the filter, x1 and x2 are state variables, K is determined using the mathematical expression 19, the constants ζ, w n and f s are set by a user during a filter design process, the values in the matrix are all shown by constants, the output value of the IIR filter can be calculated by a calculation of the state equation, and similarly, the time delay can be calculated by calculating the mathematical expression 8, and in the same manner.

[0120] Mathematical expression 18

[0121]

[0122]

[0123] Mathematical expression 19

[0124]

[0125] In the fifth embodiment, the FIR filter has a certain group delay in all frequency regions, and can be implemented according to a direct realization method or an optimized realization method. In one embodiment, the direct realization method is determined by a calculation of the number of TAPs (N) of the FIR filter divided by the sampling frequency, and the optimized realization method can be determined according to the mathematical expression 20.

[0126] Mathematical expression 20

[0127]

[0128] Gaussian A block diagram of the filter 100 of the sixth embodiment is shown in FIG. 6, Figure 9A diagram for illustrating the operation of the apparatus 1000 of the sixth embodiment is shown.

[0129] Referring to Figure 3 , the filter 100 can include a low pass filter 110, an anti-aliasing filter 120, and a FIR filter 130. In one embodiment, in order to effectively control the motor or generator 10, the apparatus 1000 can be used by combining various types of filters, for example, in the case where the filter 100 utilizes a logic model (e.g., FPGA) in order to control a low pass filter 110 located at the current sensing section (not shown) for measuring the current of the motor or generator 10, an anti-aliasing filter 120 located at the front end of the ADC, and the ADC, and can include a FIR filter 130 located within the logic model, and can further include an IIR filter or the like, which can be connected to the processor 200 or the driving section 300 for real-time control of the motor or generator 10, and finally removes the electrical noise and the PMW frequency in the current signal.

[0130] Referring to Figure 4 , the filter 100 can include a Bessel type second order low pass filter 110 configured at the back end of the current sensing section, an elliptic type second order anti-aliasing filter 120 configured at the front end of the ADC, and a Blackman-Harris type FIR filter 130 configured within the FPGA, and the processor 200 determines the time delay (Tg) by adding a first time delay (T d1 ) generated through the low pass filter 110, a second time delay (T d2 ) generated through the low pass filter 110 and the anti-aliasing filter 120, and a third time delay (T d3 ) generated through the low pass filter 110, the anti-aliasing filter 120, and the FIR filter 130, calculates the frequency w using the position information of the rotor and the above mathematical formula, and can determine the phase compensation value θ g for the time delay compensation by multiplying the calculated frequency w by the time delay (T d ).

[0131] In the sixth embodiment, the first time delay (T d1 ) to the third time delay (T d3 ) can be determined according to the above-described manner, for example, the processor 200 can determine the cutoff frequency w n = 2πf according to the attenuation factor ζ in Table 1 and the mathematical formulas 6 and 8, determine the gain function (M 2B ) and the time delay function (ρ 2B ) of the Bessel type low pass filter 110 as mathematical formula 21 and mathematical formula 22, and can determine the cutoff frequency w nEThe gain function (M 2E ) and the time delay function (p 2E ) of the elliptic type anti-aliasing filter 120 are determined as Math. 24 and Math. 25.

[0132] Math. 21

[0133]

[0134] Math. 22

[0135]

[0136] Math. 23

[0137] ω nE = k E × 2πf c = 7.5 × 2πf c

[0138] Math. 24

[0139]

[0140] Math. 25

[0141]

[0142] In the sixth embodiment, the processor 200 can obtain the gain and the time delay in the half cut-off frequency determined using Math. 20 to 25 as shown in Table 4. In Table 5, it can be confirmed that the gain in the half cut-off frequency is -1.44 [dB], which is reduced by about 15%, and the time delay is 605.38 [uSec], which shows a difference of about 2.8%. According to the sixth embodiment, the frequency response characteristics of the device 1000 incorporating various filters are shown in FIG. 10, and it can be seen that the gain characteristics shown above 5 [kHz] are -100 [dB], which means that most of the electrical noise can be removed, and in the case where the PWM frequency is set to be above 5 [kHz], it can be seen that the influence of the PWM is almost perfectly removed. Figure 3

[0143] Table 4

[0144]

[0145] ​In one embodiment, the processor 200 calculates the delay phase angle using Equation 15 in the case of the low pass filter 110 and the anti-aliasing filter 120, and calculates the time delay of the analog filter in the case of the FIR filter 130 in compensating the time delay. In this case, the calculation time consumed in the FIR filter 130 can be shortened, thereby being efficient in terms of resource consumption of the MCU performing the calculation. In one embodiment, the processor 200 can compensate the time delay according to whether the magnitude of the gain function is 1 or less. For example, in the processor 200, if the magnitude of the gain function is 1 or less, as shown in Equation 16, the attenuation ratio of the gain function is compensated, and if the magnitude of the gain function is less than 1, a value greater than 1 is subtracted from the calculated value of the gain function, thereby compensating the attenuation ratio of the gain function, and in this case, the gain function compensator M Figure 4 . k .

[0146] Equation 16

[0147]

[0148] In one embodiment, in the processor 200, in the case where the error with respect to the time delay phase is within a preset allowable error range, the phase for time delay compensation can be determined according to a lookup table including information about the time delay. For example, as shown in Table 5, the error of the time delay phase and the half cutoff frequency is about 2.8%, and when it is within the allowable error range (e.g., 3%), the time delay T g calculated according to the sixth embodiment can be shown by a constant value based on Equation 27. The time delay T g may be used in the form of a lookup table, and when the motor or generator 10 operates at a rated frequency, the delay phase angle can be determined according to Equation 28, and the gain error can be naturally compensated by the error dynamics of the device 1000. In this case, in order to process the operation of the processor 200, even if a low-end microcontroller (MCU: Micro Controller Unit) not having a built-in floating point unit (FPU: floating point unit) is used, the calculation of the algorithm can be easily performed.

[0149] Equation 27

[0150] T g = T d1@f＝rated + T d2@f＝rated + T FIR

[0151] Equation 28

[0152] θ d = T d x ω

[0153] In an embodiment, the processor 200 can determine the 3-phase current signal passing through the components of the device 1000 as in Math. 29 according to Math. 28, and can convert the 3-phase current signal DQ into a 2-phase rotating coordinate system (Clarke Transformation) to determine as in Math. 30 according to Math. 29, and can determine a 2-phase stationary coordinate system (Park Transformation) as in Math. 31 using Math. 30.

[0154] Math. 29

[0155] i fa = sin(θ - θ d )

[0156]

[0157]

[0158] Math. 30

[0159] i α = sin(θ - θ d )

[0160] i β = -cos(θ - θ d )

[0161] Math. 31

[0162]

[0163] In an embodiment, the processor 200 can include a central processing unit (CPU) that performs a series of actions for determining the current of the motor or generator 10 and controls the entire action of the device 1000, and can be electrically connected to the filter 100 and the components thereof to control the data flow therebetween.

[0164] In an embodiment, the device 1000 can further include a driving part 300 that controls the driving of the motor or generator 10 according to the control signal of the processor 200, and the motor or generator 10 that rotates the rotor according to the supply of electricity of the driving part 300.

[0165] And, it will be understood by those of ordinary skill in the art that the embodiments described above are merely illustrative of the present application and should not be used in a limiting sense to determine the scope of the present application. Figure 10The device 1000 includes other general components in addition to the illustrated components. For example, the device 1000 can further include a current detection section that can detect a current applied to the motor or generator 10, a rotor position detection section that can detect a position of a rotor rotating in the motor or generator 10, and the like, and in another embodiment, some of the components illustrated in Figure 4 or Figure 1

[0166] Figure 1 A flowchart of a method of determining a current of the motor or generator 10 for the device 1000 of an embodiment is shown.

[0167] Referring to Figure 2 In step SllO, the device 1000 can obtain a characteristic of the filter 100 that filters noise generated in determining the current of the motor or generator 10. In an embodiment, a magnitude representing the characteristic of the filter 100 and a phase representing the characteristic of the filter 100 can be determined by an operating frequency.

[0168] In step S1120, the device 1000 can determine a time delay generated by the filter 100 based on a change in the phase representing the characteristic of the filter 100 determined by a change in the operating frequency of the motor or generator 10. In an embodiment, the device 1000 can determine the time delay by using a derivative of the operating frequency to represent a phase of a transfer function of the characteristic of the filter 100.

[0169] In step S1130, the device 1000 can determine the current of the motor or generator 10 by compensating for the time delay. In an embodiment, the device 1000 updates a current phase of the motor or generator according to a value obtained by multiplying the time delay by the operating frequency.

[0170] According to an embodiment of the present application, the device 1000 can accurately determine a time delay generated by the filter 100 according to a change in the phase representing the characteristic of the filter 100 to effectively compensate for the current of the motor or generator 10.

[0171] Figure 11 A graph of simulation results for the device 1000 of an embodiment that is improved by effectively compensating for a time delay is shown.

[0172] Referring to Figure 11 It can be confirmed that the device 1000 improves a mechanical output by about 38.7% by effectively compensating for the time delay generated by the filter 100, referring to Figures 12 to 15 improves a rotational speed by about 28.2%, referring to Figure 12 generates a torque that is increased by about 14.6% at the same current, referring to Figure 13 Figure 14 Figure 15 ​As the rotational speed increases, the degree of torque improvement increases significantly by approximately 10.8% or more. Furthermore, it provides the following effects: the device 1000 can compensate for and improve current consumption, power consumption, etc., based on time delay, maintaining constant torque until a set RPM (e.g., 12000 RPM) is achieved.

[0173] Furthermore, the above methods can be created by programs capable of running on a computer and implemented in a general-purpose digital computer running the program using a computer-readable recording medium. Moreover, the data structures used in the above methods can be recorded in a computer-readable recording medium by various means. Such computer-readable recording media include storage media such as magnetic storage media (e.g., read-only memory, random access memory, universal serial bus (USB), floppy disk, hard disk, etc.) and optical reading media (e.g., optical disc, DVD, etc.).

[0174] The foregoing description of this disclosure is for illustrative purposes only. It will be understood by those skilled in the art that variations are readily possible without altering the technical concept or essential features of this disclosure. Therefore, it should be understood that the embodiments described above are merely illustrative in all respects and are not limiting. For example, components described as a single entity can be implemented separately; similarly, components described separately can also be combined in real time.

[0175] The scope of this disclosure is shown by the appended claims, and the meaning and scope of the claims, as well as all variations or modifications derived from their equivalents, are included within the scope of this disclosure.

Claims

1. A method for determining the current of an electric motor or generator, characterized in that, comprising: obtaining a characteristic of a filter that filters noise generated in determining a current of the motor or the generator; determining a time delay generated by the filter based on a phase change of the characteristic of the filter determined by a change in an operating frequency of the motor or the generator; and determining the current of the motor or the generator by compensating for the time delay, wherein in the step of determining the time delay, the time delay is determined by using a phase of a transfer function that represents the characteristic of the filter differentiated with respect to the operating frequency, the phase of the transfer function uses the operating frequency as a variable input, in the step of determining the current of the generator, a phase of the current of the motor or the generator is updated based on a value obtained by multiplying the operating frequency by the time delay, when the transfer function (G2(s)) satisfies the following mathematical expression (1), the time delay (p2) satisfies the following mathematical expression (2): （1）， （2）， where w n is the cutoff frequency, ζ is the damping factor, and w is the operating frequency.

2. The method according to claim 1, wherein a magnitude of the characteristic of the filter and a phase of the characteristic of the filter are determined by the operating frequency.

3. The method according to claim 1, wherein the filter includes at least one of a low-pass filter, an anti-aliasing filter, and a finite impulse response filter.

4. The method according to claim 1, wherein the filter includes a low-pass filter, an anti-aliasing filter, and a finite impulse response filter, the time delay is determined by adding a first time delay generated by the low-pass filter, a second time delay generated by the anti-aliasing filter, and a third time delay generated by the finite impulse response filter.

5. An apparatus for determining the current of an electric motor or generator, characterized by comprising: a filter that filters noise generated in determining a current of the motor or the generator; and a processor that obtains a characteristic of the filter, determines a time delay generated by the filter based on a phase change of the characteristic of the filter determined by a change in an operating frequency of the motor or the generator, and determines the current of the motor or the generator by compensating for the time delay, wherein the processor determines the time delay by using a phase of a transfer function that represents the characteristic of the filter differentiated with respect to the operating frequency, the phase of the transfer function uses the operating frequency as a variable input, the processor updates a phase of the current of the motor or the generator based on a value obtained by multiplying the operating frequency by the time delay, when the transfer function (G2(s)) satisfies the following mathematical expression (1), the time delay (p2) satisfies the following mathematical expression (2): （1）， （2）， where w n is the cutoff frequency, ζ is the damping factor, and w is the operating frequency.

6. The apparatus according to claim 5, wherein a magnitude of the characteristic of the filter and a phase of the characteristic of the filter are determined by the operating frequency.

7. The apparatus according to claim 5, wherein the filter includes at least one of a low-pass filter, an anti-aliasing filter, and a finite impulse response filter. 8.The apparatus of claim 5, wherein, the filter includes a low pass filter, an anti-aliasing filter, and a finite impulse response filter, the time delay is determined by adding a first time delay generated by the low pass filter, a second time delay generated by the anti-aliasing filter, and a third time delay generated by the finite impulse response filter. 9.A computer-readable recording medium, wherein, a program for causing a computer to execute the method according to any one of claims 1 to 4 is recorded.

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