Operational amplifier, operational amplifier circuit, chip and electronic device

Abstract

The present application discloses an operational amplifier, an operational amplifier circuit, a chip and an electronic device, wherein the operational amplifier includes a differential input module, a differential output module, a first bias module and a second bias module; wherein the differential input module includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential pair, the first PMOS differential input pair is connected to the first bias module, and the second PMOS differential input pair is connected to the second bias module. The differential input module in the operational amplifier provided in the present application includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential pair, and by connecting the gate of the PMOS tube to the differential input module of the operational amplifier, it can be ensured that when a negative voltage is input, the PMOS tube of the first PMOS differential input pair of the differential input module works in a saturation region.

Description

Technical Field

[0001] The present application relates to the field of integrated circuits, and in particular to the field of operational amplifiers, operational amplifier circuits, chips, and electronic equipment. Background Art

[0002] The common method of current detection is to connect a high-precision resistor in the current path and detect the current by detecting the voltage across the resistor. However, the resistor connected in the current path must be very small, otherwise the voltage drop and power loss introduced will be unacceptable. Therefore, it is necessary to amplify the voltage across the resistor through a high-precision operational amplifier, and then perform subsequent processing after amplification to obtain the corresponding current.

[0003] When detecting current in the motor drive field, according to the application of the motor, it is necessary to detect the current of the high side (power supply measurement), low side (ground measurement) and intermediate level series resistor of the motor drive output. Therefore, the common mode input range of the op amp should support the input of the low side, high side and intermediate level. When detecting the low side, the continuous current will be generated when the driver tube is turned off, so in this case, a negative common mode input will be generated.

[0004] In the prior art, for the negative voltage input of current detection, a charge pump is used to generate a negative voltage power supply, so that when the common mode input is negative, the operational amplifier can work normally. However, the existing solution of using charge pump technology to generate negative voltage requires an additional charge pump module, which increases cost and power consumption, and also increases design complexity. Summary of the invention

[0005] The purpose of the present application is to enable the operational amplifier circuit to support low-side negative voltage input without the need for a charge pump to provide a negative voltage power supply when the operational amplifier has a low-side negative voltage input.

[0006] In order to achieve the above technical objectives, this application adopts the following technical solutions.

[0007] In a first aspect, an embodiment of the present application provides an operational amplifier, comprising: a differential input module, wherein

[0008] The differential input module is used to receive the differential signal to be amplified;

[0009] A differential output module, the differential output module is used to output the amplified differential signal;

[0010] A first bias module, wherein the first bias module is connected to the differential input module;

[0011] A second bias module, wherein the second bias module is connected to the differential input module and the differential output module respectively;

[0012] The differential input module includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential pair, the first PMOS differential input pair is connected to the first bias module, and the second PMOS differential input pair is connected to the second bias module.

[0013] According to the embodiment disclosed in the present application, the first PMOS differential input pair includes a PMOS tube MP1 and a PMOS tube MP2, and the second PMOS differential input pair includes a PMOS tube MP3 and a PMOS tube MP4; the first bias module includes a first output terminal and a second output terminal;

[0014] The gate of the PMOS tube MP1 and the gate of the PMOS tube MP3 are connected to each other to form a differential voltage receiving terminal VIN, and the gate of the PMOS tube MP2 and the gate of the PMOS tube MP4 are connected to each other to form a differential voltage receiving terminal VIP; the source of the PMOS tube MP1 is connected to the first output terminal, and the N-well potential of the PMOS tube MP1 is connected to the source of the PMOS tube MP1; the source of the PMOS tube MP2 is connected to the source of the PMOS tube MP1, the N-well potential of the PMOS tube MP2 is connected to the source of the PMOS tube MP2, and the source of the PMOS tube MP2 is connected to the second output terminal;

[0015] The drain of the PMOS tube MP3 is connected to the second bias module, and the drain of the PMOS tube MP4 is connected to the second bias module; the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP3, and the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP4.

[0016] According to the embodiments disclosed in the present application, the PMOS tube MP3 and the PMOS tube MP4 are high-voltage MOS tubes with a withstand voltage of 0V-60V; the PMOS tube MP1 and the PMOS tube MP2 are low-voltage MOS tubes with a withstand voltage of 0V-5V.

[0017] According to an embodiment disclosed in the present application, the first bias module includes a current mirror circuit.

[0018] According to the embodiment disclosed in the present application, the current mirror circuit includes: a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7 and a PMOS tube MP8; wherein the source of the PMOS tube MP6 is connected to the source of the PMOS tube MP7, and the source of the PMOS tube MP7 is connected to a power supply; the gate of the PMOS tube MP6 is connected to the gate of the PMOS tube MP7, and the gate of the PMOS tube MP7 is connected to a first bias voltage vpbp1; the gate of the PMOS tube MP8 is connected to the gate of the PMOS tube MP5, and the gate of the PMOS tube MP8 is connected to a second bias voltage vpbp2; the drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP5, the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP8, the drain of the PMOS tube MP8 serves as the first output end, and the drain of the PMOS tube MP5 serves as the second output end.

[0019] According to the embodiment disclosed in the present application, the PMOS tube MP5 and the PMOS tube MP8 are high-voltage MOS tubes with a withstand voltage of 0V-60V; the PMOS tube MP6 and the PMOS tube MP7 are low-voltage MOS tubes with a withstand voltage of 0V-5V.

[0020] According to the embodiment disclosed in the present application, the first bias module also includes a potential difference circuit, which includes an input end and an output end, the first output end is connected to the input end, the output end of the potential difference circuit is connected to the source of the PMOS tube MP1, the input end of the potential difference circuit is connected to the potential difference bias voltage vb, the N-well potential of the PMOS tube MP1 is connected to the input end, and the N-well potential of the PMOS tube MP2 is connected to the input end, so as to raise the threshold voltage of the first PMOS differential input pair.

[0021] According to the embodiment disclosed in the present application, the potential difference circuit includes: a PMOS tube MP9, a PMOS tube MP10 and a PMOS tube MP11; the source of the PMOS tube MP9 is connected to the gate of the PMOS tube MP9 as an input end, the drain of the PMOS tube MP9 is respectively connected to the source of the PMOS tube MP10 and the gate of the PMOS tube MP10, the drain of the PMOS tube MP10 is respectively connected to the source of the PMOS tube MP11 and the gate of the PMOS tube MP11, and the drain of the PMOS tube MP11 is used as the output end.

[0022] According to the embodiment disclosed in the present application, the second bias module includes a first current source Is1, a second current source Is2, a third current source Is3, a fourth current source Is4, an NMOS tube MN1, an NMOS tube MN2, an NMOS tube MN3, an NMOS tube MN4, a PMOS tube MP12 and a PMOS tube MP13;

[0023] Wherein, one end of the first current source Is1 is connected to a power supply, and the other end of the first current source Is1 is respectively connected to the drain of the NMOS tube MN1 and the source of the PMOS tube MP12; the source of the NMOS tube MN1 is connected to the drain of the PMOS tube MP12, and the drain of the PMOS tube MP12 is connected to the output stage P; the drain of the NMOS tube MN1 is connected to the source of the PMOS tube MP12, and the source of the PMOS tube MP12 is connected to the output stage P; the gate of the NMOS tube MN1 is connected to the sixth bias voltage vbn2, and the gate of the PMOS tube MP12 is connected to the third bias voltage vbp3;

[0024] One end of the second current source Is2 is connected to a power supply, and the other end of the second current source Is2 is respectively connected to the drain of the NMOS tube MN2 and the source of the PMOS tube MP13; the source of the NMOS tube MN2 is connected to the drain of the PMOS tube MP13, and the drain of the PMOS tube MP13 is connected to the output stage N; the drain of the NMOS tube MN2 is connected to the source of the PMOS tube MP13, and the source of the PMOS tube MP13 is connected to the output stage N; the gate of the NMOS tube MN2 is connected to the seventh bias voltage vbn3, and the gate of the PMOS tube MP13 is connected to the fourth bias voltage vbp4;

[0025] The source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN3, the source of the NMOS tube MN2 is connected to the drain of the NMOS tube MN4, the source of the NMOS tube MN3 is connected to the ground through the third current source Is3, the source of the NMOS tube MN4 is connected to the ground through the fourth current source Is4, the gate of the NMOS tube MN3 is connected to the fifth bias voltage vbn1, and the gate of the NMOS tube MN4 is connected to the fifth bias voltage vbn1.

[0026] In a second aspect, an embodiment of the present application further discloses an amplifier circuit, including: an operational amplifier unit;

[0027] The operational amplifier unit performs amplification processing according to the input voltage signal to be amplified, and obtains a processed voltage signal output;

[0028] The operational amplifier unit includes a first-stage operational amplifier and a second-stage operational amplifier, wherein the first-stage operational amplifier includes an operational amplifier provided by any possible implementation of the first aspect, the gain of the first-stage operational amplifier is a fixed value, and the second-stage operational amplifier adopts a variable gain.

[0029] In a third aspect, an embodiment of the present application further discloses an amplifier circuit, comprising an operational amplifier provided in any possible implementation manner of the first aspect.

[0030] In a fourth aspect, an embodiment of the present application further discloses an electronic device, comprising an operational amplifier provided by any possible implementation of the first aspect.

[0031] Beneficial technical effects achieved by this application:

[0032] The differential input module in the operational amplifier provided in the present application includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential pair. By applying the PMOS tube pair to the differential input module, it can be ensured that when a negative voltage is input, the PMOS tube of the first PMOS differential input pair of the differential input module operates in a saturation region.

[0033] The operational amplifier circuit provided in the present application can be applied to application scenarios where the low-side input is a negative voltage (such as -2V), without the need to additionally use a charge pump to generate a negative voltage power supply, thereby simplifying the circuit structure.

[0034] When high voltage is input, four high voltage tubes, namely, PMOS tube MP3, PMOS tube MP4, PMOS tube MP5 and PMOS tube MP8, are used to withstand the high voltage, so that the PMOS tube MP1 and PMOS tube MP2 of the first PMOS differential input pair do not need to withstand the high voltage, thus playing a protective role. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The drawings described herein are for explanation purposes only and are not intended to limit the scope of the present application in any way. In addition, the shapes and proportional dimensions of the components in the drawings are only for illustration purposes and are used to help understand the present application. They do not specifically limit the shapes and proportional dimensions of the components of the present application. Under the guidance of the present application, those skilled in the art can select various possible shapes and proportional dimensions to implement the present application according to specific circumstances. In the drawings:

[0036] Figure 1 A circuit schematic diagram of an operational amplifier provided in one embodiment of the present application;

[0037] Figure 2 A circuit schematic diagram of an operational amplifier provided in yet another embodiment of the present application;

[0038] Figure 3A schematic diagram of an amplifier circuit provided in an embodiment of the present application;

[0039] Figure 4 A structural block diagram of an electronic device provided in an embodiment of the present application;

[0040] Figure numerals: 100 - differential input module, 200 - first bias module, 300 - second bias module, 400 - differential output module, 500 - electronic device, 600 - operational amplifier, 2001 - current mirror circuit, 2002 - potential difference circuit, 10 - first stage operational amplifier, 20 - second stage operational amplifier. DETAILED DESCRIPTION

[0041] In order to enable those skilled in the art to better understand the technical solutions in the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work should fall within the scope of protection of this application.

[0042] The terms "first", "second", etc. are only used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. They cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated.

[0043] The common-mode input range of the op amp must support low-side, high-side, and intermediate-level inputs. When detecting current in the motor drive field, a continuous current will be generated when the driver tube is turned off, so a low-side negative common-mode input will be generated in this case. In the prior art, for the negative voltage input of current detection, a charge pump is used to generate a negative voltage power supply to ensure that the op amp can work normally when the common-mode input is negative.

[0044] In order to simplify the circuit and realize the current detection operational amplifier circuit supporting negative voltage input at the minimum cost, the present application provides an operational amplifier, including: a differential input module 100, used to receive the differential signal to be amplified; a differential output module 400, used to output the amplified differential signal; a first bias module 200, connected to the differential input module 100; a second bias module 300, respectively connected to the differential input module 100 and the differential output module 400; wherein the differential input module 100 includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential pair, the first PMOS differential input pair is connected to the first bias module 200, and the second PMOS differential input pair is connected to the second bias module 300.

[0045] The differential input module 100 includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential pair. By applying the PMOS tube pair to the differential input module 100 of the operational amplifier, it can be ensured that when a negative voltage is input, the PMOS tube of the first PMOS differential input pair of the differential input module 100 operates in a saturation region.

[0046] A specific embodiment provides an operational amplifier, which receives a differential input signal, performs amplification processing, and outputs an amplified differential output signal. Figure 1 As shown, the differential input signal to be processed is input through the differential voltage receiving terminals VIN and VIP, the differential output module 400 includes an output stage P and an output stage N, and the amplified differential signal is output through the output stage P and the output stage N.

[0047] The operational amplifier includes: a differential input module 100, for receiving a differential signal to be amplified; a differential output module 400, for outputting the amplified differential signal; a first bias module 200, connected to the differential input module 100; a second bias module 300, connected to the differential input module 100 and the differential output module 400;

[0048] The differential input module 100 includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential pair. The first PMOS differential input pair is connected to the first bias module 200 , and the second PMOS differential input pair is connected to the second bias module 300 .

[0049] Specifically, the first PMOS differential input pair includes a PMOS transistor MP1 and a PMOS transistor MP2, and the second PMOS differential input pair includes a PMOS transistor MP3 and a PMOS transistor MP4; the first bias module 200 includes a first output terminal and a second output terminal;

[0050] Among them, the gate of the PMOS tube MP1 and the gate of the PMOS tube MP3 are connected to each other to form a differential voltage receiving end VIN, and the gate of the PMOS tube MP2 and the gate of the PMOS tube MP4 are connected to each other to form a differential voltage receiving end VIP; the source of the PMOS tube MP1 is connected to the first output end, and the N-well potential of the PMOS tube MP1 is connected to the source of the PMOS tube MP1; the source of the PMOS tube MP1 and the source of the PMOS tube MP2 are connected to each other, and the N-well potential of the PMOS tube MP2 is connected to the source of the PMOS tube MP2 ( Figure 1The source of the PMOS tube MP2 is connected to the second output terminal; the drain of the PMOS tube MP3 and the drain of the PMOS tube MP4 are connected to each other and to the second bias module 300; the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP3, and the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP4.

[0051] Since the differential input module 100 uses two PMOS differential pairs, according to the working principle of PMOS, the VGS (i.e., the voltage difference between the gate G and the source S) will be turned on when it is less than the VGS value, and the VGS value is the threshold voltage or turn-on voltage required for the conductive channel, represented by Vth. Optionally, the power supply VDD can be 3.3V.

[0052] The operational amplifier circuit provided in the present application can be applied to application scenarios where the low-side input is a negative voltage (such as -2V), without the need to additionally use a charge pump to generate a negative voltage power supply, thereby simplifying the circuit structure.

[0053] like Figure 1 As shown, the first bias module 200 includes a current mirror circuit. The current mirror circuit includes: a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7 and a PMOS tube MP8, wherein the source of the PMOS tube MP6 and the source of the PMOS tube MP7 are connected to a power supply, the gate of MP6 and the gate of the PMOS tube MP7 are connected, and the gate of the PMOS tube MP7 is connected to a first bias voltage vpbp1; the gate of the PMOS tube MP8 is connected to the gate of the PMOS tube MP5, and the gate of the PMOS tube MP8 is connected to a second bias voltage vpbp2, the drain of MP6 and the source of the PMOS tube MP5 are connected, the drain of the PMOS tube MP7 and the source of the PMOS tube MP8 are connected, and the drain of the PMOS tube MP8 is connected as a first output terminal to the source of the PMOS tube MP1 in the first PMOS differential input pair; the drain of the PMOS tube MP5 is connected as a second output terminal to the source of the PMOS tube MP2 in the first PMOS differential input pair.

[0054] In this embodiment, the first bias module 200 includes a current mirror circuit, which provides a bias current in the operational amplifier to form a tail current and determine a DC bias point. The first bias voltage vpbp1 and the second bias voltage vpbp2 can make the PMOS tube MP5, PMOS tube MP6, PMOS tube MP7 and PMOS tube MP8 in a saturated state, thereby generating a bias current. When the PMOS tube MP1 and PMOS tube MP2 of the first PMOS differential input pair, and the PMOS tube MP3 and PMOS tube MP4 of the second PMOS differential input pair are in a conducting state, the bias current generated by the first bias module 200 converts the differential input voltage (the voltage between VIN and VIP) into a differential input current, and enters the second bias module 300 after passing through the first PMOS differential input pair and the second PMOS differential input pair.

[0055] Optionally, the first bias voltage vpbp1 and the second bias voltage vpbp2 are 1.8V.

[0056] In other embodiments, the operational amplifier (ie, operational amplifier) ​​is required to support both negative voltage input and high voltage input.

[0057] In CMOS technology, the matching characteristics of high-voltage tubes are very poor. It is not recommended to use high-voltage tubes directly for high-precision op amp input pairs. Therefore, based on the above embodiment, Figure 1 In the operational amplifier provided by the illustrated embodiment, the PMOS tube MP1, the PMOS tube MP2, the PMOS tube MP6 and the PMOS tube MP7 of the first PMOS differential input pair are low-voltage tubes (i.e., low-voltage MOS tubes), and the PMOS tube MP3, the PMOS tube MP4, the PMOS tube MP5 and the PMOS tube MP8 of the second PMOS differential input pair are high-voltage tubes (i.e., high-voltage MOS tubes); the PMOS tube MP6 and the PMOS tube MP7 input the high-voltage VCCH.

[0058] When the high-voltage tube (such as PMOS tube MP3 and PMOS tube MP4) is in working state, the source voltage and gate voltage of the low-voltage tube (such as PMOS tube MP1 and PMOS tube MP2) are limited, and both the high-voltage tube and the low-voltage tube work in the safe working area. Therefore, when high voltage is input, the four high-voltage tubes, namely, PMOS tube MP3, PMOS tube MP4, PMOS tube MP5 and PMOS tube MP8, are used to withstand the high voltage, so that the PMOS tube MP1 and PMOS tube MP2 of the first PMOS differential input pair do not need to withstand the high voltage, thus playing a protective role.

[0059] In order to further improve the performance of the circuit, a specific embodiment may be based on the above embodiment, wherein the first bias module 200 further includes a potential difference circuit 2002, the potential difference circuit 2002 includes an input end and an output end, the input end of the potential difference circuit 2002 is connected to the first output end of the first bias module 200, the output end of the potential difference circuit 2002 is connected to the source of the PMOS tube MP1 in the first PMOS differential input pair, the input end of the potential difference circuit 2002 is connected to the potential difference bias voltage vb, the N-well potential (also called body potential) of the PMOS tube MP1 is connected to the input end, and the N-well potential of the PMOS tube MP2 is connected to the input end, so as to raise the threshold voltage of the first PMOS differential input pair.

[0060] In some embodiments, the potential difference circuit 2002 includes a PMOS tube MP9, a PMOS tube MP10 and a PMOS tube MP11. The source of the PMOS tube MP9 is connected to the gate of the PMOS tube MP9 as an input end. In this embodiment, the input end is connected to the drain of the PMOS tube MP8, the drain of the PMOS tube MP9 is connected to the source of the PMOS tube MP10 and the gate of the PMOS tube MP10, the drain of the PMOS tube MP10 is connected to the source of the PMOS tube MP11 and the gate of the PMOS tube MP11, and the drain of the PMOS tube MP11 is used as an output end. In this embodiment, the output end is connected to the source of the PMOS tube MP1.

[0061] The PMOS tubes MP1 and MP2 of the first PMOS differential input pair are low-voltage tubes, and in the BCD process, the normal threshold voltage is generally about 0.7V. The PMOS tubes MP3 and MP4 of the second PMOS differential input pair are high-voltage tubes (i.e., high-voltage MOS tubes), and the threshold voltage is about 1V. Since the VTH of the high-voltage MOS tube is about 300mV higher than that of the low-voltage tube, if the VDS-Vov voltage (i.e., the difference between the drain-source voltage and the overdrive voltage) of the PMOS tubes MP1 and MP2 is less than 300mV, the PMOS tubes MP1 and MP2 of the first PMOS differential input pair will work in the linear region, affecting the normal operation of the operational amplifier, where Vov = VDS-Vth, and VDS is the voltage between the drain and the source. The voltage of the potential difference bias voltage Vb is 2-3 diode voltages higher than the source of the PMOS tube MP1 and the PMOS tube MP2, so that the Vth of the PMOS tube MP1 and the PMOS tube MP2 is raised by about 1V, so that the threshold voltage of the PMOS tube MP1 and the PMOS tube MP2 becomes about 1.7V, which can ensure that the input pair of tubes MP1 and MP2 of the operational amplifier always work in the saturation area, thereby ensuring the performance of the operational amplifier circuit.

[0062] It should be noted that in the present application, the withstand voltage of the high-voltage MOS tube is about 0V-60V, and the withstand voltage of the low-voltage MOS tube is about 0V-5V. The low-voltage MOS tube only needs an extremely low gate charge to meet the strong current and high power processing capabilities. In addition to the fast switching speed, it also has the characteristics of low switching loss. The reaction speed of the high-voltage MOS tube is slower than that of the low-voltage MOS tube. When used specifically, those skilled in the art can select a specific model according to needs.

[0063] Further, the second bias module 300 includes a first current source Is1, a second current source Is2, a third current source Is3, a fourth current source Is4, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, an NMOS transistor MN4, a PMOS transistor MP12, and a PMOS transistor MP13;

[0064] Among them, one end of the first current source Is1 is connected to the power supply, and the other end of the first current source Is1 is respectively connected to the drain of the NMOS tube MN1 and the source of the PMOS tube MP12; the source of the NMOS tube MN1 and the drain of the PMOS tube MP12 are connected to each other and connected to the output stage P; the drain of the NMOS tube MN1 and the source of the PMOS tube MP12 are connected to each other and connected to the output stage P; the gate of the NMOS tube MN1 is connected to the sixth bias voltage vbn2, and the gate of the PMOS tube MP12 is connected to the third bias voltage vbp3;

[0065] One end of the second current source Is2 is connected to the power supply, and the other end of the second current source Is2 is respectively connected to the drain of the NMOS tube MN2 and the source of the PMOS tube MP13; the source of the NMOS tube MN2 and the drain of the PMOS tube MP13 are connected to each other and connected to the output stage N; the drain of the NMOS tube MN2 and the source of the PMOS tube MP13 are connected to each other and connected to the output stage N; the gate of the NMOS tube MN2 is connected to the seventh bias voltage vbn3, and the gate of the PMOS tube MP13 is connected to the fourth bias voltage vbp4;

[0066] The source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN3, the electrode of the NMOS tube MN2 is connected to the drain of the NMOS tube MN4, the source of the NMOS tube MN3 is connected to the ground through the third current source Is3, the source of the NMOS tube MN4 is connected to the ground through the fourth current source Is4, and the gates of the NMOS tubes MN3 and MN4 are both connected to the fifth bias voltage vbn1.

[0067] By inputting the sixth bias voltage vbn2 into the gate of the NMOS tube MN1, the NMOS tube MN1 is driven to be turned on or off. By inputting the third bias voltage vbp3 into the gate of the PMOS tube MP12, the PMOS tube MP12 is driven to be turned on or off. By inputting the seventh bias voltage vbn3 into the gate of the NMOS tube MN2, the NMOS tube MN2 is driven to be turned on or off. By inputting the fourth bias voltage vbp4 into the gate of the PMOS tube MP13, the PMOS tube MP13 is driven to be turned on or off. In a specific embodiment, the threshold voltage of a low-voltage NMOS is generally about 0.7V; the threshold voltage of a low-voltage PMOS tube is about 0.7V.

[0068] The NMOS transistor MN1 and the PMOS transistor MP12 are adapted to be connected to the first current source Is1, the NMOS transistor MN2 and the PMOS transistor MP13 are adapted to be connected to the second current source Is2, the NMOS transistor MN3 is adapted to be connected to the third current source Is3, and the NMOS transistor MN4 is adapted to be connected to the fourth current source Is4.

[0069] The gate of the NMOS transistor MN3 and the gate of the NMOS transistor MN4 are connected to each other and to the bias voltage fifth bias voltage vbn1 , and the output impedance of the current source can be increased through the NMOS transistor MN3 and the NMOS transistor MN4 .

[0070] In addition, the present application also provides an amplifier circuit, such as Figure 3 As shown, it includes an operational amplifier unit;

[0071] The operational amplifier unit is used to amplify the input voltage signal to be amplified, and obtain a processed voltage signal output;

[0072] The operational amplifier unit includes a first-stage operational amplifier 10 and a second-stage operational amplifier 20, wherein the first-stage operational amplifier 10 includes the above operational amplifiers, the 10 gain of the first-stage operational amplifier is a fixed value, and the second-stage operational amplifier 20 adopts a variable gain.

[0073] like Figure 3 As shown, the differential input signals IN+ and IN- are respectively input to the differential input terminals of the first-stage operational amplifier 10 through resistors R1 and R2, and the output terminals of the first-stage operational amplifier 10 feed back the output signals to the differential input terminals through resistors R3 and R4, respectively. The differential output terminals of the first-stage operational amplifier 10 are respectively input to the positive input terminal and the negative input terminal of the second-stage operational amplifier 20 through resistors R5 and R6, and the positive input terminal of the second-stage operational amplifier 20 is connected to the reference voltage REF through resistor R7; and the negative input terminal of the second-stage operational amplifier 20 is connected to the output terminal through resistor R8.

[0074] Among them, resistor R7 and resistor R8 are gain adjustment resistors, the gain of the first stage operational amplifier 10 is set to 2, and the gain of the second stage operational amplifier 20 is adjustable (N) and can be adjusted according to actual needs. Figure 3 The gain ratio is adjusted on the frame structure shown, and the output common-mode voltage of the first-stage operational amplifier 10 is made positive, so that the voltage seen at the input end of the second-stage operational amplifier 20 is the divided voltage of the input voltage and the output common-mode voltage of the first-stage operational amplifier 10, so that the negative voltage seen at the input end of the second-stage operational amplifier 20 is higher than the actual input IN+ and IN- voltages.

[0075] The operational amplifier and the amplifying circuit provided in the above embodiments can be used in a current detection circuit, such as a first input terminal of the operational amplifier or the amplifying circuit is connected to a first terminal of a sampling resistor, a second input terminal of the operational amplifier or the amplifying circuit is connected to a second terminal of the sampling resistor, and an output terminal of the operational amplifier and the amplifying circuit is connected to a sampling terminal of a control chip in the system, so as to obtain a current sampling signal.

[0076] The operational amplifier and amplifier circuit provided in the present application can achieve process compatibility in ordinary CMOS processes, have a small area and low cost, and can input a negative voltage on the low side.

[0077] After improvement, the operational amplifier and amplification circuit provided in the present application can input negative voltage at the low side and can also support high voltage common mode input.

[0078] The embodiment of the present disclosure also provides a chip, which includes the above operational amplifier.

[0079] like Figure 4 As shown, the embodiment of the present disclosure further provides an electronic device 500, and the electronic device 500 includes an operational amplifier 600 provided by the embodiment of the present disclosure.

[0080] It should be understood that the above description is for illustration and not for limitation. Many embodiments and many applications beyond the examples provided will be apparent to those skilled in the art upon reading the above description. Therefore, the scope of the present teachings should not be determined with reference to the above description, but rather with reference to the foregoing claims and the full scope of equivalents to which such claims are entitled. For the purpose of comprehensiveness, all articles and references, including disclosures of patent applications and publications, are incorporated herein by reference. The omission of any aspect of the subject matter disclosed herein in the foregoing claims is not intended to be a waiver of such subject matter, nor should it be considered that the applicant has not considered such subject matter to be part of the disclosed application subject matter.

Claims

1. An operational amplifier, characterized in that: include: A differential input module 100, the differential input module is used to receive a differential signal to be amplified; A differential output module 400, the differential output module is used to output the amplified differential signal; A first bias module 200, wherein the first bias module is connected to the differential input module; A second bias module 300, the second bias module is connected to the differential input module and the differential output module respectively; Wherein, the differential input module includes a first PMOS differential input pair and a second PMOS differential input pair connected to the first PMOS differential input pair, the first PMOS differential input pair is connected to the first bias module, and the second PMOS differential input pair is connected to the second bias module; The first PMOS differential input pair includes a PMOS tube MP1 and a PMOS tube MP2, and the second PMOS differential input pair includes a PMOS tube MP3 and a PMOS tube MP4; the first bias module includes a first output end and a second output end; wherein the PMOS tube MP1 and the PMOS tube MP2 are low-voltage tubes, and the PMOS tube MP3 and the PMOS tube MP4 are high-voltage tubes; The gate of the PMOS tube MP1 is connected to the gate of the PMOS tube MP3 to form a differential voltage receiving terminal VIN, and the gate of the PMOS tube MP2 is connected to the gate of the PMOS tube MP4 to form a differential voltage receiving terminal VIP; the source of the PMOS tube MP2 is connected to the source of the PMOS tube MP1, and the source of the PMOS tube MP2 is connected to the second output terminal; The drain of the PMOS tube MP3 is connected to the second bias module, and the drain of the PMOS tube MP4 is connected to the second bias module; the drain of the PMOS tube MP1 is connected to the source of the PMOS tube MP3, and the drain of the PMOS tube MP2 is connected to the source of the PMOS tube MP4; The first bias module includes a current mirror circuit, and the current mirror circuit includes: a PMOS tube MP5, a PMOS tube MP6, a PMOS tube MP7 and a PMOS tube MP8; The source of the PMOS tube MP6 is connected to the source of the PMOS tube MP7, the source of the PMOS tube MP7 is connected to a power supply, the gate of the PMOS tube MP6 is connected to the gate of the PMOS tube MP7, and the gate of the PMOS tube MP7 is connected to a first bias voltage vpbp1; The gate of the PMOS tube MP8 is connected to the gate of the PMOS tube MP5, and the gate of the PMOS tube MP8 is connected to the second bias voltage vpbp2; The drain of the PMOS tube MP6 is connected to the source of the PMOS tube MP5, and the drain of the PMOS tube MP7 is connected to the source of the PMOS tube MP8; the drain of the PMOS tube MP8 serves as the first output terminal, and the drain of the PMOS tube MP5 serves as the second output terminal; The first bias module further includes a potential difference circuit, the potential difference circuit includes an input end and an output end, the first output end is connected to the input end, the output end is connected to the source of the PMOS tube MP1, and the input end is connected to a potential difference bias voltage vb; the N-well potential of the PMOS tube MP1 is connected to the input end, and the N-well potential of the PMOS tube MP2 is connected to the input end, so as to raise the threshold voltage of the first PMOS differential input pair; The potential difference circuit includes a PMOS tube MP9, a PMOS tube MP10 and a PMOS tube MP11. The source of the PMOS tube MP9 is connected to the gate of the PMOS tube MP9 and serves as the input end. The drain of the PMOS tube MP9 is respectively connected to the source of the PMOS tube MP10 and the gate of the PMOS tube MP10. The drain of the PMOS tube MP10 is respectively connected to the source of the PMOS tube MP11 and the gate of the PMOS tube MP11. The drain of the PMOS tube MP11 serves as the output end.

2. An operational amplifier according to claim 1, characterized in that: The withstand voltage range of the PMOS tube MP3 and the PMOS tube MP4 is 0V-60V, and the withstand voltage range of the PMOS tube MP1 and the PMOS tube MP2 is 0V-5V.

3. An operational amplifier according to claim 1, characterized in that: The withstand voltage range of the PMOS tube MP5 and the PMOS tube MP8 is 0V-60V, and the withstand voltage range of the PMOS tube MP6 and the PMOS tube MP7 is 0V-5V.

4. The operational amplifier according to claim 1, characterized in that: The second bias module includes a first current source Is1, a second current source Is2, a third current source Is3, a fourth current source Is4, an NMOS transistor MN1, an NMOS transistor MN2, an NMOS transistor MN3, an NMOS transistor MN4, a PMOS transistor MP12, and a PMOS transistor MP13; One end of the first current source Is1 is connected to a power supply, and the other end of the first current source Is1 is respectively connected to the drain of the NMOS tube MN1 and the source of the PMOS tube MP12; the source of the NMOS tube MN1 is connected to the drain of the PMOS tube MP12, the drain of the PMOS tube MP12 is connected to the output stage P; the source of the PMOS tube MP12 is connected to the output stage P; The gate of the NMOS transistor MN1 is connected to the sixth bias voltage vbn2, and the gate of the PMOS transistor MP12 is connected to the third bias voltage vbp3; One end of the second current source Is2 is connected to a power supply, and the other end of the second current source Is2 is respectively connected to the drain of the NMOS tube MN2 and the source of the PMOS tube MP13; the source of the NMOS tube MN2 is connected to the drain of the PMOS tube MP13, the drain of the PMOS tube MP13 is connected to the output stage N; the source of the PMOS tube MP13 is connected to the output stage N; The gate of the NMOS transistor MN2 is connected to the seventh bias voltage vbn3, and the gate of the PMOS transistor MP13 is connected to the fourth bias voltage vbp4; The source of the NMOS tube MN1 is connected to the drain of the NMOS tube MN3, and the source of the NMOS tube MN2 is connected to the drain of the NMOS tube MN4; the source of the NMOS tube MN3 is connected to the ground through the third current source Is3, and the source of the NMOS tube MN4 is connected to the ground through the fourth current source Is4, the gate of the NMOS tube MN3 is connected to the fifth bias voltage vbn1, and the gate of the NMOS tube MN4 is connected to the fifth bias voltage vbn1.

5. An amplifier circuit, characterized in that: include: Operational amplifier unit; The operational amplifier unit performs amplification processing according to the input voltage signal to be amplified to obtain a processed voltage signal; The operational amplifier unit includes a first-stage operational amplifier and a second-stage operational amplifier, the first-stage operational amplifier includes the operational amplifier according to any one of claims 1 to 4, the gain of the first-stage operational amplifier is a fixed value, and the second-stage operational amplifier adopts a variable gain.

6. A chip, characterized in that: The invention comprises an operational amplifier as claimed in any one of claims 1 to 4.

7. An electronic device, characterized in that: The invention comprises an operational amplifier as claimed in any one of claims 1 to 4.

Images