A method, device, equipment and medium for FPGA prototype verification platform transplantation

Abstract

The application provides a FPGA prototype verification platform transplantation method, device and equipment and readable medium, the method comprises the following steps: importing the engineering file of ASIC design into the engineering of FPGA prototype environment; identifying each phase-locked loop library module in the ASIC design, and analyzing the related parameters of the phase-locked loop, and generating the phase-locked loop IP module of the FPGA prototype verification platform based on the analyzed parameters; identifying each memory library module in the ASIC design, and analyzing the related parameters of the memory module, and generating the memory IP module of the FPGA prototype verification platform based on the analyzed parameters; generating the bidirectional IO port control logic module in the FPGA prototype verification platform based on the IO PAD library module in the ASIC design, and synchronizing the information of the pin in the ASIC design to the FPGA prototype verification platform. Through the use of the scheme of the application, the work efficiency of the ASIC design to the FPGA prototype transplantation can be improved, and the rework and repeated work caused by mistakes can be reduced.

Description

Technical Field

[0001] This invention relates to the field of computers, and more specifically to a method, apparatus, device, and readable medium for porting an FPGA prototype verification platform. Background Technology

[0002] FPGA (Field-Programmable Gate Array) prototyping is essential in ASIC (Application-Specific Integrated Circuit) design and verification. Before the ASIC is manufactured, significant effort is spent verifying the design code; additionally, software development needs to begin before the ASIC is delivered. Both of these tasks require FPGA prototyping to provide a verification platform, simulating ASIC behavior and helping hardware and software developers improve their work efficiency.

[0003] Compared to front-end simulation, hardware simulation, or accelerator simulation, FPGA prototyping (an ASIC verification method based on FPGA) has the following advantages:

[0004] 1. FPGAs operate at speeds closer to real ASIC chips, enabling software developers to work on underlying software development and strongly supporting chip-level system development that moves software development and system verification forward.

[0005] 2. In addition to allowing for software development in advance, FPGA prototypes can quickly build a hardware verification environment in terms of time cost.

[0006] 3. FPGA prototypes can be easily connected to real interface peripherals, such as UART, I2C, QSPI Flash, and JTAG peripherals commonly used in ASICs, facilitating functional testing and verification before tape-out.

[0007] Of course, FPGA prototypes, as verification platforms before ASIC tape-out, also have many limitations, such as size limitations, speed limitations, power consumption limitations, and structural limitations. ASICs and FPGAs have different physical structures; ASICs are based on standard cell libraries, while FPGAs are based on manufacturer-provided macrocell modules (lookup tables and flip-flops). This means that for FPGA prototype verification, ASIC code must be converted to be ported to the FPGA. This conversion is only at the code level; it replaces parts of the ASIC code with methods that can be implemented on the FPGA, without changing the original functionality. Traditionally, replacing process libraries in ASIC designs requires FPGA prototype engineers to manually modify and replace them according to the process library settings. This manual replacement work is labor-intensive, time-consuming, and requires engineers with extensive engineering experience to complete. Summary of the Invention

[0008] In view of this, the purpose of this invention is to provide a method, apparatus, device and readable medium for porting FPGA prototype verification platform. By using the technical solution of this invention, the efficiency of porting ASIC design to FPGA prototype can be improved, and rework and repeated work caused by errors can be reduced.

[0009] To achieve the above objectives, one aspect of the present invention provides a method for porting an FPGA prototype verification platform, comprising the following steps:

[0010] Import the ASIC design project files into the FPGA prototyping environment project;

[0011] Identify each phase-locked loop (PLL) technology library module in the ASIC design, analyze the relevant parameters of the PLL, and generate the PLL IP module for the FPGA prototype verification platform based on the analyzed parameters;

[0012] Identify each memory technology library module in the ASIC design, analyze the relevant parameters of the memory module, and generate the memory IP module of the FPGA prototype verification platform based on the analyzed parameters.

[0013] The bidirectional I / O port control logic module in the FPGA prototyping platform is generated based on the IO PAD process library module in the ASIC design, and the pin information in the ASIC design is synchronized to the FPGA prototyping platform.

[0014] According to one embodiment of the present invention, identifying each phase-locked loop (PLL) process library module in an ASIC design and analyzing the relevant parameters of the PLL includes:

[0015] Identify each phase-locked loop (PLL) technology library module in the ASIC design and analyze the proportional relationship between the input clock frequency, the number of output clock channels, the output clock frequency, and the frequency of each output channel for each PLL.

[0016] According to one embodiment of the present invention, the phase-locked loop IP module for generating an FPGA prototype verification platform based on analyzed parameters includes:

[0017] The highest output frequency of the phase-locked loop in the ASIC design is mapped to the highest frequency expected to be achieved in the FPGA prototyping platform.

[0018] Each output clock of each phase-locked loop identified in the ASIC design is downscaled proportionally in the FPGA prototyping platform to ensure that the frequency ratio of each output clock is the same as the original output clock ratio of the phase-locked loop in the ASIC design.

[0019] The phase-locked loop IP module of the FPGA prototype verification platform is generated according to the output frequency ratio.

[0020] According to one embodiment of the present invention, identifying each memory technology library module in an ASIC design and analyzing the relevant parameters of the memory module includes:

[0021] Identify each memory technology library module in the ASIC design and analyze the memory module's input / output clock, input / output data signal bit width, input / output address signal bit width, and memory depth parameters.

[0022] According to one embodiment of the present invention, the memory IP module of the FPGA prototyping platform generated based on analyzed parameters includes:

[0023] The analyzed memory resource overhead is summarized and compared with the available block memory resources in the FPGA prototyping platform;

[0024] Since the resource overhead does not exceed the available block memory resources within the FPGA prototyping platform, the memory IP module of the FPGA prototyping platform is generated using the block memory resources.

[0025] In response to resource overhead exceeding the available block memory resources within the FPGA prototyping platform, the excess memory resource overhead is used to generate the memory IP module of the FPGA prototyping platform using distributed memory resources.

[0026] According to one embodiment of the present invention, generating a bidirectional I / O port control logic module within an FPGA prototyping platform based on the I / O PAD process library module in the ASIC design, and synchronizing pin information from the ASIC design to the FPGA prototyping platform includes:

[0027] Identify the IO PAD process library modules in the ASIC design, and generate bidirectional IO port control logic modules in the FPGA prototyping platform based on the identified modules;

[0028] Based on the definition of each pin signal input / output / bidirectional in the ASIC design, the direction information of the pin signal is synchronized to the top-level module of the FPGA prototype verification platform.

[0029] According to one embodiment of the present invention, it further includes:

[0030] The generated phase-locked loop IP module, memory IP module, and bidirectional I / O port control logic module are checked to ensure there are no syntax errors.

[0031] Another aspect of the present invention provides an apparatus for porting an FPGA prototyping platform, the apparatus comprising:

[0032] The import module is configured to import ASIC design project files into the FPGA prototyping environment project.

[0033] The identification module is configured to identify each phase-locked loop (PLL) technology library module in the ASIC design, analyze the relevant parameters of the PLL, and generate the PLL IP module of the FPGA prototype verification platform based on the analyzed parameters.

[0034] The analysis module is configured to identify each memory technology library module in the ASIC design, analyze the relevant parameters of the memory module, and generate the memory IP module of the FPGA prototype verification platform based on the analyzed parameters.

[0035] The synchronization module is configured to generate a bidirectional I / O port control logic module within the FPGA prototyping platform based on the I / O PAD process library module in the ASIC design, and to synchronize the pin information in the ASIC design to the FPGA prototyping platform.

[0036] Another aspect of the embodiments of the present invention also provides a computer device, the computer device comprising:

[0037] At least one processor; and

[0038] The memory stores computer instructions that can be executed by a processor, which, when executed by the processor, implement the steps of any of the methods described above.

[0039] In another aspect, embodiments of the present invention also provide a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of any of the above methods.

[0040] The present invention has the following beneficial technical effects: The FPGA prototype verification platform porting method provided in the embodiments of the present invention imports the ASIC design project file into the FPGA prototype environment project; identifies each phase-locked loop (PLL) process library module in the ASIC design, analyzes the relevant parameters of the PLL, and generates the PLL IP module of the FPGA prototype verification platform based on the analyzed parameters; identifies each memory process library module in the ASIC design, analyzes the relevant parameters of the memory module, and generates the memory IP module of the FPGA prototype verification platform based on the analyzed parameters; generates a bidirectional I / O port control logic module in the FPGA prototype verification platform based on the IOPAD process library module in the ASIC design, and synchronizes the pin information in the ASIC design to the FPGA prototype verification platform. This technical solution can improve the efficiency of ASIC design to FPGA prototype porting and reduce rework and duplicate work caused by errors. Attached Figure Description

[0041] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other embodiments can be obtained based on these drawings without creative effort.

[0042] Figure 1 This is a schematic flowchart illustrating a method for porting an FPGA prototyping verification platform according to an embodiment of the present invention.

[0043] Figure 2 A schematic diagram of an apparatus for porting an FPGA prototyping verification platform according to an embodiment of the present invention;

[0044] Figure 3 This is a schematic diagram of a computer device according to an embodiment of the present invention;

[0045] Figure 4 This is a schematic diagram of a computer-readable storage medium according to an embodiment of the present invention. Detailed Implementation

[0046] To make the objectives, technical solutions, and advantages of the present invention clearer, the embodiments of the present invention will be further described in detail below with reference to specific examples and the accompanying drawings.

[0047] Based on the above objectives, a first aspect of the embodiments of the present invention provides an embodiment of a method for porting an FPGA prototype verification platform. Figure 1 The diagram shown is a schematic flowchart of the method.

[0048] like Figure 1 As shown, the method may include the following steps:

[0049] S1 imports the ASIC design project files into the FPGA prototyping environment project.

[0050] S2 identifies each PLL (Phase-Locked Loop) technology library module in the ASIC design, analyzes the relevant parameters of the PLL, and generates a PLL IP module for the FPGA prototyping platform based on the analyzed parameters. Through an intelligent generation engine, it identifies each PLL technology library module in the ASIC design, analyzes the PLL's input clock frequency, number of output clock paths, output clock frequency, and the proportional relationship between each output clock frequency for each module. It maps the highest output frequency of the PLL in the ASIC design to the highest frequency expected to be achieved in the FPGA prototype. Each output clock of each PLL identified in the ASIC design is proportionally down-clocked in the FPGA prototype to ensure that the frequency ratio of each output clock is the same as the original PLL output clock ratio in the ASIC design. Then, according to this output frequency ratio, a synthesizable PLL IP module is generated within the FPGA.

[0051] S3 identifies each memory technology library module in the ASIC design, analyzes its relevant parameters, and generates memory IP modules for an FPGA prototyping platform based on these parameters. The intelligent generation engine identifies each memory technology library module in the ASIC design and analyzes its input / output clock, input / output data signal width, input / output address signal width, and memory depth parameters for each module. The analyzed memory resource overhead is summarized and compared with the available block memory resources within the FPGA prototype. If the resource overhead does not exceed the available block memory resources, the synthesizable memory IP module for the FPGA prototype is generated directly using the block memory resources. If the resource overhead exceeds the available block memory resources, the excess memory resource overhead is used to generate a synthesizable memory IP module for the FPGA prototype using distributed memory resources.

[0052] S4 generates bidirectional I / O port control logic modules within the FPGA prototyping platform based on the I / O PAD technology library modules in the ASIC design, and synchronizes pin information from the ASIC design to the FPGA prototyping platform. The intelligent generation engine identifies the I / O PAD technology library modules in the ASIC design and generates synthesizable bidirectional I / O port control logic modules within the FPGA. Based on the input / output / bidirectional definitions of each pin signal in the ASIC design, the direction information of the pin signals is automatically synchronized to the top-level module of the FPGA prototype.

[0053] By using the technical solution of the present invention, the efficiency of porting ASIC designs to FPGA prototypes can be improved, and rework and duplicate work caused by errors can be reduced.

[0054] In a preferred embodiment of the present invention, identifying each phase-locked loop (PLL) process library module in the ASIC design and analyzing the relevant parameters of the PLL includes:

[0055] Identify each phase-locked loop (PLL) technology library module in the ASIC design and analyze the proportional relationship between the input clock frequency, the number of output clock channels, the output clock frequency, and the frequency of each output channel for each PLL.

[0056] In a preferred embodiment of the present invention, the phase-locked loop IP module for generating an FPGA prototype verification platform based on analyzed parameters includes:

[0057] The highest output frequency of the phase-locked loop in the ASIC design is mapped to the highest frequency expected to be achieved in the FPGA prototyping platform.

[0058] Each output clock of each phase-locked loop identified in the ASIC design is downscaled proportionally in the FPGA prototyping platform to ensure that the frequency ratio of each output clock is the same as the original output clock ratio of the phase-locked loop in the ASIC design.

[0059] The phase-locked loop IP module of the FPGA prototype verification platform is generated according to the output frequency ratio.

[0060] In a preferred embodiment of the present invention, identifying each memory technology library module in the ASIC design and analyzing the relevant parameters of the memory module includes:

[0061] Identify each memory technology library module in the ASIC design and analyze the memory module's input / output clock, input / output data signal bit width, input / output address signal bit width, and memory depth parameters.

[0062] In a preferred embodiment of the present invention, the memory IP module of the FPGA prototype verification platform generated based on the analyzed parameters includes:

[0063] The analyzed memory resource overhead is summarized and compared with the available block memory resources in the FPGA prototyping platform;

[0064] Since the resource overhead does not exceed the available block memory resources within the FPGA prototyping platform, the memory IP module of the FPGA prototyping platform is generated using the block memory resources.

[0065] In response to resource overhead exceeding the available block memory resources within the FPGA prototyping platform, the excess memory resource overhead is used to generate the memory IP module of the FPGA prototyping platform using distributed memory resources. Resource overhead can be obtained from analyzed parameters, and the memory IP module of the FPGA prototyping platform is generated based on the relationship between resource overhead and the size of the available block memory within the FPGA prototyping platform.

[0066] In a preferred embodiment of the present invention, generating a bidirectional I / O port control logic module within the FPGA prototyping platform based on the I / O PAD process library module in the ASIC design, and synchronizing pin information from the ASIC design to the FPGA prototyping platform includes:

[0067] Identify the IO PAD process library modules in the ASIC design, and generate bidirectional IO port control logic modules in the FPGA prototyping platform based on the identified modules;

[0068] Based on the definition of each pin signal input / output / bidirectional in the ASIC design, the direction information of the pin signal is synchronized to the top-level module of the FPGA prototype verification platform.

[0069] In a preferred embodiment of the present invention, it further includes:

[0070] The generated phase-locked loop IP module, memory IP module, and bidirectional I / O port control logic module are checked to ensure there are no syntax errors.

[0071] This invention provides a method for proactively identifying phase-locked loop (PLL), memory, and IOPAD technology library modules in ASIC designs, analyzing their internal configuration parameters, and automatically converting them into synthesizable IP modules and logic design modules for the FPGA prototype based on the actual hardware environment. This method offers the following benefits:

[0072] The traditional method of manually replacing and modifying the PLL, memory, and IOPAD technology library modules in ASIC designs has been optimized to actively identify these modules, analyze their internal configuration parameters, and automatically convert them into synthesizable IP modules and logic design modules for the FPGA prototype based on the actual hardware environment. This improves the efficiency of porting ASIC designs to FPGA prototypes and reduces rework and duplication caused by errors.

[0073] It should be noted that those skilled in the art will understand that all or part of the processes in the above embodiments can be implemented by a computer program instructing related hardware. The program can be stored in a computer-readable storage medium, and when executed, it can include the processes of the embodiments of the above methods. The storage medium can be a magnetic disk, optical disk, read-only memory (ROM), or random access memory (RAM), etc. The embodiments of the computer program described above can achieve the same or similar effects as any of the corresponding foregoing method embodiments.

[0074] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a CPU, which may be stored in a computer-readable storage medium. When the computer program is executed by the CPU, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0075] Based on the above objectives, a second aspect of the embodiments of the present invention provides an apparatus for porting an FPGA prototype verification platform, such as... Figure 2 As shown, the device 200 includes:

[0076] The import module is configured to import ASIC design project files into the FPGA prototyping environment project.

[0077] The identification module is configured to identify each phase-locked loop (PLL) technology library module in the ASIC design, analyze the relevant parameters of the PLL, and generate the PLL IP module of the FPGA prototype verification platform based on the analyzed parameters.

[0078] The analysis module is configured to identify each memory technology library module in the ASIC design, analyze the relevant parameters of the memory module, and generate the memory IP module of the FPGA prototype verification platform based on the analyzed parameters.

[0079] The synchronization module is configured to generate a bidirectional I / O port control logic module within the FPGA prototyping platform based on the I / O PAD process library module in the ASIC design, and to synchronize the pin information in the ASIC design to the FPGA prototyping platform.

[0080] In view of the above objectives, a third aspect of the present invention provides a computer device. Figure 3 The diagram shown is a schematic representation of an embodiment of the computer device provided by the present invention. Figure 3As shown, embodiments of the present invention include the following apparatus: at least one processor 21; and a memory 22 storing computer instructions 23 executable on the processor, which, when executed by the processor, implement the following method:

[0081] Import the ASIC design project files into the FPGA prototyping environment project;

[0082] Identify each phase-locked loop (PLL) technology library module in the ASIC design, analyze the relevant parameters of the PLL, and generate the PLL IP module for the FPGA prototype verification platform based on the analyzed parameters;

[0083] Identify each memory technology library module in the ASIC design, analyze the relevant parameters of the memory module, and generate the memory IP module of the FPGA prototype verification platform based on the analyzed parameters.

[0084] The bidirectional I / O port control logic module in the FPGA prototyping platform is generated based on the IO PAD process library module in the ASIC design, and the pin information in the ASIC design is synchronized to the FPGA prototyping platform.

[0085] In a preferred embodiment of the present invention, identifying each phase-locked loop (PLL) process library module in the ASIC design and analyzing the relevant parameters of the PLL includes:

[0086] Identify each phase-locked loop (PLL) technology library module in the ASIC design and analyze the proportional relationship between the input clock frequency, the number of output clock channels, the output clock frequency, and the frequency of each output channel for each PLL.

[0087] In a preferred embodiment of the present invention, the phase-locked loop IP module for generating an FPGA prototype verification platform based on analyzed parameters includes:

[0088] The highest output frequency of the phase-locked loop in the ASIC design is mapped to the highest frequency expected to be achieved in the FPGA prototyping platform.

[0089] Each output clock of each phase-locked loop identified in the ASIC design is downscaled proportionally in the FPGA prototyping platform to ensure that the frequency ratio of each output clock is the same as the original output clock ratio of the phase-locked loop in the ASIC design.

[0090] The phase-locked loop IP module of the FPGA prototype verification platform is generated according to the output frequency ratio.

[0091] In a preferred embodiment of the present invention, identifying each memory technology library module in the ASIC design and analyzing the relevant parameters of the memory module includes:

[0092] Identify each memory technology library module in the ASIC design and analyze the memory module's input / output clock, input / output data signal bit width, input / output address signal bit width, and memory depth parameters.

[0093] In a preferred embodiment of the present invention, the memory IP module of the FPGA prototype verification platform generated based on the analyzed parameters includes:

[0094] The analyzed memory resource overhead is summarized and compared with the available block memory resources in the FPGA prototyping platform;

[0095] Since the resource overhead does not exceed the available block memory resources within the FPGA prototyping platform, the memory IP module of the FPGA prototyping platform is generated using the block memory resources.

[0096] In response to resource overhead exceeding the available block memory resources within the FPGA prototyping platform, the excess memory resource overhead is used to generate the memory IP module of the FPGA prototyping platform using distributed memory resources.

[0097] In a preferred embodiment of the present invention, generating a bidirectional I / O port control logic module within the FPGA prototyping platform based on the I / O PAD process library module in the ASIC design, and synchronizing pin information from the ASIC design to the FPGA prototyping platform includes:

[0098] Identify the IO PAD process library modules in the ASIC design, and generate bidirectional IO port control logic modules in the FPGA prototyping platform based on the identified modules;

[0099] Based on the definition of each pin signal input / output / bidirectional in the ASIC design, the direction information of the pin signal is synchronized to the top-level module of the FPGA prototype verification platform.

[0100] In a preferred embodiment of the present invention, it further includes:

[0101] The generated phase-locked loop IP module, memory IP module, and bidirectional I / O port control logic module are checked to ensure there are no syntax errors.

[0102] In view of the above objectives, a fourth aspect of the present invention provides a computer-readable storage medium. Figure 4 The diagram shown is a schematic representation of an embodiment of the computer-readable storage medium provided by the present invention. Figure 4 As shown, the computer-readable storage medium 31 stores a computer program 32 that, when executed by a processor, performs the methods described above.

[0103] Furthermore, the method disclosed in the embodiments of the present invention can also be implemented as a computer program executed by a processor, which may be stored in a computer-readable storage medium. When the computer program is executed by the processor, it performs the functions defined in the method disclosed in the embodiments of the present invention.

[0104] Furthermore, the above-described method steps and system units can also be implemented using a controller and a computer-readable storage medium for storing a computer program that enables the controller to perform the functions of the above-described steps or units.

[0105] Those skilled in the art will also understand that the various exemplary logic blocks, modules, circuits, and algorithm steps described in conjunction with the disclosure herein can be implemented as electronic hardware, computer software, or a combination of both. To clearly illustrate this interchangeability between hardware and software, the functionality of various illustrative components, blocks, modules, circuits, and steps has been generally described. Whether this functionality is implemented as software or as hardware depends on the specific application and the design constraints imposed on the system as a whole. Those skilled in the art can implement the functionality in various ways for each specific application, but such implementation decisions should not be construed as departing from the scope of the embodiments disclosed herein.

[0106] In one or more exemplary designs, functionality may be implemented in hardware, software, firmware, or any combination thereof. If implemented in software, functionality may be stored as one or more instructions or code on or transmitted via a computer-readable medium. Computer-readable media include computer storage media and communication media, including any medium that facilitates the transfer of a computer program from one location to another. Storage media may be any available medium accessible to a general-purpose or special-purpose computer. By way of example, and not limitation, computer-readable media may include RAM, ROM, EEPROM, CD-ROM or other optical disc storage devices, disk storage devices or other magnetic storage devices, or any other medium that may be used to carry or store the required program code in the form of instructions or data structures and is accessible to a general-purpose or special-purpose computer or a general-purpose or special-purpose processor. Furthermore, any connection may be appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technologies such as infrared, radio, and microwave, then the aforementioned coaxial cable, fiber optic cable, twisted pair, DSL, or wireless technologies such as infrared, radio, and microwave are all included in the definition of media. As used herein, disks and optical discs include compact discs (CDs), laser discs, optical discs, digital multifunction discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above should also be included within the scope of computer-readable media.

[0107] The above are exemplary embodiments disclosed in this invention. However, it should be noted that various changes and modifications can be made without departing from the scope of the embodiments of this invention as defined by the claims. The functions, steps, and / or actions of the methods according to the disclosed embodiments described herein do not need to be performed in any particular order. Furthermore, although the elements disclosed in the embodiments of this invention may be described or claimed individually, they may be understood as multiple unless explicitly limited to a singular number.

[0108] It should be understood that, as used herein, the singular form “a” is intended to include the plural form as well, unless the context clearly supports an exception. It should also be understood that, as used herein, “and / or” refers to any and all possible combinations of one or more of the associated listed items.

[0109] The embodiment numbers disclosed in the above embodiments of the present invention are for descriptive purposes only and do not represent the superiority or inferiority of the embodiments.

[0110] Those skilled in the art will understand that all or part of the steps of the above embodiments can be implemented by hardware or by a program instructing related hardware. The program can be stored in a computer-readable storage medium, such as a read-only memory, a disk, or an optical disk.

[0111] Those skilled in the art should understand that the discussion of any of the above embodiments is merely exemplary and is not intended to imply that the scope of the invention (including the claims) is limited to these examples. Within the framework of the invention, technical features of the above embodiments or different embodiments can be combined, and many other variations of different aspects of the invention exist, which are not provided in the details for the sake of brevity. Therefore, any omissions, modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the invention should be included within the protection scope of the invention.

Claims

1. A method for porting an FPGA prototype verification platform, characterized in that, Includes the following steps: Import the ASIC design project files into the FPGA prototyping environment project; Identify each phase-locked loop (PLL) technology library module in the ASIC design, analyze the relevant parameters of the PLL, and generate the PLL IP module for the FPGA prototype verification platform based on the analyzed parameters; Identify each memory technology library module in the ASIC design, analyze the relevant parameters of the memory module, and generate the memory IP module of the FPGA prototype verification platform based on the analyzed parameters. The bidirectional I / O port control logic module in the FPGA prototype verification platform is generated based on the IO PAD process library module in the ASIC design, and the pin information in the ASIC design is synchronized to the FPGA prototype verification platform. The generation of the phase-locked loop (PLL) IP module for the FPGA prototyping platform based on the analyzed parameters includes: mapping the highest output frequency of the PLL in the ASIC design to the highest frequency expected to be achieved in the FPGA prototyping platform; performing proportional frequency reduction processing on each output clock of each PLL identified in the ASIC design in the FPGA prototyping platform to ensure that the frequency ratio of each output clock is the same as the original PLL output clock ratio in the ASIC design; and generating the PLL IP module for the FPGA prototyping platform according to the output frequency ratio. The process of generating a memory IP module for an FPGA prototyping platform based on analyzed parameters includes: summarizing the analyzed memory resource overhead and comparing the resource overhead with the available block memory resources within the FPGA prototyping platform; generating a memory IP module for the FPGA prototyping platform using the block memory resources if the resource overhead does not exceed the available block memory resources within the FPGA prototyping platform; and generating a memory IP module for the FPGA prototyping platform using distributed memory resources if the resource overhead exceeds the available block memory resources within the FPGA prototyping platform. The process of generating a bidirectional I / O port control logic module within an FPGA prototyping platform based on the I / O PAD technology library module in the ASIC design and synchronizing pin information from the ASIC design to the FPGA prototyping platform includes: identifying the I / O PAD technology library module in the ASIC design; generating the bidirectional I / O port control logic module within the FPGA prototyping platform based on the identified module; and synchronizing the direction information of the pin signals to the top-level module of the FPGA prototyping platform according to the input / output / bidirectional definition of each pin signal in the ASIC design.

2. The method according to claim 1, characterized in that, Identify each phase-locked loop (PLL) technology library module in the ASIC design and analyze the relevant parameters of the PLL, including: Identify each phase-locked loop (PLL) technology library module in the ASIC design and analyze the proportional relationship between the input clock frequency, the number of output clock channels, the output clock frequency, and the frequency of each output channel for each PLL.

3. The method according to claim 1, characterized in that, Identify each memory technology library module in the ASIC design and analyze the relevant parameters of the memory module, including: Identify each memory technology library module in the ASIC design and analyze the memory module's input / output clock, input / output data signal bit width, input / output address signal bit width, and memory depth parameters.

4. The method according to claim 1, characterized in that, Also includes: The generated phase-locked loop IP module, memory IP module, and bidirectional I / O port control logic module are checked to ensure there are no syntax errors.

5. An apparatus for porting an FPGA prototype verification platform, characterized in that, The device includes: An import module, configured to import ASIC design project files into a project within an FPGA prototyping environment; The identification module is configured to identify each phase-locked loop (PLL) process library module in the ASIC design, analyze the relevant parameters of the PLL, and generate the PLL IP module of the FPGA prototype verification platform based on the analyzed parameters. The analysis module is configured to identify each memory technology library module in the ASIC design, analyze the relevant parameters of the memory module, and generate the memory IP module of the FPGA prototype verification platform based on the analyzed parameters. The synchronization module is configured to generate a bidirectional IO port control logic module within the FPGA prototype verification platform based on the IO PAD process library module in the ASIC design, and to synchronize the pin information in the ASIC design to the FPGA prototype verification platform. The identification module is further configured to map the highest output frequency of the phase-locked loop in the ASIC design to the highest frequency expected to be achieved in the FPGA prototyping platform; to perform proportional frequency reduction processing on each output clock of each phase-locked loop identified in the ASIC design in the FPGA prototyping platform to ensure that the frequency ratio of each output clock is the same as the original phase-locked loop output clock ratio in the ASIC design; and to generate the phase-locked loop IP module of the FPGA prototyping platform according to the output frequency ratio. The analysis module is further configured to summarize the analyzed memory resource overhead and compare the resource overhead with the available block memory resources within the FPGA prototyping platform; in response to the resource overhead not exceeding the available block memory resources within the FPGA prototyping platform, to generate a memory IP module for the FPGA prototyping platform using the block memory resources; in response to the resource overhead exceeding the available block memory resources within the FPGA prototyping platform, to generate a memory IP module for the FPGA prototyping platform using distributed memory resources for the excess memory resource overhead portion. The synchronization module is also configured to identify the IO PAD process library module in the ASIC design, generate a bidirectional IO port control logic module in the FPGA prototype verification platform based on the identified module, and synchronize the direction information of the pin signal to the top-level module of the FPGA prototype verification platform according to the definition of each pin signal input / output / bidirectional in the ASIC design.

6. A computer device, characterized in that, include: At least one processor; as well as A memory storing computer instructions executable on the processor, which, when executed by the processor, implement the steps of the method according to any one of claims 1-4.

7. A computer-readable storage medium storing a computer program, characterized in that, When the computer program is executed by a processor, it implements the steps of the method according to any one of claims 1-4.

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