A substrate for chip stack package, chip stack package structure and method

Abstract

Embodiments of the present disclosure provide a substrate for chip stack packaging, a chip stack packaging structure and a method, the substrate comprising a plurality of sub-substrates stacked, an edge region of the plurality of sub-substrates comprising a plurality of stepped surfaces for placing chips; each of the sub-substrates is provided with a circuit layer, a first pad electrically connected with the circuit layer, and a conductive via corresponding to the first pad, and the sub-substrates are electrically connected through the conductive via. The substrate for chip stack packaging, the chip stack packaging structure and the method of the embodiments of the present disclosure reduce the thickness of the package, the loss of electrical performance, and enhance the reliability through a specific substrate shape and conductive structure in the substrate. The material and environmental requirements for packaging are low, and there is no need to set a bonding wire, so the cost is low.

Description

Technical Field

[0001] The embodiments disclosed herein belong to the field of semiconductor packaging technology, specifically relating to a substrate for chip stacking packaging, a chip stacking packaging structure, and a method. Background Technology

[0002] Traditional chip stacking and packaging interconnects can typically be implemented using two methods: (1) wire bonding and (2) through-silicon vias (TSVs). TSV technology has significant limitations and is relatively expensive. Wire bonding, on the other hand, is a mature, low-cost, widely used, and easy-to-implement interconnect technology, often used in consumer-grade memory products.

[0003] However, this type of packaging structure has some problems. For example, the package is thick; the bonding wires between the chip and the substrate introduce large parasitic parameters, causing the electrical performance to fall short of expectations and resulting in low reliability.

[0004] Therefore, how to further reduce the thickness of the package, improve the reliability of the package, and reduce the loss of electrical performance while controlling costs is a major problem that urgently needs to be solved. Summary of the Invention

[0005] The embodiments disclosed herein aim to at least solve one of the technical problems existing in the prior art, and provide a substrate for chip stacking packaging, a chip stacking packaging structure and method.

[0006] One aspect of this disclosure provides a substrate for chip stacking packaging, including a multilayer sub-substrate stacked together, wherein the edge region of the multilayer sub-substrate includes a plurality of stepped surfaces for placing chips;

[0007] Each of the sub-substrates is provided with a circuit layer, a first pad electrically connected to the circuit layer, and a conductive via corresponding to the first pad. The sub-substrates of each layer are electrically connected to each other through the conductive vias.

[0008] Optionally, the length of the multilayer sub-substrate decreases sequentially along its stacking direction.

[0009] Optionally, the plurality of stepped surfaces are symmetrically distributed in the edge regions on both sides of the multilayer sub-substrate.

[0010] Optionally, at least one plastic sealing hole is also provided in the edge region of the sub-substrate located at the bottom layer.

[0011] Optionally, a plurality of plastic sealing holes are provided in the edge region of the sub-substrate located at the bottom layer, and the plurality of plastic sealing holes are symmetrically arranged in the edge regions on both sides of the sub-substrate layer.

[0012] Optionally, the thickness of each of the sub-substrates is consistent with the thickness of the chip on which it is placed.

[0013] Another aspect of this disclosure provides a chip stacking package structure, including a plurality of chips having second pads, a molding compound, and a substrate, said substrate being the substrate described above;

[0014] The chips are stacked on the corresponding stepped surfaces, and the second pads of the chips are soldered to the corresponding first pads;

[0015] The molding compound covers the substrate and the plurality of chips.

[0016] Optionally, when the substrate includes a plastic sealing hole, the molding body includes a molding body portion and a plastic sealing fastening portion;

[0017] The encapsulated body covers the substrate and the plurality of chips, and the encapsulated sealing portion is inserted into the encapsulated hole.

[0018] Optionally, the structure further includes multiple adhesive layers disposed between the corresponding sub-substrate and the chip.

[0019] Optionally, the structure further includes solder balls, which are disposed on a third pad prefabricated on the side of the sub-substrate opposite to the chip, and the third pad is electrically connected to the circuit layer.

[0020] The final aspect of this disclosure provides a chip stacking packaging method, comprising:

[0021] A substrate and multiple chips are provided respectively; wherein the substrate is the substrate described above;

[0022] Each of the chips is stacked sequentially onto the step surface corresponding to the substrate;

[0023] The plurality of chips and the substrate are encapsulated to form an encapsulated body;

[0024] Balls are implanted on the side of the substrate away from the plurality of chips.

[0025] This disclosure discloses a chip stacking packaging substrate, chip stacking packaging structure, and method. Through a specific substrate shape and conductive structure within the substrate, the thickness and electrical performance loss of the package are reduced, and reliability is enhanced. Furthermore, the packaging requires low-cost materials and has low environmental requirements, eliminating the need for bonding wires and resulting in low cost. Attached Figure Description

[0026] Figure 1 This is a schematic diagram of existing common chip stacking methods;

[0027] Figure 2This is a schematic diagram of the structure of a chip stacking packaging substrate according to an embodiment of the present disclosure;

[0028] Figure 3 This is a schematic diagram of a chip stacking packaging structure according to another embodiment of the present disclosure;

[0029] Figure 4 This is a schematic flowchart of a chip stacking and packaging method according to another embodiment of the present disclosure. Detailed Implementation

[0030] In current common chip stacking packaging methods, low-cost semiconductor products for consumer use mainly employ wire bonding interconnects. For example... Figure 1 As shown, existing wire bonding chip stacking methods mainly include, for example... Figure 1 (a) shows a step-like stack, as in Figure 1 (b) shows the stack by spacer, as Figure 1 (c) shows the film on wire (FOW) and as shown in the image. Figure 1 (d) shows film on die (FOD), etc.

[0031] like Figure 1 As shown, all of the above stacking methods require the addition of an intermediate material layer 130 between the substrate 110 and the chip 120, and between chips 120, resulting in a larger thickness of the final package; they all require the setting of bonding wires 140 to interconnect the chip 120 and the substrate 110, which results in larger parasitic parameters and a loss of overall electrical performance; and the reliability of the wire bonding method itself is also lower compared with other existing packaging methods.

[0032] To this end, this disclosure provides a series of solutions to overcome the above-mentioned problems.

[0033] To enable those skilled in the art to better understand the technical solutions of this disclosure, the disclosure will be further described in detail below with reference to the accompanying drawings and specific embodiments.

[0034] like Figure 2 As shown, embodiments of this disclosure provide a chip stacking packaging substrate 200, including multilayer sub-substrates 210 stacked together. The edge regions of the multilayer sub-substrates 210 include multiple stepped surfaces 211 for placing chips. Each sub-substrate 210 is provided with a circuit layer 220, a first pad 230 electrically connected to the circuit layer 220, and a conductive via 240 corresponding to the first pad 230. The sub-substrates 210 are electrically connected to each other through the conductive vias 240.

[0035] Specifically, combined Figure 3 When performing chip stacking and packaging using the substrate 200 of this embodiment, multiple chips 310 are stacked sequentially on the corresponding step surfaces 211, and the second pads 311 on the chip 310 are soldered to the first pads 230 on the corresponding sub-substrate 210, so that the chip 310 can be electrically connected to the substrate 200 through the second pads 311, the first pads 230 and the conductive vias 240.

[0036] The chip stacking packaging substrate provided in this embodiment is used to solder chips onto various step surfaces of the substrate, resulting in a relatively thin chip stack. Furthermore, the substrate has lateral circuit layers and vertical conductive vias, eliminating the need for bonding wires, thus reducing cost and increasing reliability.

[0037] For example, such as Figure 2 As shown, the length of the multilayer sub-substrate 210 decreases sequentially along its stacking direction, and the plurality of stepped surfaces 211 are symmetrically distributed in the edge regions on both sides of the multilayer sub-substrate 210. That is, as... Figure 2 As shown, stepped surfaces 211 are present on both the left and right edges of the multilayer sub-substrate 210. (This is combined with...) Figure 3 When performing chip stacking and packaging, multiple chips are stacked sequentially on the stepped surfaces 211 of the left and right edge regions of the sub-substrate 210, which can further reduce the thickness of the chip stacked package and effectively improve the reliability of the package.

[0038] It should be noted that, in addition to symmetrically distributing multiple step surfaces, those skilled in the art can also adopt other distribution methods for multiple step surfaces according to actual needs. For example, the step surfaces can be distributed in the same edge area of ​​the sub-substrate, etc. This embodiment does not limit this.

[0039] It should be understood that the thickness of each sub-substrate needs to be determined based on the thickness of the chips stacked on the sub-substrate below it, so as to ensure that after the chips are stacked, the upper surface of each chip is flush with the upper surface of the corresponding sub-substrate, so that all chips are flatly attached to the substrate, thereby improving the reliability and safety of the package.

[0040] For example, such as Figure 2 As shown, a plurality of plastic sealing holes 250 are also provided in the edge region of the sub-substrate 210 located at the bottom layer. The plastic sealing holes 250 can be obtained by etching blind holes of a certain depth on the bottom sub-substrate 210. The specific depth of the plastic sealing holes 250 can be determined according to actual needs, for example, two-thirds of the thickness of the bottom sub-substrate 210.

[0041] Specifically, combined Figure 3After the chip stacking is completed using the substrate 200 of this embodiment, the multiple chips 310 and the entire substrate 200 are encapsulated using the molding compound 320. A protruding structure, namely the molding sealing part 322 mentioned below, is formed in the bottom edge region of the molding compound 320. The molding sealing part 322 is inserted into the molding sealing hole 250, thereby improving the molding reliability of the molding compound 320.

[0042] It should be understood that the plastic sealing hole 250 needs to be located on the outside of the chip 310 stacked on the bottom sub-substrate 210.

[0043] It should be noted that the distribution of the plastic sealing holes (such as on one or both edges of the bottom sub-substrate 210) depends on the distribution of the step surface 211. When the step surface 211 is symmetrically distributed, multiple plastic sealing holes 250 can be symmetrically arranged in the two edge areas of the bottom sub-substrate 210.

[0044] The substrate of the present disclosure has a plastic sealing hole provided in the edge region of the bottom sub-substrate of the substrate. During plastic sealing, the plastic sealing material extends into the plastic sealing hole to lock the plastic sealing layer laterally, thereby enhancing the bonding force between the plastic sealing layer and the substrate and improving the stability and reliability of the product.

[0045] like Figure 3 As shown, another embodiment of this disclosure provides a chip stacking package structure, including a plurality of chips 310, a molding compound 320, and a substrate 330, wherein the substrate 330 is the substrate described above; each chip 310 is provided with a second pad 311, the chips 310 are stacked on a corresponding step surface 332, and the second pad 311 of the chip 310 is soldered to the corresponding first pad 331; the molding compound 320 covers the substrate 330 and the plurality of chips 310.

[0046] Specifically, the corresponding chips are stacked sequentially from the bottom substrate to the top substrate. The chips are fixed in predetermined positions on the substrate by soldering the pads on the chips to the corresponding pads on the substrate, thus forming an electrical connection between the chips and the substrate. Finally, the substrate and chips are encapsulated together.

[0047] Depend on Figure 3As can be seen, the thickness of each sub-substrate in substrate 330 is equal to that of the chips 310 on both sides, thereby avoiding affecting the stacking of the upper-layer chips. In some embodiments, the chip thickness may differ from the thickness of the corresponding sub-substrate. In order not to affect the stacking of the upper-layer chips, when the chip thickness is greater than the thickness of the corresponding sub-substrate, the chip can be thinned by grinding to match the thickness of the corresponding sub-substrate; when the chip thickness is less than the thickness of the corresponding sub-substrate, an intermediate material layer, such as a silicon interposer, can be formed on the lower surface of the chip, and then vias can be formed at the positions of the corresponding chip pads and filled with conductive material, such as TSV process, so that the total thickness of the chip and the intermediate material layer is consistent with the thickness of the corresponding sub-substrate.

[0048] The packaging structure of this disclosure reduces the thickness of the packaging structure by using the aforementioned stepped substrate; it eliminates the need for bonding wires, thereby reducing electrical performance loss and enhancing reliability.

[0049] For example, such as Figure 3 As shown, when the substrate 330 includes a plastic sealing hole 333, the molding body 320 includes a molding body portion 321 and a molding sealing portion 322. The molding body portion 321 covers the substrate 330 and the plurality of chips 310, and the molding sealing portion 322 is inserted into the plastic sealing hole 333.

[0050] Specifically, when a molding seal hole is pre-drilled on the substrate, the molding material will extend into the molding seal hole during the overall molding of the substrate and the chip. The aforementioned molding body and molding seal portion constitute a complete molding body, which encapsulates the entire structure, including the substrate and the chip, to form an integrated packaging structure.

[0051] The packaging structure of this disclosure enhances the stability and reliability of the product by providing a plastic sealing hole to laterally lock the plastic sealing layer onto the substrate.

[0052] For example, such as Figure 3 As shown, the structure also includes a plurality of adhesive layers 340, which are disposed between the corresponding sub-substrate 332 and the chip 310.

[0053] Specifically, by Figure 3 As can be seen, the thickness of the adhesive layer is equal to the combined thickness of the chip pad 311, the substrate pad 331, and the circuit layer within the substrate 330. It is flush with the side edge of the corresponding chip 310, bonding the chip to the corresponding step surface of the substrate and a portion of the area of ​​the chip beneath it, providing additional bonding force between the chip and the substrate beyond the solder joints. Clearly, the chip on the bottom substrate has no underlying chip, and its adhesive layer area is included within the step surface area of ​​the bottom substrate. Understandably, the adhesive layer may or may not extend beyond the side edge of the chip above it, but being perfectly flush is optimal.

[0054] The packaging structure of this disclosure increases the stability and reliability of the packaging structure by using an adhesive material to form an adhesive layer to bond the chip to the substrate and the underlying chip.

[0055] For example, such as Figure 3 As shown, the chip stacking package structure also includes solder balls 350, which are disposed on a third pad 360 prefabricated on the side of the sub-substrate 332 away from the chip 310. The third pad 360 is electrically connected to the circuit layer.

[0056] Specifically, after molding and forming the overall package structure, solder balls can be added to the package structure. Using methods such as laser soldering, multiple solder balls are soldered to multiple pre-prepared pads on the lower surface of the bottom substrate, forming a package structure with solder balls. The specific positions of the pads on the lower surface of the substrate are determined based on the positions of the pads on the printed circuit board to which this package structure needs to be soldered. If the position of the pad on the circuit board corresponds exactly to the position of the conductive via on the lower surface of the substrate, the pad on the lower surface of the substrate can be directly placed at the opening of the conductive via; otherwise, an additional conductive path needs to be set in the substrate to make the pad electrically connected to the chip.

[0057] The packaging structure of this disclosure, by setting solder balls, can improve the electrothermal performance of the chip, increase the signal transmission frequency, and help protect the chip, thereby improving the reliability, security and stability of the packaging structure.

[0058] like Figure 4 As shown, the last embodiment of this disclosure provides a chip stacking packaging method, including:

[0059] Step S41: Provide a substrate and a plurality of chips respectively; wherein the substrate is the substrate described above.

[0060] Specifically, based on the shape of the substrate described above, it can be referred to as a stepped substrate. When fabricating a stepped substrate, the thickness of the chips to be mounted on each step should be predetermined. Except for the first step at the bottom of the substrate, the thickness of each step above it should be consistent with the thickness of the chips to be mounted on the next step. Furthermore, substrate pads are pre-positioned on the step surface according to the positions of the chip pads, for soldering each chip to its predetermined location on the substrate. Conversely, the chip thickness and the position of the chip pads can be adjusted based on the pre-determined thickness of each step and the position of the substrate pads.

[0061] The substrate and chip dimensions of the present disclosure embodiments are matched, so that each layer of chip can be mounted flat on the substrate, ensuring the stability and security of the packaging structure, while controlling the thickness of the packaging structure to be minimized.

[0062] Step S42: Stack each chip sequentially onto the step surface corresponding to the substrate.

[0063] Apply soldering material to the chip's pads, and apply adhesive material to other areas on the same surface as the pads. Then, with the chip's pads facing down and aligned with the pads on the substrate, perform soldering and mounting sequentially from bottom to top.

[0064] Step S43: Moldulate the plurality of chips and the substrate to form a molded body.

[0065] Specifically, adhesive is applied to the surfaces of the chip and substrate before molding to form a molded package. Applying adhesive further increases the adhesion between the molding material and the chip and substrate surfaces, improving the reliability of the packaging structure.

[0066] Step S44: Ball placement is performed on the side of the substrate away from the plurality of chips.

[0067] Specifically, based on the specific pad locations on the printed circuit board to be mounted on the substrate, corresponding pads are pre-prepared at corresponding positions on the lower surface of the substrate. The prepared pads may be located precisely at exposed conductive vias on the lower surface of the substrate, or they may be in other locations. When the pads are in other locations, they cannot be directly interconnected with the chip through the conductive vias or circuit layers in the substrate as described above. In this case, additional conductive paths are needed within the substrate to connect the pads to the conductive vias or circuit layers, thereby electrically connecting the pads to the chip. After forming the molding compound, solder balls are implanted at the pads at the bottom of the molding compound to form the overall package structure. The solder ball implantation improves the electrothermal performance of the package structure, increases the signal transmission frequency, and helps protect the chip, thus improving the reliability, security, and stability of the package structure.

[0068] The chip stacking and packaging method of this disclosure uses a substrate with a specific shape and internal conductive structure for chip packaging, which reduces the thickness of the packaging structure, reduces electrical performance loss, and enhances reliability. Furthermore, the packaging requires low-cost materials and has low environmental requirements, eliminates the need for bonding wires, and is cost-effective.

[0069] It is understood that the above embodiments are merely exemplary embodiments used to illustrate the principles of this disclosure, and this disclosure is not limited thereto. For those skilled in the art, various modifications and improvements can be made without departing from the spirit and substance of this disclosure, and these modifications and improvements are also considered to be within the scope of protection of this disclosure.

Claims

1. A substrate for chip stacking and packaging, characterized in that, The substrate includes multiple sub-substrates stacked together, and the edge region of the multiple sub-substrates includes multiple stepped surfaces for placing chips. The length of the multilayer sub-substrate decreases sequentially along its stacking direction; the multiple stepped surfaces are symmetrically distributed in the edge regions on both sides of the multilayer sub-substrate. The thickness of each sub-substrate is the same as the thickness of the chip stacked on the sub-substrate below it; Each of the sub-substrates is provided with a circuit layer, a first pad electrically connected to the circuit layer, and a conductive via corresponding to the first pad. The sub-substrates of each layer are electrically connected to each other through the conductive vias.

2. The substrate according to claim 1, characterized in that, At least one plastic sealing hole is also provided in the edge region of the sub-substrate located at the bottom layer.

3. The substrate according to claim 2, characterized in that, Multiple plastic sealing holes are provided in the edge region of the sub-substrate located at the bottom layer, and the multiple plastic sealing holes are symmetrically arranged in the edge regions on both sides of the sub-substrate layer.

4. A chip stacking packaging structure, characterized in that, It includes a plurality of chips having a second pad, a molding compound, and a substrate, wherein the substrate is the substrate according to any one of claims 1 to 3; The chips are stacked on the corresponding stepped surfaces, and the second pads of the chips are soldered to the corresponding first pads; The molding compound covers the substrate and the plurality of chips.

5. The chip stacking packaging structure according to claim 4, characterized in that, When the substrate includes a plastic sealing hole, the molding body includes a molding body portion and a plastic sealing fastening portion; The encapsulated body covers the substrate and the plurality of chips, and the encapsulated sealing portion is inserted into the encapsulated hole.

6. The chip stacking packaging structure according to claim 4 or 5, characterized in that, It also includes multiple adhesive layers, which are disposed between the corresponding sub-substrate and the chip.

7. The chip stacking packaging structure according to claim 4 or 5, characterized in that, It also includes solder balls, which are disposed on a third pad prefabricated on the side of the sub-substrate opposite to the chip, and the third pad is electrically connected to the circuit layer.

8. A chip stacking and packaging method, characterized in that, include: A substrate and a plurality of chips are provided respectively; wherein the substrate is the substrate according to any one of claims 1 to 3; Each of the chips is stacked sequentially onto the step surface corresponding to the substrate; The plurality of chips and the substrate are encapsulated to form an encapsulated body; Balls are implanted on the side of the substrate away from the plurality of chips.

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