An ARINC429 transceiver based on HI-8282

Abstract

This invention discloses an ARINC429 transceiver based on the HI-8282, including a 429 data interface and a data conversion module. It provides a driver for the HI-8282 chip to achieve ARINC429 data transmission and reception functions. The 429 data interface and data conversion module consist of a 429 interface unit and an MCU control and processing unit. A host computer display and control module is responsible for all data reception and transmission conversion processing, as well as lower-level computer instruction control. A power supply module includes a voltage conversion circuit that can convert 16V-36V DC power to +15V, -15V, and +5V DC power to power the 429 data interface and data conversion module. This invention effectively reduces maintenance costs by using the HI-8282 and HI-8585 chips. Through the setting of a complete communication protocol and the development of host and lower-level computer software, it exhibits strong portability.

Description

Technical Field

[0001] This invention relates to the field of aircraft maintenance, specifically to an ARINC429 transceiver based on the HI-8282. Background Technology

[0002] The ARINC 429 bus protocol was proposed by the Airlines Engineering Committee in July 1977, and published and approved for use in the same month. Its full name is Digital Information Transmission System (DITS). The protocol standard specifies the requirements for digital information transmission between avionics equipment and related systems.

[0003] ARINC429 is widely used in advanced civil aircraft such as the B-737, B757, and B-767. The ARINC429 bus has a simple structure, stable performance, and strong anti-interference capabilities; its greatest advantage lies in its high reliability, due to its decentralized control, reliable transmission, and good error isolation. The ARINC-429 bus standard provides a serial standard that operates in a differential output symmetrical manner, and is an interface-oriented, unidirectional broadcast transmission bus. The standard specifies that only one transmitter is allowed on the bus, but multiple receivers (up to 20) are permitted. The bus standard recommends using twisted-pair shielded cable for asynchronous data transmission.

[0004] The general signal characteristics of ARINC429 are shown in the attached instruction manual. Figure 1 As shown, ARINC429 signals that need to be decoded are frequently encountered in the field of aviation maintenance. Traditional ARINC429 signal decoding is achieved through test benches designed by the original manufacturer and some dedicated ARINC429 communication boards. Since these communication boards are relatively expensive and cannot be used for secondary development, they can affect the normal maintenance of certain components in many cases. In order to solve this problem, it is necessary to develop a new transceiver device that conforms to the ARINC429 communication protocol and that can be well used for the secondary development of test equipment. Summary of the Invention

[0005] The purpose of this invention is to provide an ARINC429 transceiver based on HI-8282 to solve the problems mentioned in the background art.

[0006] To achieve the above objectives, the present invention provides the following technical solution: an ARINC429 transceiver based on HI-8282, comprising:

[0007] The 429 data interface and data conversion module provides a driver for the HI-8282 chip to achieve the function of transmitting and receiving ARINC429 data. The 429 data interface and data conversion module consists of a 429 interface unit and an MCU control and processing unit.

[0008] The host computer display and control module is responsible for all data reception and transmission conversion processing, as well as command control of the slave computer;

[0009] The power module includes a voltage conversion circuit that can convert 16V-36V DC power to +15V, -15V, and 5V DC power, and power the 429 data interface and data conversion module.

[0010] Preferably, the 429 interface unit consists of 429 interface circuit chips HI-8282 and HI-8585, and multiple auxiliary interface circuits, including auxiliary interface circuits A, B, C, D, E, F, and G.

[0011] The auxiliary interface circuit A is connected to pin 41 of the chip HI-8282. The auxiliary interface circuit A includes chip X1 with model number XTAL-ACT4P and capacitors C1 and C2. Pin 4 of chip X1 is connected to the VCC terminal, pin 1 of chip X1 is connected to capacitor C2 and grounded, pin 3 of chip X1 is connected to pin 41 of chip HI-8282, and pin 2 of chip X1 is grounded.

[0012] The auxiliary interface circuit B is connected to pins 2 and 3 of the HI-8282 chip. The auxiliary interface circuit B includes plug-in JP2, resistors R3 and R4, and capacitors C5 and C6. The first interface of plug-in JP2 is connected to the first end of resistor R4. The second end of resistor R4 is connected to capacitor C6 and grounded in one path, and connected to pin 2 of the HI-8282 chip in the other path. The second interface of plug-in JP2 is connected to the first end of resistor R3. The second end of resistor R3 is connected to capacitor C5 and grounded in one path, and connected to pin 3 of the HI-8282 chip in the other path.

[0013] The auxiliary interface circuit C is connected to pins 4 and 5 of the HI-8282 chip. The auxiliary interface circuit C includes resistors R8 and R9, capacitors C7, C8, C9, and C10, and connectors JP4, JP5, and JP6. Connector JP4's first interface is connected to the first terminal of resistor R8. The second terminal of resistor R8 is split into two paths: one connected to capacitor C7 and grounded, and the other connected to pin 5 of the HI-8282 chip. Connector JP4's second interface is connected to the first terminal of resistor R9. The second terminal of resistor R9 is split into two paths: one connected to capacitor C8 and grounded, and the other connected to pin 4 of the HI-8282 chip. Connector JP5's first interface is connected to the second interface of connector JP6. Connector JP5's second interface is connected to the first terminal of capacitor C9. The second terminal of capacitor C9 is connected to the second interface of JP6 and the first interface of connector JP5 and grounded. Connector C10's first terminal is connected to the second terminal of capacitor C9. The second terminal of capacitor C10 is connected to the first interface of JP6.

[0014] Preferably, pins 2 and 3 of the HI-8585 chip are connected to pins 34 and 35 of the HI-8282 chip, and pins 6 and 7 of the HI-8585 chip are connected to the auxiliary interface circuit G.

[0015] Preferably, the MCU control processing unit is used for driving the interface chip, decoding the host computer control instructions, and converting ARINC input and output data.

[0016] Preferably, the voltage conversion circuit includes a DC-DC chip U1, a single-pole switch S1, polarized capacitors C2, C3, C4, C5, C6, C7, C8, light-emitting diodes D1, D2, D3, resistors R1, R2, R3, and connectors J1, J2, J3, J4, J5. Pin 4 of chip U1 is connected to the positive terminal of polarized capacitor C5 and the second interface of connector J3. Pin 1 of chip U1 is connected to the positive terminal of polarized capacitor C5, and the negative terminal of polarized capacitor C5 is grounded. Pin 3 of chip U1 is connected to the second terminal of single-pole switch S1. One terminal of single-pole switch S1 is connected to the negative terminal of polarized capacitor C5 and grounded, and the other terminal is connected to the second terminal of J3. Pin 6 of chip U1 is connected to the first terminal of resistor R2. Pin 5 of chip U1 is connected to the first interface of connector J4. The second interface of connector J4 is connected to pin 5 of chip U1 through polarized capacitor C4. One path is connected to a polarized capacitor C6 and grounded; pins 7, 8, and 11 of chip U1 are connected to the negative terminal of polarized capacitor C4; pins 11, 10, 14, 13, and 3 of chip U1 are connected to interfaces 1, 2, 3, 4, and 5 of connector J5 respectively; pin 16 of chip U1 is split into two paths connected to polarized capacitors C7 and C8 respectively and grounded; interface 1 of connector J2 is connected to the positive terminal of capacitor C2; interface 2 of connector J2 is connected in one path to the negative terminal of polarized capacitor C2, and the other path is connected to the second terminal of resistor R2 via LED D2; interface 1 of connector J1 is connected to the positive terminal of polarized capacitor C1; interface 2 of connector J1 is connected in one path to the negative terminal of polarized capacitor C1, and the other path is connected to LED D1 and grounded; resistor R3 and LED D3 are connected in series between interface 1 of connector J1 and the grounded terminal to which LED D1 is connected.

[0017] Compared with the prior art, the beneficial effects of the present invention are:

[0018] This invention effectively reduces maintenance costs by using HI-8282 and HI-8585 chips. Through the setting of a complete communication protocol and the development of upper and lower computer software, it has strong portability and can be more conveniently used in the development of other test benches that require ARINC429 communication. Using the results of this project, customized development of test equipment can be realized, and the development efficiency of test benches can be improved. Attached Figure Description

[0019] Figure 1 This is a typical signal characteristic diagram of the ARINC429 signal;

[0020] Figure 2 This is a diagram of the module architecture of the present invention;

[0021] Figure 3This is a schematic diagram of the conversion circuit of the power module in this invention.

[0022] Figure 4 The circuit schematic of the interface circuit chip HI-8282 of this invention is shown below.

[0023] Figure 5 This is a schematic diagram of the auxiliary interface circuit in an embodiment of the present invention;

[0024] Figure 6 This is a schematic diagram of the HI-8585 chip in an embodiment of the present invention;

[0025] Figure 7 This is a flowchart of the HI-8282 data receiving program in an embodiment of the present invention;

[0026] Figure 8 This is a flowchart of the HI-8282 data transmission program in an embodiment of the present invention. Detailed Implementation

[0027] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0028] The purpose of this invention is to use the HI-8282J and HI-8585 chips manufactured by HOLT Corporation to realize the function of transmitting and receiving ARINC429 protocol data.

[0029] Please see Figure 1-6 The present invention provides a technical solution: an ARINC429 transceiver based on HI-8282, comprising:

[0030] The 429 data interface and data conversion module provides a driver for the HI-8282 chip to achieve the function of transmitting and receiving ARINC429 data. The 429 data interface and data conversion module consists of a 429 interface unit and an MCU control and processing unit.

[0031] The host computer display and control module is responsible for all data reception and transmission conversion processing, as well as command control of the slave computer;

[0032] The power module includes a voltage conversion circuit that can convert 16V-36V DC power to +15V, -15V, and 5V DC power, and power the 429 data interface and the data conversion module.

[0033] In this embodiment, the 429 interface unit consists of 429 interface circuit chips HI-8282 and HI-8585, as well as multiple auxiliary interface circuits, including auxiliary interface circuit A, auxiliary interface circuit B, auxiliary interface circuit C, auxiliary interface circuit D, auxiliary interface circuit E, auxiliary interface circuit F, and auxiliary interface circuit G.

[0034] In this embodiment, the auxiliary interface circuit A is connected to pin 41 of the chip HI-8282. The auxiliary interface circuit A includes a chip X1 of model XTAL-ACT4P and capacitors C1 and C2. Pin 4 of chip X1 is connected to the VCC terminal, pin 1 of chip X1 is connected to capacitor C2 and grounded, pin 3 of chip X1 is connected to pin 41 of chip HI-8282, and pin 2 of chip X1 is grounded.

[0035] In this embodiment, the auxiliary interface circuit B is connected to pins 2 and 3 of the chip HI-8282. The auxiliary interface circuit B includes a plug-in JP2, resistors R3 and R4, and capacitors C5 and C6. The first interface of the plug-in JP2 is connected to the first end of the resistor R4. The second end of the resistor R4 is connected to the capacitor C6 and grounded in one way, and connected to pin 2 of the chip HI-8282 in the other way. The second interface of the plug-in JP2 is connected to the first end of the resistor R3. The second end of the resistor R3 is connected to the capacitor C5 and grounded in one way, and connected to pin 3 of the chip HI-8282 in the other way.

[0036] In this embodiment, the auxiliary interface circuit C is connected to pins 4 and 5 of the HI-8282 chip. The auxiliary interface circuit C includes resistors R8 and R9, capacitors C7, C8, C9, and C10, and plug-ins JP4, JP5, and JP6. The first interface of plug-in JP4 is connected to the first end of resistor R8. The second end of resistor R8 is split into two paths: one path is connected to capacitor C7 and grounded, and the other path is connected to pin 5 of the HI-8282 chip. The second interface of plug-in JP4 is connected to the first end of resistor R9. The second end of resistor R9 is split into two paths: one path is connected to capacitor C8 and grounded, and the other path is connected to pin 4 of the HI-8282 chip. The first interface of plug-in JP5 is connected to the second interface of plug-in JP6. The second interface of plug-in JP5 is connected to the first end of capacitor C9. The second end of capacitor C9 is connected to the second interface of JP6 and the first interface of plug-in JP5 and grounded. The first end of capacitor C10 is connected to the second end of capacitor C9. The second end of capacitor C10 is connected to the first interface of JP6.

[0037] In this embodiment, pins 2 and 3 of the HI-8585 chip are connected to pins 34 and 35 of the HI-8282 chip, and pins 6 and 7 of the HI-8585 chip are connected to the auxiliary interface circuit G.

[0038] In this embodiment, the MCU control processing unit is used for driving the interface chip, decoding the host computer control instructions, and converting ARINC input and output data.

[0039] In this embodiment, by combining the control of the two units (MCU control and processing unit and 429 interface unit), the functions of 2 ARINC429 inputs and 1 ARINC429 output can be realized, and the relevant data can be forwarded through the host computer.

[0040] In this embodiment, the voltage conversion circuit includes a DC-DC chip U1, a single-pole switch S1, polarized capacitors C2, C3, C4, C5, C6, C7, and C8, light-emitting diodes D1, D2, and D3, resistors R1, R2, and R3, and connectors J1, J2, J3, J4, and J5. Pin 4 of chip U1 is connected to the positive terminal of polarized capacitor C5 and the second interface of connector J3. Pin 1 of chip U1 is connected to the positive terminal of polarized capacitor C5, and the negative terminal of polarized capacitor C5 is grounded. Pin 3 of chip U1 is connected to the second terminal of single-pole switch S1. One terminal of single-pole switch S1 is connected to the negative terminal of polarized capacitor C5 and grounded, and the other terminal is connected to the second terminal of J3. Pin 6 of chip U1 is connected to the first terminal of resistor R2. Pin 5 of chip U1 is connected to the first interface of connector J4. The second interface of connector J4 is connected to pin 5 of chip U1 via polarized capacitor C4. Another path is connected to a polarized capacitor C6 and grounded; pins 7, 8, and 11 of chip U1 are connected to the negative terminal of polarized capacitor C4; pins 11, 10, 14, 13, and 3 of chip U1 are connected to interfaces 1, 2, 3, 4, and 5 of connector J5 respectively; pin 16 of chip U1 is split into two paths connected to polarized capacitors C7 and C8 respectively and grounded; interface 1 of connector J2 is connected to the positive terminal of capacitor C2; interface 2 of connector J2 is connected in one path to the negative terminal of polarized capacitor C2, and in the other path is connected to the second terminal of resistor R2 via LED D2; interface 1 of connector J1 is connected to the positive terminal of polarized capacitor C1; interface 2 of connector J1 is connected in one path to the negative terminal of polarized capacitor C1, and in the other path is connected to LED D1 and grounded; resistor R3 and LED D3 are connected in series between interface 1 of connector J1 and the grounded terminal to which LED D1 is connected.

[0041] Please see Figure 1-8 The specific working principle is as follows:

[0042] Since the ARINC429 standard protocol requires the transmission of two words of data, these two words need to be placed on the bus in binary form. However, the HI-8282's data pins are only 8 bits, so the data needs to be transmitted in segments. In the following description, PL1 and PL2 are the pins that control this transmission.

[0043] According to the HI-8282 datasheet, when sending data, you should check if the TX / R pin is high (TX / R is similar to a status bit, mainly used to indicate whether there is data in the HI-8282's transmit memory. This data is applied to the corresponding pin of the HI-8282 through the microcontroller's I / O port). If it is high, it means that there is no data in the transmit memory. At this time, setting the ENTX pin to low will stop sending data and write the data to be sent to BD00-BD15.

[0044] Then, to send data word 1, set PL1 low and PL2 high; to send data word 2, set PL1 high and PL2 low.

[0045] Next, check if the TX / R pin is low. If it is low, it indicates that the data has been loaded into the memory. At this point, switch the ENTX pin to high to send the data. The HI-8282's transmit memory can hold up to eight 32-bit words of data, using a first-in-first-out (FIFO) transmission order.

[0046] When receiving data, the chip sets DIR1 to low level after receiver 1 receives the data; when receiver 2 receives the data, the chip sets DIR2 to low level.

[0047] To enable the receiver to send data received on BD00-BD15, first set SEL to low, then set EN1 to low and EN2 to high. Then set SEL high again to send word 2 to the 16-bit data bus. To send data from receiver 2 to the 16-bit data bus, set EN2 to low and EN1 to high.

[0048] Since the HI-8282 chip does not support differential ARINC429 signal output, the HI-8585 chip is required for ARINC429 level conversion to obtain ARINC429 signals that conform to the protocol.

[0049] Although embodiments of the invention have been shown and described, it will be understood by those skilled in the art that various changes, modifications, substitutions and alterations can be made to these embodiments without departing from the principles and spirit of the invention, the scope of which is defined by the appended claims and their equivalents.

Claims

1. An ARINC429 transceiver based on HI-8282, characterized in that, include: The 429 data interface and data conversion module provides a driver for the HI-8282 chip to achieve the function of transmitting and receiving ARINC429 data. The 429 data interface and data conversion module consists of a 429 interface unit and an MCU control and processing unit. The host computer display and control module is responsible for all data reception and transmission conversion processing, as well as the command control of the slave computer; The power module includes a voltage conversion circuit that can convert 16V-36V DC power to +15V, -15V, and 5V DC power, and power the 429 data interface and data conversion module. The 429 interface unit consists of 429 interface circuit chips HI-8282 and HI-8585, and multiple auxiliary interface circuits, including auxiliary interface circuits A, B, C, D, E, F, and G. The auxiliary interface circuit A is connected to pin 41 of the chip HI-8282. The auxiliary interface circuit A includes chip X1 with model number XTAL-ACT4P and capacitors C1 and C2. Pin 4 of chip X1 is connected to the VCC terminal, pin 1 of chip X1 is connected to capacitor C2 and grounded, pin 3 of chip X1 is connected to pin 41 of chip HI-8282, and pin 2 of chip X1 is grounded. The auxiliary interface circuit B is connected to pins 2 and 3 of the HI-8282 chip. The auxiliary interface circuit B includes plug-in JP2, resistors R3 and R4, and capacitors C5 and C6. The first interface of plug-in JP2 is connected to the first end of resistor R4. The second end of resistor R4 is connected to capacitor C6 and grounded in one path, and connected to pin 2 of the HI-8282 chip in the other path. The second interface of plug-in JP2 is connected to the first end of resistor R3. The second end of resistor R3 is connected to capacitor C5 and grounded in one path, and connected to pin 3 of the HI-8282 chip in the other path. The auxiliary interface circuit C is connected to pins 4 and 5 of the chip HI-8282. The auxiliary interface circuit C includes resistors R8 and R9, capacitors C7, C8, C9, and C10, and plug-ins JP4, JP5, and JP6. The first interface of plug-in JP4 is connected to the first end of resistor R8. The second end of resistor R8 is divided into two paths: one path is connected to capacitor C7 and grounded, and the other path is connected to pin 5 of the chip HI-8282. The second interface of plug-in JP4 is connected to the first terminal of resistor R9. The second terminal of resistor R9 is split into two paths: one path is connected to capacitor C8 and grounded, and the other path is connected to pin 4 of chip HI-8282. The first interface of plug-in JP5 is connected to the second interface of plug-in JP6. The second interface of plug-in JP5 is connected to the first terminal of capacitor C9. The second terminal of capacitor C9 is connected to the second interface of JP6 and the first interface of plug-in JP5 and grounded. The first terminal of capacitor C10 is connected to the second terminal of capacitor C9. The second terminal of capacitor C10 is connected to the first interface of JP6.

2. The ARINC429 transceiver based on HI-8282 according to claim 1, characterized in that: Pins 2 and 3 of the HI-8585 chip are connected to pins 34 and 35 of the HI-8282 chip, and pins 6 and 7 of the HI-8585 chip are connected to the auxiliary interface circuit G.

3. The ARINC429 transceiver based on HI-8282 according to claim 1, characterized in that: The MCU control processing unit is used for driving the interface chip, decoding the host computer control instructions, and converting ARINC input and output data.

4. The ARINC429 transceiver based on HI-8282 according to claim 1, characterized in that: The voltage conversion circuit includes a DC-DC chip U1, a single-pole switch S1, polarized capacitors C2, C3, C4, C5, C6, C7, C8, LEDs D1, D2, D3, resistors R1, R2, R3, and connectors J1, J2, J3, J4, J5. Pin 4 of chip U1 is connected to the positive terminal of polarized capacitor C5 and the second interface of connector J3. Pin 1 of chip U1 is connected to the positive terminal of polarized capacitor C5, and the negative terminal of polarized capacitor C5 is grounded. Pin 3 of chip U1 is connected to the second terminal of single-pole switch S1. One terminal of single-pole switch S1 is connected to the negative terminal of polarized capacitor C5 and grounded, and the other terminal is connected to the second terminal of J3. Pin 6 of chip U1 is connected to the first terminal of resistor R2. Pin 5 of chip U1 is connected to the first interface of connector J4. The second interface of connector J4 is connected to pin 5 of chip U1 via polarized capacitor C4, and the other... A polarized capacitor C6 is connected to the ground. Pins 7, 8, and 11 of chip U1 are connected to the negative terminal of polarized capacitor C4. Pins 11, 10, 14, 13, and 3 of chip U1 are connected to interfaces 1, 2, 3, 4, and 5 of connector J5, respectively. Pin 16 of chip U1 is connected to polarized capacitors C7 and C8 respectively and grounded. Interface 1 of connector J2 is connected to the positive terminal of capacitor C2. Interface 2 of connector J2 is connected to the negative terminal of polarized capacitor C2 in one path and to the second terminal of resistor R2 via LED D2 in the other path. Interface 1 of connector J1 is connected to the positive terminal of polarized capacitor C1. Interface 2 of connector J1 is connected to the negative terminal of polarized capacitor C1 in one path and to LED D1 in the other path and grounded. Resistor R3 and LED D3 are connected in series between interface 1 of connector J1 and the grounded terminal to which LED D1 is connected.

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