Router for realizing continuous single - cycle multi - hop traversal in network - on - chip

Abstract

The present invention discloses a router for realizing continuous single-cycle multi-hop traversal in a network-on-chip, which is applied to a two-dimensional mesh structure composed of n×n basic routers; and an asynchronous repeater is embedded in the crossbar switch of each basic router. Among them, the control path module is composed of a dedicated repeat line unit and a global switch allocation unit; a continuous single-cycle multi-hop traversal module and a power gating module are also provided in the basic router; the continuous single-cycle multi-hop traversal module enables data packets to continuously traverse multiple routers in a single cycle. Under the condition of low load, the power gating module turns off some components such as the buffer and crossbar switch of the router, effectively reducing the static power consumption of the network. The present invention efficiently completes the power gating of the network-on-chip router with a small hardware overhead and power consumption overhead, thereby effectively improving the network performance.

Description

Technical Field

[0001] The present invention belongs to the application technical field of integrated circuit chip design, and specifically relates to a router and a power gating method for realizing continuous single-cycle multi-hop traversal in a network-on-chip. Background Art

[0002] The network-on-chip is a new communication method for the system-on-chip, which has the characteristics of low latency, high scalability, high reliability, etc. However, applying the network-on-chip on a multi-core system will consume a lot of power, and as the transistor size is further scaled down, the proportion of static power consumption in the total power consumption of the network-on-chip will continue to increase. Research shows that when the transistor feature size is reduced to 10 nm, the static power consumption will become the main part of the NoC total power consumption.

[0003] The power gating technology is an effective method to reduce the static power consumption of the network-on-chip by turning off the idle circuit blocks of the router. However, the traditional power gating method generally has the following two problems: the first is the wake-up delay, and there is an obvious wake-up delay (generally 6 to 12 cycles) to charge the powered-off router to the fully active state; the second is the break-even time (BET). The power gating process will generate additional energy overhead. The powered-off power gating circuit block needs to maintain a certain number of cycles before being woken up. The energy overhead saved in this minimum number of cycles should at least compensate for the energy overhead generated by the power gating technology. Generally, BET is used to describe this minimum number of clock cycles. This means that frequent power gating or short-term power gating may not only not reduce the power consumption but may even increase it.

[0004] Many methods attempt to overcome the above-mentioned disadvantages of power gating in different aspects, such as extending the router sleep time. A common method to extend the router sleep time is the bypass technology. For example, NoRD provides a bypass ring network to bypass the powered-off router. When the router is powered off, there is no need to wake up the router. Only need to bypass the powered-off router along this virtual ring. However, the delay of this ring topology is very large, making the scalability of this technology very low, and the data packet may need to bypass many routers to reach the destination.

[0005] And in the existing bypass-based methods, only a single-hop router can be traversed in multiple cycles, and the delay of the data packet in the network is affected, reducing the performance while reducing the power consumption. Summary of the Invention

[0006] The present invention is to solve the above-mentioned deficiencies existing in the prior art, and proposes a router for realizing continuous single-cycle multi-hop traversal in a network-on-chip, in order to efficiently complete the power gating of the network-on-chip router with relatively small hardware overhead and power consumption overhead, so that the data packet can continuously traverse multiple routers in a single cycle, thereby greatly improving the performance of the network.

[0007] To achieve the above object, the present invention adopts the following technical solutions:

[0008] A router for realizing continuous single - cycle multi - hop traversal in a network - on - chip of the present invention is applied to a two - dimensional mesh structure, and the two - dimensional mesh is composed of n×n basic routers; the basic router is composed of an input port, an output port, an input buffer unit, a routing calculation unit, a virtual channel allocation unit, a switch allocation unit, a cross - bar switch, a control path module, and a data path module; and an asynchronous repeater is embedded in the cross - bar switch of each basic router. Among them, the control path module is composed of a dedicated repeat line unit and a global switch allocation unit; its characteristics are: a continuous single - cycle multi - hop traversal module and a power gating module are also provided in the basic router;

[0009] The basic router that sends a data packet is denoted as the source router, and the basic router that the data packet finally reaches is denoted as the destination router; if the source router and the destination router are in the same dimension in the two - dimensional mesh structure, the logical distance between them is the actual physical distance; if the source router and the destination router are not in the same dimension, when the data packet of the source router is sent in the X direction, the logical distance value is the difference in X - direction coordinates; when the data packet of the source router is sent in the Y direction, the logical distance value is the difference in Y - direction coordinates;

[0010] The nearest neighbor router obtained by the data packet according to the XY routing algorithm is called the X - neighbor, and the nearest neighbor router obtained by the data packet according to the YX routing algorithm is called the Y - neighbor;

[0011] Let the power states of the basic router be divided into an idle state, a sleep state, and an on state;

[0012] The escape subnet means that the power states of the routers in the last column of the two - dimensional mesh structure are always kept in the on state;

[0013] The router transmits data packets according to the following steps:

[0014] Step 1: The routing calculation unit of the source router i determines whether the source router and the destination router are in the same dimension according to the destination router address. If they are, go to Step 2; otherwise, go to Step 5;

[0015] Step 2: The routing calculation unit of the source router i determines the logical distance between the source router i and the destination router. If the logical distance is less than or equal to the maximum number of hops HPCmax that can be jumped within a single cycle, go to Step 3; otherwise, go to Step 4;

[0016] Step 3: The routing calculation unit of the source router i calculates the output port according to the position of the destination router. The asynchronous repeater of the source router i drives multiple hops within a single cycle, enabling the data packet to reach a position in the same row or the same column as the destination router from the output port, and then enters Step 10;

[0017] Step 4: The asynchronous repeater of the source router i drives multiple hops within the first HPCmax hops, enabling the data packet to reach the last router of the single-cycle multiple hops. The continuous single-cycle multiple-hop traversal module of the last router of the single-cycle multiple hops drives the remaining hops, enabling the data packet to continue to be transmitted towards the destination router, and then enters Step 10;

[0018] Step 5: The power gating module of the source router i queries whether its Y neighbor is in the sleep state. If so, it enters Step 6; otherwise, it enters Step 8;

[0019] Step 6: The power gating module of the source router i queries whether its X neighbor is in the sleep state. If so, it enters Step 7; otherwise, it enters Step 9;

[0020] Step 7: The data packet of the source router i is routed towards the escape subnet and is forwarded by the routers in the last column of the escape subnet until it reaches the destination router;

[0021] Step 15: The data packet of the source router i is forwarded to the Y neighbor router and enters Step 2;

[0022] Step 18: The data packet of the source router i is forwarded to the X neighbor router and enters Step 2;

[0023] Step 21: Determine whether the data packet has reached the destination router. If it has reached the destination router, the transmission ends; otherwise, it returns and enters Step 2.

[0024] The characteristics of the router that realizes continuous single-cycle multiple-hop traversal in the network-on-chip described in the present invention also lie in that: the continuous single-cycle multiple-hop traversal module includes a bypass control unit and a conflict resolution unit; wherein, the bypass control unit consists of a demultiplexer SpecD, a multiplexer SpecM, and an input port latch; the conflict resolution unit consists of a multiplexer SSRmux;

[0025] Assume that the maximum number of hops of the single-cycle multiple hops is 2 hops. The continuous single-cycle multiple-hop traversal module drives multiple hops according to the following process:

[0026] In the first cycle, the source router i receives the data packet and buffers it in the input buffer unit. The routing calculation unit of the source router i calculates the output port of its own router. Then, the virtual channel allocation unit arbitrates the input ports of the downstream router i+1. Next, the switch allocation unit of the source router i requests the output port of its own router. Finally, the asynchronous repeater of the source router i starts to prepare to send a single-cycle multi-hop request signal, that is, the SSR signal;

[0027] In the second cycle, after the source router i successfully requests the output port of its own router and the input port of the downstream router i+1 is successfully requested, the asynchronous repeater of the source router i sends the SSR signal and broadcasts it to each basic router within the single-cycle multi-hop through the dedicated repeater unit, that is, broadcasts to the downstream router i+1 and the downstream router i+2;

[0028] For the downstream routers i+1 and i+2: First, the global switch allocation units of the two downstream routers send all the received SSR signals to their own conflict resolution units for arbitration to obtain the arbitration result. Assume that the arbitration result is that the SSR signal sent by the source router i wins the arbitration on both downstream routers; the data path modules of the two downstream routers set up dedicated paths from the source router i to their own routers;

[0029] The routing calculation unit of the downstream router i+2 calculates the destination information of the data packet and prepares to generate a speculative SSR signal using its own global switch allocation unit in the next cycle;

[0030] In the third cycle, the data packet directly reaches the input port latch of the downstream router i+2 through the dedicated path set by the data path module from the source router i via the downstream router i+1;

[0031] For the downstream router i+2: First, the global switch allocation unit of the downstream router i+2 generates a speculative SSR signal and sends the generated speculative SSR signal and the SSR signals received from other routers to its own conflict resolution unit for arbitration. Assume that the arbitration result is that the speculative SSR signal wins the arbitration; second, the speculative SSR signal of the downstream router i+2 is broadcast to each basic router in the next single-cycle multi-hop through the dedicated repeater unit, that is, the downstream router i+3 and the downstream router i+4;

[0032] For downstream routers i+3 and i+4: The conflict resolution units of the two downstream routers arbitrate all the received speculative SSR signals. Assuming that the arbitration result is that the speculative SSR signal sent by downstream router i+2 wins the arbitration, the data path modules of the two downstream routers use demultiplexer SpecD and multiplexer SpecM to construct dedicated paths from downstream router i+2 to downstream router i+3 and from downstream router i+3 to downstream router i+4;

[0033] In the fourth cycle: The data packet directly latches from the input port latch of downstream router i+2, and successively passes through the dedicated path constructed from downstream router i+2 to downstream router i+3 and the dedicated path constructed from downstream router i+3 to downstream router i+4, until finally reaching the destination router.

[0034] The power gating module includes a power gating controller and a power status register; wherein, the power status register is used to store the power status of its adjacent router;

[0035] The power gating module of the nearest neighbor router of source router i determines the power status of its own router according to the following process, and sends the power status of its own router to the power status register of source router i, so that the source router i can query the power status of its X neighbor or Y neighbor through the power status register of its own router;

[0036] When there are no remaining data packets in the input buffer unit of the nearest neighbor router and no upstream router sends a WU signal to the nearest neighbor router, it means that the nearest neighbor router enters the idle state;

[0037] In the idle state, the nearest neighbor router uses the power gating controller to send a PG signal to all upstream routers; then wait for several idle cycles. If no router sends a WU signal to the nearest neighbor router within several idle cycles, the power gating controller cuts off the power of the nearest neighbor router, so that all the input buffer units of the nearest neighbor router are closed, and the crossbar directly connects the input port and the output port in the same dimension, indicating that the nearest neighbor router enters the sleep state; if a WU signal is detected within several idle cycles, the nearest neighbor router immediately cancels the PG signal sent to other routers, indicating that the nearest neighbor router is still in the idle state:

[0038] When the total number of SSR signals and speculative SSR signals received by the global switch allocation unit of the nearest neighbor router from other routers exceeds the specified threshold, the nearest neighbor router is woken up, and after the wake-up delay time, the nearest neighbor router enters the on state.

[0039] The conflict resolution unit arbitrates according to the following process:

[0040] If a conflict occurs between multiple SSR signals, that is, the SSR signal with the shortest distance to the current router wins the arbitration;

[0041] If a conflict occurs between an SSR signal and a speculated SSR signal, the SSR signal wins the arbitration, and the multiplexer SSRmux discards the speculated SSR signal;

[0042] If a conflict occurs between multiple speculated SSR signals, the speculated SSR signal closest to the destination router wins the arbitration.

[0043] Compared with the prior art, the beneficial effects of the present invention are as follows:

[0044] 1. The power gating module of the present invention can turn off components such as the buffer and crossbar switch of the router under low load conditions to ensure the connectivity of the router in the network. At the same time, it also uses the idle time of the router to reduce the static power consumption of the network, thereby effectively improving the network performance.

[0045] 2. The present invention is based on single-cycle multi-hop traversal of the network, so that even if some components in the router are turned off, data packets can still traverse multiple-hop routers within a single cycle, thereby greatly reducing the latency of network data packets; at the same time, through the continuous single-cycle multi-hop traversal module, data packets can continuously traverse multiple routers within a single cycle. Even when the data packet reaches the last router of the multi-hop path, it does not need to be buffered and can directly enter the next multi-hop traversal stage, further reducing the latency of network data packets.

[0046] 3. The power gating method designed by the present invention can achieve continuous single-cycle multi-hop traversal in a one-dimensional mesh regardless of whether the bypassed router is power-gated. In a two-dimensional mesh, by introducing an escape subnet, flexible transmission of data packets is achieved. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 is the router architecture diagram for implementing continuous single-cycle multi-hop traversal in the present invention;

[0048] Figure 2a is a partial multi-hop flow chart driven by the continuous single-cycle multi-hop traversal module in the present invention;

[0049] Figure 2b is the remaining multi-hop flow chart driven by the continuous single-cycle multi-hop traversal module in the present invention;

[0050] Figure 3 is an example diagram of the power gating scheme in the present invention. DETAILED DESCRIPTION OF THE INVENTION

[0051] In this embodiment, a router that realizes continuous single-cycle multi-hop traversal in a network-on-chip is applied to a two-dimensional mesh structure, which is composed of n×n basic routers. Among them, the basic router is composed of an input port, an output port, an input buffer unit, a routing calculation unit RC, a virtual channel allocation unit VA, a switch allocation unit SA, a crossbar switch, a control path module, and a data path module; the control path module is composed of a dedicated repeating line unit and a global switch allocation unit SA-G;

[0052] Among them, the router architecture that realizes continuous single-cycle multi-hop traversal is as Figure 1 shown, and it is composed of adding a continuous single-cycle multi-hop traversal module and a power gating module to the basic router; the added continuous single-cycle multi-hop traversal module includes a bypass control unit and a conflict resolution unit; among them, the bypass control unit is composed of a demultiplexer SpecD, a multiplexer SpecM, and an input port latch; the conflict resolution unit is composed of a multiplexer SSRmux; the added power gating module includes a power gating controller Ctrlr and a power status register; when the router is power-gated, the buffer of the router in this embodiment is all closed, and the crossbar switch of the power-gated router in this embodiment is not allocated by an arbiter, but the input port and the output port on the same dimension are fixedly connected. For other routers in the network, the power-gated router is two data links, one vertical and one horizontal.

[0053] The basic router that sends the data packet is denoted as the source router, and the basic router where the data packet finally arrives is denoted as the destination router;

[0054] As Figure 2a shown is the multi-hop flow chart driven by the continuous single-cycle multi-hop traversal module:

[0055] Here, it is assumed that the maximum number of hops for single-cycle multi-hop is 2 hops;

[0056] In the first cycle, the source router i receives the data packet and buffers it in the input buffer unit. The routing calculation unit of the source router i calculates the output port of its own router. Then, the virtual channel allocation unit arbitrates the input port of the downstream router i+1. Next, the switch allocation unit of the source router i requests the output port of its own router. Finally, the asynchronous repeater of the source router i starts to prepare to send a single-cycle multi-hop request signal, that is, the SSR signal;

[0057] In the second cycle, after the source router i successfully requests the output port of its own router and the input port of the downstream router i + 1 is successfully requested, the asynchronous repeater of the source router i sends an SSR signal and broadcasts it through the dedicated repeater unit to each base router within a single-cycle multi-hop, that is, it broadcasts to the downstream router i + 1 and the downstream router i + 2;

[0058] For the downstream routers i + 1 and i + 2: First, the global switch allocation units of the two downstream routers send all the received SSR signals to their own conflict resolution units for arbitration to obtain the arbitration result. Assume that the arbitration result is that the SSR signal sent by the source router i wins the arbitration on both downstream routers; the data path modules of the two downstream routers set up a dedicated path from the source router i to their own routers;

[0059] The routing calculation unit of the downstream router i + 2 calculates the destination information of the data packet and prepares to generate a speculative SSR signal using its own global switch allocation unit in the next cycle;

[0060] As Figure 2b shown in the flowchart of the continuous single-cycle multi-hop traversal module driving the remaining multi-hops:

[0061] In the third cycle, the data packet directly reaches the input port latch of the downstream router i + 2 from the source router i through the dedicated path set by the data path module, passing through the downstream router i + 1;

[0062] For the downstream router i + 2: First, the global switch allocation unit of the downstream router i + 2 generates a speculative SSR signal and sends the generated speculative SSR signal and the SSR signals received from other routers to its own conflict resolution unit for arbitration. Assume that the arbitration result is that the speculative SSR signal wins the arbitration; secondly, the speculative SSR signal of the downstream router i + 2 is broadcast through the dedicated repeater unit to each base router within the next single-cycle multi-hop, that is, the downstream router i + 3 and the downstream router i + 4;

[0063] For the downstream routers i + 3 and i + 4: The conflict resolution units of the two downstream routers arbitrate all the received speculative SSR signals. Assume that the obtained arbitration result is that the speculative SSR signal sent by the downstream router i + 2 wins the arbitration. The data path modules of the two downstream routers use the demultiplexer SpecD and the multiplexer SpecM to construct dedicated paths from the downstream router i + 2 to the downstream router i + 3 and from the downstream router i + 3 to the downstream router i + 4;

[0064] In the fourth cycle: The data packet is directly latched from the input port latch of the downstream router i + 2, and then sequentially passes through the dedicated path constructed from the downstream router i + 2 to the downstream router i + 3, and the dedicated path from the downstream router i + 3 to the downstream router i + 4, until it finally reaches the destination router.

[0065] The power gating module includes a power gating controller and a power status register; among them, the power status register is used to store the power status of its adjacent router.

[0066] The power gating module of the nearest neighbor router of the source router i determines the power status of its own router according to the following process, and sends the power status of its own router to the power status register of the source router i, so that the source router i can query the power status of its X neighbor or Y neighbor through the power status register of its own router.

[0067] When there are no remaining data packets in the input buffer unit of the nearest neighbor router and no upstream router sends a WU signal to the nearest neighbor router, it means that the nearest neighbor router enters the idle state.

[0068] In the idle state, the nearest neighbor router uses the power gating controller to send a PG signal to all upstream routers; then wait for several idle cycles. If no router sends a WU signal to the nearest neighbor router within several idle cycles, the power gating controller cuts off the power of the nearest neighbor router, so that all the input buffer units of the nearest neighbor router are closed, and the crossbar directly connects the input port and the output port in the same dimension, indicating that the nearest neighbor router enters the sleep state; if a WU signal is detected within several idle cycles, the nearest neighbor router immediately cancels the PG signal sent to other routers, indicating that the nearest neighbor router is still in the idle state.

[0069] When the total number of SSR signals and speculative SSR signals received by the global switch allocation unit of the nearest neighbor router from other routers exceeds the specified threshold, the nearest neighbor router is woken up, and after the wake-up delay time, the nearest neighbor router enters the on state.

[0070] If the source router and the destination router are in the same dimension in the two-dimensional mesh structure, the logical distance between them is the actual physical distance; if the source router and the destination router are not in the same dimension, when the data packet of the source router is sent in the X direction, the logical distance value is the difference in the X direction coordinates; when the data packet of the source router is sent in the Y direction, the logical distance value is the difference in the Y direction coordinates.

[0071] The nearest neighbor router obtained by the data packet according to the XY routing algorithm is called the X neighbor, and the nearest neighbor router obtained by the data packet according to the YX routing algorithm is called the Y neighbor.

[0072] An escape subnet means keeping the power state of the routers in the last column of a two-dimensional mesh structure always on.

[0073] In specific implementation, the router transmits data packets according to the following steps:

[0074] Step 1: The routing calculation unit of the source router i determines whether the source router and the destination router are in the same dimension according to the destination router address. If so, go to Step 2; otherwise, go to Step 5.

[0075] Step 2: The routing calculation unit of the source router i determines the logical distance between the source router i and the destination router. If the logical distance is less than or equal to the maximum number of hops HPCmax that can be skipped within a single cycle, go to Step 3; otherwise, go to Step 4.

[0076] Step 3: The routing calculation unit of the source router i calculates the output port according to the position of the destination router. The asynchronous repeater of the source router i drives multiple hops within a single cycle, so that the data packet reaches the position in the same row or the same column as the destination router from the output port, and go to Step 10.

[0077] Step 4: The asynchronous repeater of the source router i drives multiple hops within the first HPCmax hops, so that the data packet reaches the last router of the single-cycle multi-hop. The continuous single-cycle multi-hop traversal module of the last router of the single-cycle multi-hop drives the remaining hops, so that the data packet continues to be transmitted to the destination router, and go to Step 10.

[0078] Step 5: The power gating module of the source router i determines whether its Y neighbor is in the sleep state. If so, go to Step 6; otherwise, go to Step 8.

[0079] Step 6: The power gating module of the source router i determines whether its X neighbor is in the sleep state. If so, go to Step 7; otherwise, go to Step 9.

[0080] Step 7: The data packet of the source router i is routed into the escape subnet and is forwarded by the routers in the last column of the escape subnet until it reaches the destination router.

[0081] Step 8: The data packet of the source router i is forwarded to the Y neighbor router, and go to Step 2.

[0082] Step 9: The data packet of the source router i is forwarded to the X neighbor router, and go to Step 2.

[0083] Step 10: Determine whether the data packet reaches the destination router. If it reaches the destination router, the transmission ends; otherwise, return to Step 2.

[0084] As Figure 3 shown is an example of the power gating scheme in this embodiment. The packet routing process will be described in detail through this example. Here, SRC represents the source router, DST represents the destination router, light gray represents the routers that are power gated, and the gray on the far right represents the routers of the escape subnet that are always turned on.

[0085] In Figure 3 part (A), the source router and the destination router are in the same dimension. Even if the intermediate router is power gated, the packet can be transmitted to the destination router through single - cycle multi - hop bypass.

[0086] In Figure 3 part (B), the source router 20 and the destination router 02 are not in the same dimension. First, based on the YX routing algorithm, it is found that its direct Y neighbor (router 10) is in the off state. Then, based on the XY routing algorithm, its direct X neighbor, router 21, is found to be in the on state, and the packet is forwarded through the XY routing algorithm.

[0087] In Figure 3 part (C), the source router 20 and the destination router 02 are not in the same dimension. First, based on the YX routing algorithm, its direct Y neighbor (router 10) is found, and it is found that router 10 is in the on state, so the packet is directly forwarded through the YX routing algorithm.

[0088] In Figure 3 part (D), the source router 20 and the destination router 02 are not in the same dimension. Based on the YX and XY routing algorithms, it is found that both its direct Y neighbor 10 and direct X neighbor 21 are in the power - gated state. At this time, because the power states of other routers cannot be known, it will enter the escape subnet in the far east, send the packet to router 23, then router 23 sends the packet to router 04, the packet makes a turn at router 04, and finally is sent to the destination router 02.

[0089] In summary, the continuous single - cycle multi - hop traversal module of the present invention enables the packet to continuously traverse multiple routers in a single cycle. Even when the packet reaches the last router of the multi - hop, it does not have to be forced to buffer and can still continue the next multi - hop traversal. In the case of low load, the power gating module turns off some components such as the buffer and cross - switch of the router, effectively reducing the static power consumption of the network. Experiments show that the present implementation method uses less hardware overhead and power consumption overhead, efficiently completes the power gating of the on - chip network router, and effectively improves the network performance.

Claims

1. A router for realizing continuous single - cycle multi - hop traversal in a network - on - chip, which is applied to a two - dimensional mesh structure. The two - dimensional mesh is composed of n×n basic routers; the basic router is composed of an input port, an output port, an input buffer unit, a routing calculation unit, a virtual channel allocation unit, a switch allocation unit, a cross - switch, a control path module and a data path module; and an asynchronous repeater is embedded in the cross - switch of each basic router. Among them, the control path module is composed of a dedicated repeat line unit and a global switch allocation unit; its characteristics are: a continuous single - cycle multi - hop traversal module and a power gating module are also set in the basic router. The basic router that sends the data packet is denoted as the source router, and the basic router that the data packet finally reaches is denoted as the destination router; if the source router and the destination router are in the same dimension in the two - dimensional mesh structure, then the logical distance between them is the actual physical distance; if the source router and the destination router are not in the same dimension, then when the data packet of the source router is sent in the X direction, the logical distance value is the difference in the X - direction coordinates; when the data packet of the source router is sent in the Y direction, the logical distance value is the difference in the Y - direction coordinates. The nearest neighbor router obtained by the data packet according to the XY routing algorithm is called the X - neighbor, and the nearest neighbor router obtained by the data packet according to the YX routing algorithm is called the Y - neighbor. Let the power state of the basic router be divided into an idle state, a sleep state, and an on state. The escape subnet means that the power state of the routers in the last column of the two - dimensional mesh structure is always kept in the on state. The router transmits data packets according to the following steps: Step 1: The routing calculation unit of the source router i judges whether the source router and the destination router are in the same dimension according to the destination router address. If they are, go to Step 2; otherwise, go to Step 5. Step 2: The routing calculation unit of the source router i judges the logical distance between the source router i and the destination router. If the logical distance is less than or equal to the maximum number of hops HPCmax that can be jumped within a single cycle, go to Step 3; otherwise, go to Step 4. Step 3: The routing calculation unit of the source router i calculates the output port according to the position of the destination router. The asynchronous repeater of the source router i drives multi - hops within a single cycle, so that the data packet reaches the position in the same row or the same column as the destination router, and go to Step 10. Step 4: The asynchronous repeater of the source router i drives multi - hops within the first HPCmax hops, so that the data packet reaches the last router of the single - cycle multi - hop. The continuous single - cycle multi - hop traversal module of the last router of the single - cycle multi - hop drives the remaining hops, so that the data packet continues to be transmitted to the destination router, and go to Step 10. Step 5: The power gating module of the source router i queries whether its Y - neighbor is in the sleep state. If it is, go to Step 6; otherwise, go to Step 8. Step 6: The power gating module of the source router i queries whether its X - neighbor is in the sleep state. If it is, go to Step 7; otherwise, go to Step 9. Step 7: The data packet of the source router i is routed towards the escape subnet and forwarded by the last column of routers in the escape subnet until it reaches the destination router; Step 8: The data packet of the source router i is forwarded to the Y neighbor router, and step 2 is entered; Step 9: The data packet of the source router i is forwarded to the X neighbor router, and step 2 is entered; Step 10: Determine whether the data packet has reached the destination router. If it has reached the destination router, the transmission ends; otherwise, return to step 2.

2. The router for realizing continuous single-cycle multi-hop traversal in the network-on-chip according to claim 1, characterized in that: The continuous single-cycle multi-hop traversal module includes a bypass control unit and a conflict resolution unit; wherein, the bypass control unit consists of a demultiplexer SpecD, a multiplexer SpecM, and an input port latch; the conflict resolution unit consists of a multiplexer SSRmux; Assume that the maximum number of hops for single-cycle multi-hop is 2 hops. The continuous single-cycle multi-hop traversal module drives multi-hop according to the following process: In the first cycle, the source router i receives the data packet and buffers it in the input buffer unit. The routing calculation unit of the source router i calculates the output port of its own router. Then, the virtual channel allocation unit arbitrates the input ports of the downstream router i + 1. Next, the switch allocation unit of the source router i requests the output port of its own router. Finally, the asynchronous repeater of the source router i starts to prepare to send a single-cycle multi-hop request signal, that is, the SSR signal; In the second cycle, after the source router i successfully requests the output port of its own router and the input port of the downstream router i + 1 is successfully requested, the asynchronous repeater of the source router i sends the SSR signal and broadcasts it to each basic router within the single-cycle multi-hop through the dedicated repeat line unit, that is, broadcasts to the downstream router i + 1 and the downstream router i + 2; For the downstream routers i + 1 and i + 2: First, the global switch allocation units of the two downstream routers send all the received SSR signals to their own conflict resolution units for arbitration to obtain the arbitration result. Assume that the arbitration result is that the SSR signal sent by the source router i wins the arbitration on both downstream routers; the data path modules of the two downstream routers set up a dedicated path from the source router i to their own routers; The routing calculation unit of the downstream router i + 2 calculates the destination information of the data packet and prepares to generate a speculative SSR signal using its own global switch allocation unit in the next cycle; In the third cycle, the data packet directly reaches the input port latch of the downstream router i + 2 from the source router i through the downstream router i + 1 via the dedicated path set by the data path module; For the downstream router i + 2: First, the global switch allocation unit of the downstream router i + 2 generates a speculative SSR signal, and sends the generated speculative SSR signal and the SSR signals of other routers received to its own conflict resolution unit for arbitration. Assume that the arbitration result is that the speculative SSR signal wins the arbitration; Second, the speculative SSR signal of the downstream router i + 2 is broadcast to each base router within the next single-cycle multi-hop through the dedicated repeater unit, that is, the downstream routers i + 3 and i + 4. For the downstream routers i + 3 and i + 4: The conflict resolution units of the two downstream routers arbitrate all the received speculative SSR signals. Assume that the arbitration result obtained is that the speculative SSR signal sent by the downstream router i + 2 wins the arbitration. The data path modules of the two downstream routers use the demultiplexer SpecD and the multiplexer SpecM to construct dedicated paths from the downstream router i + 2 to the downstream router i + 3 and from the downstream router i + 3 to the downstream router i + 4. In the fourth cycle: The data packet directly latches from the input port latch of the downstream router i + 2, and successively passes through the dedicated path constructed from the downstream router i + 2 to the downstream router i + 3 and the dedicated path from the downstream router i + 3 to the downstream router i + 4, until finally reaching the destination router.

3. The router for realizing continuous single-cycle multi-hop traversal in the network-on-chip according to claim 1, characterized in that: The power gating module includes a power gating controller and a power status register; wherein, the power status register is used to store the power status of its adjacent routers; The power gating module of the nearest neighbor router of the source router i judges the power status of its own router according to the following process, and sends the power status of its own router to the power status register of the source router i, so that the source router i queries the power status of its X neighbor or Y neighbor through the power status register of its own router; When there are no remaining data packets in the input buffer unit of the nearest neighbor router and no upstream router sends a WU signal to the nearest neighbor router, it means that the nearest neighbor router enters the idle state; In the idle state, the nearest neighbor router uses the power gating controller to send a PG signal to all upstream routers; then wait for several idle cycles. If no router sends a WU signal to the nearest neighbor router within several idle cycles, the power gating controller cuts off the power of the nearest neighbor router, so that all the input buffer units of the nearest neighbor router are closed, and the crossbar directly connects the input port and the output port in the same dimension, indicating that the nearest neighbor router enters the sleep state; If a WU signal is detected within several idle cycles, the nearest neighbor router immediately cancels the PG signal sent to other routers, indicating that the nearest neighbor router is still in the idle state: When the global switch allocation unit of the nearest neighbor router receives that the total number of SSR signals and speculative SSR signals sent by other routers exceeds a specified threshold, it wakes up the nearest neighbor router, and after a wake-up delay time, the nearest neighbor router enters the on state.

4. The router for realizing continuous single-cycle multi-hop traversal in the network-on-chip according to claim 2, characterized in that: The conflict resolution unit arbitrates according to the following process: If a conflict occurs between multiple SSR signals, that is, the SSR signal with the shortest distance to the current router wins the arbitration; If a conflict occurs between an SSR signal and a speculative SSR signal, the SSR signal wins the arbitration, and the multiplexer SSRmux discards the speculative SSR signal; If a conflict occurs between multiple speculative SSR signals, the speculative SSR signal closest to the destination router wins the arbitration.

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