Image sensor and image sensing system

Abstract

The present invention discloses an image sensor and an image sensing system, wherein the image sensor includes a BJT pixel circuit, a bias circuit, and a comparator. The BJT pixel circuit includes a BJT; a charge selection circuit for controlling the charging of a first storage capacitor at a first reset time and controlling the charging of a second storage capacitor at a second reset time; a discharge selection circuit for causing the first storage capacitor to discharge through the BJT during a first exposure time to generate a first output voltage, and for causing the second storage capacitor to discharge through the BJT during a second exposure time to generate a second output voltage; a bias circuit for providing a voltage drop and a voltage boost to the second output voltage to generate an adjusted voltage; and a comparator for comparing the first output voltage with the adjusted voltage. The present invention can reduce memory size and simplify calculations.

Description

Technical Field

[0001] The present invention relates to an image sensor and an image sensing system, and more particularly to an image sensor and an image sensing system capable of detecting motion without storing the entire image. Background Art

[0002] With existing motion detection, each new image is compared to the previous one. If certain pixels show significant differences between the two images, a motion signal is triggered. For example, image T1 is the background of the environment. When an object passes through the image sensor's sensing area, the image sensor senses image T2. In this case, after comparing image T1 and image T2 (image T1 minus image T2), some pixels will reflect significant differences between the two images, thus concluding that motion has been detected.

[0003] However, in this operation, after the shutter is exposed, each pixel signal is processed by an amplifier, then digitized by an ADC (Analog to Digital Converter) and sent to the digital core for further processing. Furthermore, image T1 (the background image) is stored in memory. Therefore, if the pixel array size is 30x30 and the ADC is 8-bit, 900 bytes of memory are required to store image T1. Furthermore, the digital core accesses memory to obtain image T1 and then compares it with the new image T2. Therefore, a large amount of memory and complex calculations are required. Summary of the Invention

[0004] An object of the present invention is to disclose an image sensor that can reduce memory capacity and mobile computing complexity.

[0005] Another object of the present invention is to disclose an image sensing system that can reduce memory capacity and mobile computing complexity.

[0006] One embodiment of the present invention discloses an image sensor, characterized by including a BJT pixel circuit. The BJT pixel circuit includes: a photodiode; a BJT controlled by the photodiode; a first storage capacitor; a second storage capacitor; a charge selection circuit configured to charge the first storage capacitor to a first predetermined voltage level during a first reset time, and to charge the second storage capacitor to a second predetermined voltage level during a second reset time; a discharge selection circuit configured to discharge the first storage capacitor by the BJT to generate a first output voltage during a first exposure time, and to discharge the second storage capacitor by the BJT to generate a second output voltage during a second exposure time; and a read selection circuit configured to read the first and second output voltages during a second read time. The image sensor further includes a bias circuit configured to provide a voltage drop according to the second output voltage and the first detection voltage to generate a first adjusted voltage, and to provide a voltage boost according to the second output voltage and the second detection voltage to generate a second adjusted voltage; and a comparator configured to generate a first comparison result according to the first output voltage and the first adjusted voltage, and to generate a second comparison result according to the first output voltage and the second adjusted voltage.

[0007] Another embodiment of the present invention discloses an image sensing system, characterized by comprising: a light source and an image sensor. The image sensor includes a BJT pixel circuit. The BJT pixel circuit includes: a photodiode; a BJT controlled by the photodiode; a first storage capacitor; a second storage capacitor; a charging selection circuit configured to charge the first storage capacitor to a first predetermined voltage level during a first reset time, and to charge the second storage capacitor to a second predetermined voltage level during a second reset time; a discharging selection circuit configured to discharge the first storage capacitor by the BJT during a first exposure time to generate a first output voltage, and to discharge the second storage capacitor by the BJT during a second exposure time to generate a second output voltage; and a reading selection circuit configured to read the first output voltage and the second output voltage during a second reading time. The image sensor further includes: a bias circuit configured to provide a voltage drop based on the second output voltage and the first detection voltage to generate a first adjusted voltage, and to provide a voltage boost based on the second output voltage and the second detection voltage to generate a second adjusted voltage; a comparator configured to generate a first comparison result based on the first output voltage and the first adjusted voltage, and a second comparison result based on the first output voltage and the second adjusted voltage. The first comparison result and the second comparison result are used to determine whether motion has occurred; and the light source emits light during the first exposure time and the second exposure time.

[0008] According to the above embodiment, since it is not limited to storing the entire image and motion detection can be performed by comparing different image signals in pixels, the memory size can be reduced and the calculation can be simplified. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 FIG. 4 shows a block diagram of an image sensor according to an embodiment of the present invention.

[0010] Figure 2 Draws Figure 1 Detailed circuit of the BJT pixel circuit shown.

[0011] Figure 3 Draws Figure 2 The waveform diagram of the operation of the BJT pixel circuit shown.

[0012] Figure 4 Draws Figure 2 The detailed circuit of the bias circuit is shown in the circuit diagram.

[0013] Figure 5 Draws Figure 4 Schematic diagram of the operation of the bias circuit is shown.

[0014] Figure 6 FIG. 4 is a schematic diagram of an image sensing system according to an embodiment of the present invention.

[0015] The description of the accompanying drawings is as follows:

[0016] 100 Image Sensor

[0017] 101 BJT pixel circuit

[0018] 103 Bias Circuit

[0019] 105 Comparator

[0020] 107 Photodiode

[0021] 109 BJT

[0022] 111 Charging selection circuit

[0023] 113 Discharge selection circuit

[0024] 115 Read selection circuit

[0025] 117 Current supply circuit

[0026] 401 Counter

[0027] 600 Image Sensing System

[0028] 601 Image Sensor

[0029] C1 first storage capacitor

[0030] C2 Second storage capacitor

[0031] C_b1 first capacitor

[0032] C_b2 Second capacitor

[0033] CS_11, CS_12, CS_13, CS_21, CS_22 current sources

[0034] VDD power supply

[0035] SW_c1 First charging switch

[0036] SW_c2 Second charging switch

[0037] SW_d1 First discharge switch

[0038] SW_d2 Second discharge switch

[0039] SW_r1 First read switch

[0040] SW_r2 Second read switch

[0041] Vo1 first output voltage

[0042] Vo2 Second output voltage

[0043] RL1 first read line

[0044] RL2 Second read line

[0045] S_C1, S_D1, S_C2, S_D2, RD signals

[0046] SW switch

[0047] Cout output

[0048] Ob object

[0049] LS light source DETAILED DESCRIPTION

[0050] The present invention will be described below using multiple embodiments. Please note that the components in each embodiment may be implemented via hardware (e.g., a device or circuit) or firmware (e.g., at least one program written in a microprocessor). Furthermore, the terms "first," "second," and similar terms in the following description are used solely to define different components, parameters, data, signals, or steps. They are not intended to limit their order. For example, the first device and the second device may have the same structure but be different devices.

[0051] Figure 1 FIG. 1 shows a block diagram of an image sensor according to an embodiment of the present invention. Figure 1 As shown, image sensor 100 includes a BJT (bipolar transistor) pixel circuit 101, a bias circuit 103, and a comparator 105. The BJT pixel circuit includes a photodiode 107, a BJT 109, a charge selection circuit 111, a discharge selection circuit 113, a read selection circuit 115, a first storage capacitor C1, and a second storage capacitor C2. BJT 109 is controlled by photodiode 107. Charge selection circuit 111 is configured to charge first storage capacitor C1 to a first predetermined voltage level during a first reset time, and to charge second storage capacitor C1 to a second predetermined voltage level during a second reset time. Discharge selection circuit 113 is configured to control BJT 109 to discharge first storage capacitor C1 during a first exposure time to generate a first output voltage Vo1, and to control BJT 109 to discharge second storage capacitor C2 during a second exposure time to generate a second output voltage Vo2. The read selection circuit 115 is configured to output the first output voltage Vo1 during the first read time, and to output the first output voltage Vo1 and the second output voltage Vo2 during the second read time. Note that in one embodiment, the read selection circuit 115 outputs the first output voltage Vo1 and the second output voltage Vo2 during the second read time, but does not output the first output voltage Vo1 during the first read time.

[0052] In one embodiment, photodiode 107 is integrated into BJT 109, which is a PNP BJT. Photodiode 107 is integrated into a PN junction between the base and collector of BJT 109. BJT 109 is coupled to discharge selection circuit 113. In another embodiment, photodiode 107 has a cathode and an anode. The cathode is coupled to the emitter of BJT 109.

[0053] The bias circuit 103 receives the first output voltage Vo1 and the second output voltage Vo2 from the read selection circuit 115, and is configured to provide a voltage drop according to the second output voltage Vo2 and the first detection voltage Vd1 to generate a first adjusted voltage, and to provide a voltage boost according to the second output voltage Vo2 and the second detection voltage Vd2 to generate a second adjusted voltage Va2.

[0054] The comparator 105 is configured to generate a first comparison result based on the first output voltage Vo1 and the first adjusted voltage Va1, and to generate a second comparison result based on the first output voltage Vo1 and the second adjusted voltage Va2. Details of the bias circuit 103 and the comparator 105 will be described later.

[0055] In one embodiment, the second read time is after the first read time. In another embodiment, the first exposure time is after the first reset time, and the first read time is after the first exposure time. Additionally, in this embodiment, the second reset time is after the first read time, the second exposure time is after the second reset time, and the second read time is after the second exposure time.

[0056] In other words, the charge selection circuit 111 charges the first storage capacitor C1 to a first predetermined voltage level during the first reset time. The discharge selection circuit 113 then discharges the first storage capacitor C1 through the BJT 109 during the first exposure time to generate a first output voltage Vo1. The read selection circuit 115 then outputs the first output voltage Vo1 during the first read time. The charge selection circuit 111 then charges the second storage capacitor C2 to a second predetermined voltage level during the second reset time. The discharge selection circuit 113 then discharges the second storage capacitor C2 through the BJT 109 during the second exposure time to generate a second output voltage Vo2. The read selection circuit 115 then outputs the second output voltage Vo1 and the second output voltage Vo2 during the second read time.

[0057] Figure 2 Draws Figure 1 The detailed circuit of the BJT pixel circuit is shown. Also note that Figure 2 The embodiments in the drawings are only examples, and any circuit that can achieve the same function should also fall within the scope of the present invention. Figure 1 Some symbols in Figure 2 Shown in.

[0058] Figure 1 The charging selection circuit 111 includes Figure 2 In addition, the discharge selection circuit 113 includes a first charging switch SW_c1 and a second charging switch SW_c2. Figure 2 The first discharge switch SW_d1 and the second discharge switch SW_d2 are coupled in the embodiment of the present invention. The first charge switch SW_c1 is coupled between the first discharge switch SW_d1 and the first storage capacitor C1. The first charge switch SW_c1 is conductive during the first reset time and the first exposure time, and is non-conductive during the first read time. In addition, the second charge switch SW_c2 is coupled between the second discharge switch SW_d2 and the second storage capacitor C2. The second charge switch SW_c2 is conductive during the second reset time and the second exposure time, and is non-conductive during the second read time.

[0059] The read selection circuit 115 includes a first read switch SW_r1, a first source follower Sf1, a second read switch SW_r2, and a second source follower Sf2. The first read switch SW_r1 couples the first storage capacitor C1 and the first read line RL1. The first read switch SW_r1 is turned on during a first read time and a second read time. The first source follower Sf1 includes a gate coupled to the first storage capacitor C1, a source coupled to the first read line RL1 via the first read switch SW_r1, and a drain coupled to the power supply VDD. The second read switch SW_r2 couples the second storage capacitor C2 and the second read line RL2. The second read switch SW_r2 is turned on during the first read time and the second read time. The second source follower Sf2 includes a gate coupled to the second storage capacitor C2, a source coupled to the second read line RL2 via the second read switch SW_r2, and a drain coupled to the power supply VDD. Figure 2 The switches in the circuit can be implemented by transistors, such as PMOS or NMOS.

[0060] In one embodiment, Figure 1 The current providing circuit 117 includes Figure 2 Furthermore, in one embodiment, the read selection circuit 115 further includes current sources CS_21 and CS_22, but the present invention is not limited thereto.

[0061] Figure 3 Draws Figure 2 The waveform diagram of the operation of the BJT pixel circuit shown. Figure 3 Including signals S_C1, S_D1, S_C2, S_D2, RD, which control Figure 2 In addition, Figure 3 The relationship between the signals and the components controlled by the signals is shown in Table 1 below.

[0062] Figure 3 Signal in Figure 2 Components in S_C1 SW_c1 S_D1 SW_d1 S_C2 SW_c2 S_D2 SW_d2 RD SW_r1,SW_r2

[0063] Table 1

[0064] In one embodiment, Figure 2 The first charging switch SW_c1, the second charging switch SW_c2, the first discharging switch SW_d1 and the second discharging switch SW_d2 are PMOS with gates for receiving Figure 3 Therefore, when the corresponding signal has a low logic value, it is turned on, and when the corresponding signal has a high logic value, it is not turned on. In addition, Figure 2The first read switch SW_r1 and the second read switch SW_r2 in the embodiment are NMOS having gates that receive the signal RD and are thus turned on when the corresponding signal has a high logic value and are not turned on when the corresponding signal has a low logic value.

[0065] in addition, Figure 3 Reset 1, Shutter 1, Read Out 1, Reset 2, Shutter 2, and Read Out 2 represent the first reset time, the first exposure time, the first reading time, the second reset time, the second exposure time, and the second reading time, respectively.

[0066] During Reset 1, the first storage capacitor C1 is reset to a first predetermined voltage level. After Reset 1, the first discharge switch SW_d1 is turned on in Shutter 1, and BJT 109 discharges the first storage capacitor C1 until Shutter 1 is terminated (S_D1 = 1). Signal S_D1 is then set to a high logic value, storing the image signal (or light signal) captured in Shutter 1 in the first storage capacitor C1. More specifically, in Shutter 1, BJT 109 discharges the first predetermined voltage level, and the discharge rate is a function of the light intensity received by photodiode 107.

[0067] In addition, in Read out 1, the signal RD is set to a high logic value, and the first output voltage Vo1 is Figure 1 However, since the second storage capacitor C2 is still waiting for its image signal, its reading is skipped.

[0068] During Reset 2, the second storage capacitor C2 is reset to a second predetermined voltage level. After Reset 2, the second discharge switch SW_d2 is turned on in Shutter 2, and BJT 109 discharges the second storage capacitor C2 until Shutter 2 is discharged (S_D2 = 1). Signal S_C2 is then set to a high logic value to store the image signal obtained in Shutter 2 in the second storage capacitor C2, resulting in the first storage capacitor C1 and the second storage capacitor C1 having two image signals at different times.

[0069] As mentioned above, Figure 1The bias circuit 103 is configured to provide a step-down voltage based on the second output voltage Vo2 and the first detection voltage Vd1 to generate a first adjusted voltage Val, and to provide a step-up voltage based on the second output voltage Vo2 and the second detection voltage Vd2 to generate a second adjusted voltage Va2. The details of the bias circuit 103 according to one embodiment of the present invention are described below. In the following embodiment, the first detection voltage and the second detection voltage are the same detection voltage Vdec.

[0070] like Figure 4 As shown, bias circuit 103 includes a first capacitor C_b1 and a second capacitor C_b2. First capacitor C_b1 includes a first terminal for receiving first output voltage Vo1 and a second terminal for receiving reference voltage Vref. Second capacitor C_b2 includes a first terminal for receiving second output voltage Vo2 and a second terminal. The second terminal receives reference voltage Vref, a reference signal minus first detection voltage Vref-Vdec, and a reference signal plus second detection voltage Vref+Vdec at different times.

[0071] In this case, the bias circuit 103 biases the first output voltage with the reference voltage Vref to generate the first voltage Va0. In addition, the bias circuit 103 biases the second output voltage Vo2 with the reference voltage Vref to generate the second voltage at different times, reduces the second voltage by the first detection voltage Vdec to generate the first adjusted voltage Va1, and increases the second voltage by the second detection voltage Vdec to generate the second adjusted voltage Va2 at different times.

[0072] Figure 4 The bias circuit 103 further includes a comparator 105 and a counter 401, and Figure 5 Schematic diagram of the operation of the comparator 105 and the counter 401. As described above, the first storage capacitor C1 and the second storage capacitor C2 store image signals at different times, which can be used for but not limited to motion detection. Therefore, if an object passes through the sensing area of the image sensor, the second storage capacitor C2 will collect an image signal different from that of the first storage capacitor C1. Figure 4 As shown, the first output voltage Vo1 from the first storage capacitor C1 and the second output voltage Vo2 from the second storage capacitor C2 are transmitted to the comparator 105 through the turned-on switch SW (ie, turned on) to detect the difference. The switch SW can be integrated into Figure 1 The first output voltage Vo1 and the second output voltage Vo2 are biased by the bias voltage (reference voltage Vref) and stored on the other plates of the first capacitor C_b1 and the second capacitor C_b2.

[0073] After switch SW is closed (i.e., non-conducting), the bias voltage received by second capacitor Cb2 changes from Vref to Vref-Vdec and Vref+Vdec, respectively. If the output Cout of comparator 105 remains "0" or "1" when the bias voltage is Vref-Vdec or Vref+Vdec, it indicates that the second output voltage Vo2 is significantly different from the first output voltage Vo1. Therefore, the count of counter 401 is triggered to increase by 1.

[0074] exist Figure 5 In the example, the output of the comparator 105 has three sets of different image signals for three pixels. Each pixel has Figure 1 In the first pixel, the first output voltage Vo1 is brighter than the second output voltage Vo2, and the outputs Cout corresponding to Vref-Vdec and Vref+Vdec are both "11." This indicates that the second output voltage Vo2 is significantly different from the first output voltage Vo1.

[0075] In the second pixel, the second output voltage Vo2 is slightly brighter than the first output voltage Vo1, so the output Cout is "10." That is, the output Cout corresponding to Vref-Vdec is 1, and the output Cout corresponding to Vref+Vdec is 0. This means that the second output voltage Vo2 is not significantly different from the first output voltage Vo1.

[0076] In the third pixel, the second output voltage Vo2 is brighter than the first output voltage Vo1, and the outputs Cout corresponding to Vref-Vdec and Vref+Vdec are both "00". This means that the second output voltage Vo2 is significantly different from the first output voltage Vo1.

[0077] The counter 401 counts the total count of all pixels in the entire pixel array that have a significant difference between two consecutive images (i.e., the comparator output is "11" or "00"). Once the count exceeds a predetermined threshold, it means that motion is detected.

[0078] In summary, comparator 105 is configured to generate a first comparison result based on first output voltage Vo1 and first adjusted voltage Va1 (corresponding to Vref-Vdec), and to generate a second comparison result based on first output voltage Vo1 and second adjusted voltage Va2 (corresponding to Vref+Vdec). The first and second comparison results are used to determine whether motion exists.

[0079] Figure 5The voltages Vref-Vdec and Vref+Vdec shown can be adjusted. A lower detection voltage Vdec means that comparator 105 is more likely to change its output state, meaning it is more sensitive to motion detection, but there may be more motion detection noise. The threshold value representing the number of motion detected counters can also be adjusted. A lower detection voltage Vdec means more sensitive motion detection, but there may also be more motion detection noise. Therefore, the detection voltage Vdec and the threshold value can be optimized to ensure reliable system operation with less noise.

[0080] The image sensor can be applied to an image sensing system, such as an optical navigation device. Figure 6 FIG. 1 is a schematic diagram of an image sensing system according to an embodiment of the present invention. Figure 6 As shown, the image sensing system 600 of the optical navigation device in this embodiment includes a light source LS and an image sensor 601. The image sensor 601 includes a pixel array, and the pixel array includes a plurality of BJT pixel circuits. Each BJT pixel circuit includes Figure 1 In addition, the image sensor 601 further includes a bias circuit 103 corresponding to the BJT pixel circuit, a comparator 105 and a counter 401 .

[0081] The light source LS emits light outward toward the surface 603 of the image sensing system 600. Therefore, if an object Ob, such as a finger, moves on the surface 603, the image sensor 601 senses an image generated by the reflected light from the light source LS. In this case, there may be a difference between the image signals stored in the first storage capacitor C1 and the second storage capacitor C2, so that the movement of the object Ob can be detected. Please note that since the image signals stored in the first storage capacitor C1 and the second storage capacitor C2 are used to detect movement, the light source LS will emit light when the image signal of the first storage capacitor C1 is generated (i.e., the first exposure time), and the light source LS will also emit light when the image signal of the second storage capacitor C2 is generated (i.e., the second exposure time).

[0082] In one embodiment, when the image sensor 601 is in sleep mode, only the portion for detecting motion is activated, and when motion is detected, the entire image sensor 601 is awakened. Figure 6 The example shown. The image sensing system can be any other optical device, such as an optical mouse.

[0083] According to the above embodiment, since it is not limited to storing the entire image and motion detection can be performed by comparing different image signals in pixels, the memory size can be reduced and the calculation can be simplified.

[0084] The foregoing description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Those skilled in the art will readily appreciate that various modifications and variations of the present invention are possible. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention are intended to be within the scope of protection of the present invention.

Claims

1. An image sensor, characterized in that: include: BJT pixel circuit, including: Photodiode; BJT, controlled by the photodiode; a first storage capacitor; a second storage capacitor; a charging selection circuit configured to charge the first storage capacitor to a first predetermined voltage level during a first reset time, and to charge the second storage capacitor to a second predetermined voltage level during a second reset time; a discharge selection circuit configured to discharge the first storage capacitor by the BJT during a first exposure time to generate a first output voltage, and to discharge the second storage capacitor by the BJT during a second exposure time to generate a second output voltage; and a read selection circuit for reading the first output voltage and the second output voltage at a second read time; a bias circuit for providing a voltage drop according to the second output voltage and the first detection voltage to generate a first adjusted voltage, and for providing a voltage boost according to the second output voltage and the second detection voltage to generate a second adjusted voltage; and The comparator is configured to generate a first comparison result according to the first output voltage and the first adjusted voltage, and to generate a second comparison result according to the first output voltage and the second adjusted voltage.

2. The image sensor according to claim 1, wherein: The read selection circuit is used to read the first output voltage at a first read time. The second read time is after the first read time.

3. The image sensor according to claim 2, wherein: The first exposure time is after the first reset time, the first read time is after the first exposure time, the second reset time is after the first read time, the second exposure time is after the second reset time, and the second read time is after the second exposure time.

4. The image sensor according to claim 2, wherein: The charging selection circuit includes: a first charging switch coupled between the discharge selection circuit and the first storage capacitor, wherein the first charging switch is turned on during the first reset time and the first exposure time, and is turned off during the first reading time; The second charging switch is coupled between the discharge selection circuit and the second storage capacitor, wherein the second charging switch is turned on during the second reset time and the second exposure time, and is turned off during the second reading time.

5. The image sensor according to claim 4, wherein: The discharge selection circuit includes: A first discharge switch is coupled between the BJT and the first charge switch, wherein the first discharge switch is not turned on during the first reset time and the first read time, and is turned on during the first exposure time; and The second discharge switch is coupled between the BJT and the second charging switch, wherein the second charging switch is not turned on during the second reset time and the second reading time, and is turned on during the second exposure time.

6. The image sensor according to claim 2, wherein: The read selection circuit includes: The first read switch is coupled to the first storage capacitor and the first read line. The first read switch is turned on during the first read time and the second read time.

7. The image sensor according to claim 6, wherein: The read selection circuit further comprises: The first source follower includes a gate coupled to the first storage capacitor, a source coupled to the first read line through the first read switch, and a drain coupled to a power supply.

8. The image sensor according to claim 1, wherein: The first detection voltage is the same as the second detection voltage.

9. The image sensor according to claim 1, wherein: The bias circuit biases the first output voltage with a reference voltage to generate a first voltage, and the bias circuit biases the second output voltage with the reference voltage to generate a second voltage; The bias circuit reduces the second voltage by the first detection voltage to generate the first adjusted voltage, and increases the second voltage by the second detection voltage to generate the second adjusted voltage. The bias circuit biases the second output voltage at different times, lowers the first detection voltage and increases the second voltage.

10. The image sensor according to claim 9, wherein The bias circuit includes: A first capacitor comprising a first terminal receiving the first output voltage and a second terminal receiving the reference voltage; and The second capacitor includes a first end receiving the second output voltage and a second end, wherein the second end of the second capacitor receives the second output voltage, the reference voltage minus the first detection voltage, and the reference voltage plus the second detection voltage at different times.

11. An image sensing system, characterized in that: include: light source; Image sensors, including: BJT pixel circuit, including: Photodiode; BJT, controlled by the photodiode; a first storage capacitor; a second storage capacitor; a charging selection circuit configured to charge the first storage capacitor to a first predetermined voltage level during a first reset time, and to charge the second storage capacitor to a second predetermined voltage level during a second reset time; a discharge selection circuit configured to discharge the first storage capacitor by the BJT during a first exposure time to generate a first output voltage, and to discharge the second storage capacitor by the BJT during a second exposure time to generate a second output voltage; and a read selection circuit for reading the first output voltage and the second output voltage at a second read time; a bias circuit for providing a voltage drop according to the second output voltage and the first detection voltage to generate a first adjusted voltage, and for providing a voltage boost according to the second output voltage and the second detection voltage to generate a second adjusted voltage; and a comparator configured to generate a first comparison result based on the first output voltage and the first adjusted voltage, and to generate a second comparison result based on the first output voltage and the second adjusted voltage, wherein the first comparison result and the second comparison result are used to determine whether movement occurs; The light source emits light during the first exposure time and the second exposure time.

12. The image sensing system according to claim 11, wherein: The read selection circuit is used to read the first output voltage at a first read time. The second read time is after the first read time.

13. The image sensing system according to claim 12, wherein: The first exposure time is after the first reset time, the first read time is after the first exposure time, the second reset time is after the first read time, the second exposure time is after the second reset time, and the second read time is after the second exposure time.

14. The image sensing system according to claim 12, wherein: The charging selection circuit includes: a first charging switch coupled between the discharge selection circuit and the first storage capacitor, wherein the first charging switch is turned on during the first reset time and the first exposure time, and is turned off during the first reading time; The second charging switch is coupled between the discharge selection circuit and the second storage capacitor, wherein the second charging switch is turned on during the second reset time and the second exposure time, and is turned off during the second reading time.

15. The image sensing system according to claim 14, wherein: The discharge selection circuit includes: A first discharge switch is coupled between the BJT and the first charge switch, wherein the first discharge switch is not turned on during the first reset time and the first read time, and is turned on during the first exposure time; and The second discharge switch is coupled between the BJT and the second charging switch, wherein the second charging switch is not turned on during the second reset time and the second reading time, and is turned on during the second exposure time.

16. The image sensing system according to claim 12, wherein: The read selection circuit includes: The first read switch is coupled to the first storage capacitor and the first read line. The first read switch is turned on during the first read time and the second read time.

17. The image sensing system according to claim 16, wherein: The read selection circuit further comprises: The first source follower includes a gate coupled to the first storage capacitor, a source coupled to the first read line through the first read switch, and a drain coupled to a power supply.

18. The image sensing system according to claim 11, wherein: The first detection voltage is the same as the second detection voltage.

19. The image sensing system according to claim 11, wherein: The bias circuit biases the first output voltage with a reference voltage to generate a first voltage, and the bias circuit biases the second output voltage with the reference voltage to generate a second voltage; The bias circuit reduces the second voltage by the first detection voltage to generate the first adjusted voltage, and increases the second voltage by the second detection voltage to generate the second adjusted voltage. The bias circuit biases the second output voltage at different times, lowers the first detection voltage and increases the second voltage.

20. The image sensing system according to claim 19, wherein: The bias circuit includes: A first capacitor comprising a first terminal receiving the first output voltage and a second terminal receiving the reference voltage; and The second capacitor includes a first end receiving the second output voltage and a second end, wherein the second end of the second capacitor receives the second output voltage, the reference voltage minus the first detection voltage, and the reference voltage plus the second detection voltage at different times.

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