A 5G NR multi-bandwidth channel filter

Abstract

The application discloses a 5G NR multi-bandwidth channel filter, and belongs to the technical field of communication, which comprises a time-varying delay module, a coefficient storage and time division selection module and a polyphase filter structure. According to a current phase value, the polyphase filter structure selects a coefficient value of a current phase of a current time slot bandwidth stored in the coefficient storage and time division selection module. Meanwhile, the time-varying delay module selects different delay chain taps according to the current phase in different carrier bandwidth time slots, and performs time division convolution operation on the output coefficient value of the coefficient storage and time division selection module, so as to output a final result.

Description

Technical Field

[0001] This invention belongs to the field of communication technology, and specifically relates to a multi-bandwidth channel filter for 5G NR, which can flexibly adapt to various bandwidths of 5G, effectively reducing chip power consumption and area. Background Technology

[0002] In 5G wireless communication systems, carrier bandwidth is diverse, making carrier configuration extremely complex. Figure 1 The list outlines the carrier bandwidth types that NR needs to support. Compared to LTE, 5G NR carriers have higher spectral efficiency and narrower guard bands, typically requiring the design of 200-400 order pulse shaping channel filters. Simultaneously, with the increased bandwidth (FR2 can reach up to 400MHz), the clock frequency is higher than before, leading to significant resource and power consumption by the channel filters. However, excessive chip power consumption and logic resource usage must be avoided.

[0003] Current industry practice for filter multiplexing involves designing a separate channel filter for each bandwidth. For example, one filter can be reused for n 20MHz carriers, but this method is inadequate for four different bandwidths (e.g., 10MHz / 20MHz / 50MHz / 100MHz). Current designs require four channel filters to accommodate the four different bandwidths. Figure 2 This is the traditional multi-bandwidth filter design, which requires multiple different filters to adapt to different bandwidths and sampling rates. Summary of the Invention

[0004] To address the aforementioned issues, this invention designs a novel multi-bandwidth channel filter. Multiple carriers of different bandwidths pass through a single filter, and through time-division multiplexing, a single channel filter can simultaneously adapt to various bandwidths. Using this structure, only one multi-bandwidth filter is needed to support multiple carriers of different bandwidths simultaneously. This multi-bandwidth filter reduces the use of logic resources (DSP, LUT, Flip-flop, RAM), significantly saving chip power consumption and area.

[0005] The technical solution adopted in this invention is as follows: a 5G NR multi-bandwidth channel filter, including a time-varying delay module, a coefficient storage and time-division selection module, and a polyphase filter structure. The polyphase filter structure selects the coefficient values ​​of the current phase of the current time slot bandwidth stored in the coefficient storage and time-division selection module according to the current phase value. At the same time, the time-varying delay module selects different delay chain taps according to the current phase in different carrier bandwidth time slots, and performs time-division convolution operation with the output coefficient values ​​of the coefficient storage and time-division selection module to output the final result.

[0006] The time-varying delay module includes a time-varying delay chain. Using a more general example of a polyphase filter (a non-polyphase filter is a special case of a polyphase filter), the time-varying delay chain consists of a two-dimensional matrix, as follows:

[0007] The two-dimensional matrix has Q*R delay units, each delay unit having a delay of N clock cycles, where N equals... Where M is the number of phases in the polyphase filter, and M equals ⌈ ⌉, where I is the number of valid time slots occupied by the input data, and Fclk is the operating clock. The sampling rate is for the maximum bandwidth carrier. For polyphase filters, each column of the delay matrix contains the delay required for the minimum bandwidth adjacent order, and the unit column vector is formed by... Each column consists of M multi-phase sub-delay chains, and the number of delay units Q in each column is equal to... , The sampling rate is for the minimum bandwidth carrier. The number of columns R in the matrix represents the number of multipliers; depending on the asymmetry or symmetry of the coefficients, R equals ⌈ ⌉(Equation 5) or ⌈ ⌉, where L is the filter order.

[0008] The coefficients of the coefficient storage and time-division selection module are used for time-division convolution operations. These coefficients are time-varying and are stored in a two-dimensional array. Let h(i,j) be the j-th order coefficient of the i-th carrier. Then the corresponding coefficient storage array of the k-th multiplier is as follows:

[0009] The array is an M*I array, where M represents the number of phases and I represents the number of bandwidths. Each row of the array represents M different phases of a certain bandwidth; each column of the array represents the corresponding coefficients for different bandwidths. The time-varying order is column-first, then row-first: first traversing carriers of different bandwidths, then traversing coefficients of the same order for different phases.

[0010] The multiplier of the multiphase filter structure has two input terminals: a time-varying delay chain and a storage coefficient module. When the input data does not fill all time slots, i.e., Fclk is greater than... *I, Before the data stream enters the delay chain, valid serial data needs to be copied to the redundant time slot so that the multiplier's input MUX still selects Z at different phases. -N*M Delay the endpoints of the chain without selecting Z. -N*M The internal Z -N The nodes are used for time-division convolution; the data MUX is used to select data from different carriers and phases. The MUX selects data from different time intervals. Data is obtained from the delay taps (based on the carrier bandwidth, n=0,1,2,......) and sent to the multiplier. The system consists of two MUX stages: the first stage selects different phases, and the second stage selects different carriers. A feedback accumulator is located at the output of the polyphase filter structure to accumulate signals of different phases. The delay Z of the accumulator is... -I The effective number of time slots is the output d_out of the polyphase filter structure, which is the final result.

[0011] Compared with the prior art, the beneficial effects of the present invention are as follows: 1. One convolutional unit is required. The number of convolutional units in the existing parallel multi-bandwidth filter is P (where P is the number of bandwidth types).

[0012] 2. One delay chain is required. The number of delay chains for existing parallel multi-bandwidth filters is P (where P is the number of bandwidth types).

[0013] 3. One accumulator is required. The number of accumulators in the existing parallel multi-bandwidth filter is P (where P is the number of bandwidth types).

[0014] 4. Maintains the timing of input and output data, and has a highly user-friendly interface. Attached Figure Description

[0015] Figure 1 This diagram illustrates the 5G NR carrier configuration and bandwidth in existing technologies.

[0016] Figure 2 This is a schematic diagram of the design structure of a multi-bandwidth channel filter in the prior art.

[0017] Figure 3 This is a schematic diagram of the multi-bandwidth channel filter design structure of the present invention.

[0018] Figure 4 This is a timing diagram of the input interface of the 5G NR channel filter of the present invention.

[0019] Figure 5 This is a schematic diagram of the 5G NR 10M / 20M / 50M multi-bandwidth channel filter structure of the present invention.

[0020] Figure 6 This is a schematic diagram of the 5G NR 10M / 20M / 50M / 100M data time-varying delay tap of the present invention.

[0021] Figure 7 This is a schematic diagram of the 5G NR 10M / 20M / 50M multiphase multibandwidth channel filter structure of the present invention.

[0022] Figure 8 This is a timing diagram of the input interface of the 5G NR multichannel filter of the present invention.

[0023] Figure 9 This is a schematic diagram of the time-varying delay tap of the 5G NR 10M / 20M / 50M multiphase filter data of the present invention.

[0024] Figure 10 This is a schematic diagram of the circular traversal of the coefficients of the multiphase structure of the 5G NR coefficients of the present invention. Detailed Implementation

[0025] The technical solution of the present invention will be further explained through several specific embodiments below.

[0026] Different 5G NR bandwidths satisfy a 2^n proportional relationship in sampling rate. Low-bandwidth carriers have low sampling rates and occupy fewer time slot resources, making time-division multiplexing of channel filters possible. In traditional filter design, the delay between filter coefficients is constant. This filter design, based on carrier bandwidth and chip clock, employs a time-varying systolic delay chain matrix. Simultaneously, filter coefficients of different bandwidths are stored in an array unit according to carrier bandwidth and phase, allowing for flexible timing by the multiplier. Compared to multi-bandwidth filters with parallel structures: The required number of convolutional filters is 1 / P of the number of parallel multi-bandwidth filters (where P is the number of bandwidth types).

[0027] One delay chain is required, and the number of parallel multi-bandwidth filters is P.

[0028] One accumulator is required, and the number of parallel multi-bandwidth filters is P.

[0029] It maintains the timing of input and output data and has a highly user-friendly interface.

[0030] Inside the chip, a typical 5G NR multi-carrier serial data timing sequence is as follows: Figure 4 As shown, carriers of different bandwidths are interleaved on the serial data stream. In our example design, there are four different bandwidths: 10M / 20M / 50M / 100M, requiring only one multi-channel channel filter.

[0031] The expression formula for a typical FIR channel filter is shown in (1):

[0032] The 5G NR multi-bandwidth channel filter disclosed in this embodiment is designed with three serial time-division multiplexing modules: (1) a time-varying delay module, (2) a coefficient storage and time-division selection module, and (3) a polyphase filter structure. The polyphase filter selects the coefficient values ​​of the current phase of the current time slot bandwidth stored in the coefficient storage module based on the current phase value. Simultaneously, the time-varying delay module selects different delay chain taps based on the current phase in different carrier bandwidth time slots and performs time-division convolution operations with the output coefficient values ​​of the storage module to output the final result. This embodiment describes the design of each module based on both non-polyphase and polyphase filters.

[0033] Design of a non-polyphase 5G multi-bandwidth channel filter. As an example... Figure 5 This paper describes the implementation structure of a 10M / 20M / 50M non-polyphase filter. As shown in the figure, the filter includes a delay chain with a time-varying delay structure, time-varying coefficient storage and time-division selection, and a time-division convolutional unit (multiplicative accumulator). The delay chain of the time-varying delay structure is... Figure 5 Z below -N The delay chain connected in series with the corresponding MUX multiplexing unit; the time-varying coefficient storage unit, i.e. Figure 5 The table entries on the left side of the multiplication table; the time-division convolutional unit is... Figure 5 The filter multiplication and accumulation structure is formed by cascading multipliers and adders. The two inputs of the filter multiplier are a time-varying delay chain and storage coefficients.

[0034] Design of the time-varying delay chain. Unlike the fixed delay chain of a single-bandwidth channel filter, the filter of this invention uses a time-varying delay chain, which is composed of a two-dimensional matrix, as described in equation (2). The two-dimensional matrix has Q*R delay units, and each delay unit has a delay of N clock cycles. N equals (Equation 3), where Fclk is the operating clock. The sampling rate is the maximum bandwidth carrier; each column of the matrix contains the delay required for the minimum bandwidth adjacent order, and the number of delay units Q in each column is equal to... (Equation 4) For the minimum bandwidth carrier sampling rate, the number of columns R in the matrix represents the number of multipliers. Depending on the asymmetry or symmetry of the coefficients, R equals L (Equation 5) or ⌈ ⌉(Equation 6), where L is the filter order. Figure 5 For example, The sampling rate for a 50MHz bandwidth carrier is 61.44MHz. The sampling rate is 15.36MHz for the narrowest bandwidth 10MHz carrier. The filter order is L. Figure 5 The delay chain between any two adjacent multipliers is a column of the delay matrix, containing Q, or 4 Z, numbers. -NUnits are used to select data from different carriers and phases; different columns of the delay matrix are used for different multipliers; the delay chain taps for different carriers are represented by different arrows, such as... Figure 5 As shown, the tap points (dashed arrows) of the 50M carrier are spaced one Z. -N Unit, tap point (solid arrow) spacing of 10M carrier. One, that is, 4 Z -N Unit. To more clearly illustrate the meaning of the taps in the delay chain, Figure 6 Taking NR 10M / 20M / 50M / 100M as an example, the meaning of the taps in a time-varying delay chain is explained: A delay chain is used to concatenate data from different bandwidths. The table at the top of the diagram illustrates the data source for each tap in different time slots. Each row of the delay chain has Q taps. )Z -N Delay unit, i.e., 8 Z -N Delay unit, where a 100M delay interval is 1 Z. -N unit A 50M latency interval is 2 Z units. -N unit The 20M delay interval is 4 Z. -N unit A 10M delay interval is 8*Z. -N Unit. Meanwhile, the multiplier MUX needs to switch between taps according to the timing sequence, and the MUX starts from the time interval. (Based on the carrier bandwidth, n=0,1,2,......) the corresponding data is obtained from the delay tap points and sent to the multiplier. Figure 5 It is worth noting that: Figure 6 The tap time slots are not fully utilized. For low-bandwidth carriers, more carrier filtering can be achieved by fully utilizing the tap time slots.

[0035] (2)

[0036]

[0037] Asymmetric coefficient filter:

[0038]

[0039] Symmetric coefficient filter:

[0040] .

[0041] Coefficient storage and time-division selection module: In the filter of this embodiment, the multiplier coefficients h(n) are time-varying, rather than fixed values ​​as in traditional filters. The filter coefficients are stored in an array. For example... Figure 7As shown in the list to the left of the multiplier, the coefficients of each multiplier are stored as an array. We represent this array using an array, where h(i,j) is the coefficient of the j-th order for the i-th carrier. This vector is then [h(0,j), h(1,j), ..., h(i,j)]. For scenarios where coefficients of different bandwidths are the same, the coefficient storage space can be further reduced.

[0042] Design of Time-Division Convolution: The design of time-division convolution is similar to that of ordinary convolution, which outputs the final result through a multiply-accumulate module; the only difference is that different time slots of the convolution belong to different bandwidths and carriers.

[0043] Design of a Multiphase 5G Multi-Bandwidth Channel Filter. This invention proposes a multi-bandwidth multiphase filter design when the input data does not occupy all time slots. We define the effective time slot number I, which physically means that within 2... The maximum number of time slots occupied by valid input data between sampling points. Since the input data does not fill all time slots, it means Fclk is greater than... *I. In this case, the present invention designs a more complex polyphase filter to further reduce the resources of the multiplier. As an example, Figure 7 This paper describes the implementation structure of a 10M / 20M / 50M polyphase filter. Like non-polyphase filters, this polyphase filter also includes a delay chain with a time-varying delay structure, time-varying coefficient storage and time-division selection, and a time-division convolutional unit (multiplicative accumulator). The delay chain of the time-varying delay structure is... Figure 7 Z below -N The delay chain formed by cascading units and the corresponding MUX multiplexing unit; time-varying coefficient storage and multiplexing, i.e. Figure 7 The table entries on the left side of the multiplication table; the time-division convolutional unit is... Figure 7 The filter multiplier-accumulator structure consists of a multiplier, a cascaded adder, and a feedback accumulator at the d_out output. The two inputs of the filter multiplier are a time-varying delay chain and storage coefficients.

[0044] Design of a time-varying delay chain for a polyphase filter. For a polyphase filter, valid serial data needs to be copied to redundant time slots before the data stream enters the delay chain. Figure 7 For details, see the data coping module. Figure 8 This allows the delay unit to output corresponding carrier data in different phase slots, which can then be used for time-division convolution. The time-varying delay chain also consists of a two-dimensional matrix, as described in Equation 2. The two-dimensional matrix has Q*R delay units, each of which has a delay of N clock cycles, where N equals... (Equation 8), where M is the number of phases of the polyphase filter, and M equals ⌈ ⌉(Equation 7), where I is the number of effective time slots and Fclk is the operating clock. This represents the sampling rate of the maximum bandwidth carrier. Due to the presence of polyphase, the column vectors of the delay matrix will be divided into... There are M multiphase sub-delay chains, each containing M sub-delay chains. Each column of the matrix represents the delay required for minimum bandwidth, and the number of delay units Q in each column is equal to... (Equation 9) The sampling rate is for the minimum bandwidth carrier. The number of columns R in the matrix represents the number of multipliers; depending on the asymmetry or symmetry of the coefficients, R equals ⌈ ⌉(Equation 10) or ⌈ ⌉(Equation 11), where L is the filter order. To more clearly illustrate the meaning of the taps in the delay chain of a polyphase filter, Figure 9 Taking an NR 10M / 20M / 50M carrier with a working clock of 122.88MHz as an example, this illustrates the taps of a time-varying delay chain for a polyphase filter: In this example, the polyphase number M equals 2. The table at the top of the diagram shows the data source for each tap in different time slots. Each row of the delay chain has Q( ) Z -N Delay unit, i.e., 8 Z -N Delay unit, wherein the interval between different phase points of 50M is 1 Z. -N unit Sampling points with the same phase but different sampling points are spaced 2 Z-axis intervals. -N unit The interval between different phase points at 20M is 2 Z. -N unit Sampling points with different phases are spaced 4 Z-numbers apart. -N The unit, with different phase points of 10M spaced 4 Z-units apart. -N unit 8 Z-sampling points in the same phase but different intervals -N unit Meanwhile, the multiplier (MUX) needs to switch between taps according to the timing sequence, and the MUX is based on the time interval. (Based on the carrier bandwidth, n=0,1,2,......) the corresponding data is obtained from the delay tap points and sent to the multiplier. Figure 7 Because data is copied before entering the delay chain, the multiplier's input MUX still selects Z at different phases. -N*M The endpoint of the delay chain should not be chosen as Z. -N*M The internal Z -N Nodes. It's worth noting that: Figure 6 The tap time slots are not fully utilized. For low-bandwidth carriers, more carrier filtering can be achieved by fully utilizing the tap time slots.

[0045]

[0046]

[0047] Asymmetric coefficient filter:

[0048]

[0049] Symmetric coefficient filter:

[0050] .

[0051] The coefficients of a polyphase filter multiplier are stored and selected in a time-division manner. Unlike non-polyphase filters, the coefficients of a polyphase multiplier are stored in a two-dimensional array, such as... Figure 7 The two-dimensional list to the left of the multiplier is shown. Let h(i,j) be the j-th order coefficient of the i-th carrier. Then the corresponding coefficient storage array of the k-th multiplier is as follows:

[0052]

[0053] This array is an M*I array, where M is defined as shown in Equation 7, and I represents the number of bandwidths. Each row of the array represents the M different phases of a certain bandwidth; each column of the array represents the corresponding coefficients for different bandwidths. Specific details are as follows:

[0054] The first multiplier coefficient array:

[0055] The second multiplier coefficient array:

[0056] The array of coefficients for the Kth multiplier:

[0057]

[0058] For scenarios where coefficients are the same despite different bandwidths, the coefficient storage space can be further reduced. The coefficients are time-divided using a column-first, row-second traversal from left to right. Figure 10 Taking 10M / 20M / 50M carriers as an example, this method of time-division selection based on circular traversal is described. The coefficients in the circle are traversed clockwise as shown in the diagram, with the traversal method being different bandwidth carriers followed by different phases, repeatedly looping through the circle. The taps within a clock cycle represent a specific phase of each bandwidth carrier, and then... The taps for different phases are traversed within the period and sent cyclically according to the time slots. The specific coefficient tap timing is as follows: [h(i,j,phase1),h(i+1,j,phase1),......,h(i+N,j,phase1),

[0059] h(i,j,phase2),h(i+1,j,phase2),...,h(i+N,j,phase2), ......

[0061] h(i,j,phaseM),h(i+1,j,phaseM),...,h(i+N,j,phaseM),

[0062] h(i,j+1,phase1),h(i+1,j+1,phase1),...,h(i+N,j+1,phase1),

[0063] h(i,j+1,phase2),h(i+1,j+1,phase2),...,h(i+N,j+1,phase2), ......

[0065] h(i,j+1,phaseM),h(i+1,j+1,phaseM),...,h(i+N,j+1,phaseM), ...]

[0067] Design of a time-division convolutional unit for a polyphase filter: The filter convolution calculation is implemented through a multiply-accumulate module. Unlike non-polyphase filters, a feedback accumulator is used at the filter output to accumulate signals of different phases (see...). Figure 7 (Top right), accumulator delay Z -I This represents the effective number of time slots. The filter output d_out is the final result.

[0068] In summary, this invention designs a multi-bandwidth channel filter based on non-polyphase (for input data time slots being fully occupied) and polyphase structures (for input data time slots not being fully occupied). The design steps are summarized as follows: (1) According to Whether it is greater than 1 determines whether to adopt a multiphase structure, (2) design the delay structure according to the carrier sampling rate, such as Figure 6 Figure 9 As shown, the serial delay chain consists of Q*R Z... -N Equation 2, for a more general polyphase filter (a non-polyphase filter is a special case of a polyphase filter), where , R equals ⌈ ⌉or⌈ ⌉, The multiplier MUX is based on Figure 6 Figure 9The table above selects the input data. (3) Design the storage and time-division selection of coefficients. Depending on whether non-polyphase filtering or polyphase filtering is used, the coefficients are stored as a one-dimensional vector and a two-dimensional array. The coefficients are extracted according to different bandwidth carriers and then different phases. When the coefficients of different bandwidths are the same, the coefficient storage space can be further reduced. (4) Design the time-division convolution. For symmetrical coefficient filters, the symmetrical coefficients are first added and then multiplied by the coefficient. When a polyphase structure is used, an additional accumulator needs to be designed at the output end. The accumulation delay period is the number of effective time slots.

[0069] The above description is merely a preferred embodiment of the present invention and is not intended to limit the invention. Various variations and modifications can be made to the invention by those skilled in the art. Any modifications, equivalent substitutions, or improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A 5G NR multi-bandwidth channel filter characterized by: It includes a time-varying delay module, a coefficient storage and time-division selection module, and a polyphase filter structure. The polyphase filter structure selects the coefficient value of the current phase of the current time slot bandwidth stored in the coefficient storage and time-division selection module according to the current phase value. At the same time, the time-varying delay module selects different delay chain taps according to the current phase in different carrier bandwidth time slots, and performs time-division convolution operation with the output coefficient value of the coefficient storage and time-division selection module to output the final result. The time-varying delay module includes a time-varying delay chain, which is composed of a two-dimensional matrix, as described in equation (1). The two-dimensional matrix has Q*R delay units, each delay unit being a delay of N clock cycles, where N equals... (Equation 2), where M is the number of phases of the polyphase filter, and M equals ⌈ ⌉(Equation 3), where I is the number of effective time slots occupied by the input data, and Fclk is the operating clock. The sampling rate of the maximum bandwidth carrier; （1） （2） （3）。 2. The 5G NR multi-bandwidth channel filter of claim 1, wherein: For a polyphase filter structure, each column of the delay matrix in equation (1) contains the delay required for the minimum bandwidth adjacent order, and the unit column vector is composed of... Each column consists of M multi-phase sub-delay chains, and the number of delay units Q in each column is equal to... (Equation 4) For the minimum bandwidth carrier sampling rate, the number of columns R in the matrix represents the number of multipliers. Depending on the asymmetry or symmetry of the coefficients, R equals ⌈ ⌉(Equation 5) or ⌈ ⌉(Equation 6), where L is the filter order; （4） Asymmetric coefficient filter: （5） Symmetric coefficient filter: （6）。 3. The 5G NR multi-bandwidth channel filter of claim 2, wherein: The coefficient storage and time-division selection module includes a coefficient storage module, a coefficient time-division selection module, and a time-division convolutional module. The coefficients of the time-division convolutional module are time-varying and are a two-dimensional storage array. Let h(i,j) be the j-th order coefficient of the i-th carrier. Then the corresponding coefficient storage array of the k-th multiplier is as follows: ， The array is an M*I array, where M is defined as shown in Equation 3, and I represents the number of bandwidths. Each row of the array represents M different phases of a certain bandwidth; each column of the array represents the corresponding coefficients of different bandwidths.

4. The 5G NR multi-bandwidth channel filter of claim 3, wherein: The time-varying order is column-first, row-later: first traversing carriers of different bandwidths, then traversing coefficients of the same order for different phases.

5. The 5G NR multi-bandwidth channel filter of claim 4, wherein: The multiplier of the multiphase filter structure has two input terminals: a time-varying delay chain and a storage coefficient module. When the input data does not fill all time slots, i.e., Fclk is greater than... *I, Before the data stream enters the delay chain, valid serial data needs to be copied to the redundant time slot so that the multiplier's input MUX still selects Z at different phases. -N*M Delay the endpoints of the chain without selecting Z. -N*M The internal Z -N Nodes are used for time-division convolution; the data MUX is used to select data from different carriers and different phases, and the MUX is based on time intervals. Data is obtained from the delay taps (based on the carrier bandwidth, n=0,1,2,......) and sent to the multiplier. The system consists of two MUX stages: the first stage selects different phases, and the second stage selects different carriers. A feedback accumulator is located at the output of the polyphase filter structure to accumulate signals of different phases. The delay Z of the accumulator is... -I The effective number of time slots is the output d_out of the polyphase filter structure, which is the final result.

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