Path loss compensation for comparators

Abstract

The present disclosure relates to path loss compensation for comparators. A test system can receive a test signal from a device under test (DUT) via a first signal path. A comparator circuit can receive the test signal and, in response, generate an intermediate output signal based on an amplitude relationship between the test signal and a comparator reference signal. A compensation circuit can generate a correction signal that is complementary to a portion of the received test signal in order to correct for loading effects of the first signal path. The test system can include an output circuit configured to provide a corrected differential output signal based on a combination of the intermediate output signal and the correction signal.

Description

Technical Field

[0001] A test system for testing electronic devices may include pin driver circuitry that provides voltage test pulses to a device under test (DUT). In response, the test system may be configured to measure the response from the DUT, for example, to determine whether the DUT meets one or more specified operating parameters. The test system may optionally include multiple driver circuits, such as Class AB driver circuitry and Class A driver circuitry, to provide circuit test signals with different amplitude or timing characteristics. In one example, the test system is configured to use an active load and comparator circuitry to measure the response from the DUT to sense transitions at DUT pins. Background Technology

[0002] A system for testing digital integrated circuits (ICs) may include being configured to provide multiple voltage levels (e.g., V) to the DUT. high V low and V term The driver circuit of the DUT can exhibit bidirectional (I / O) capability because it can both provide and receive stimuli. high and V low The level is used to stimulate the DUT when it is in the "input" state, and V term Acts as the terminal of the DUT in its "output" state. In V high V low and V term The switching process between them can be conceptualized as a set of three switches, where one end of each switch is connected to V. high V low or V term The other end is connected to a 50-ohm resistor, which is then connected to the DUT node. The transition between the three levels can be achieved by turning appropriate switches on and off, for example, by turning off only one switch at any given time.

[0003] Various comparator circuit structures have been proposed. Some feature enhanced latching accuracy or bandwidth capabilities for operations such as high-speed sampling in applications including analog-to-digital converters or automated test equipment (ATE). In one example, the comparator circuit includes an AC input node, a DC input node, and an output node. In examples of comparators that include circuitry configured to perform automated testing of a DUT, the AC input node can be coupled to the DUT interface node, and the DC input node can be coupled to a reference node to receive a reference voltage signal. Signal variations at the comparator circuit's output node can provide information about the relationship between the DUT output and the reference voltage signal. Summary of the Invention

[0004] The inventors have recognized that, among other things, the problem to be solved includes providing an automated test system for measuring response signals from a device under test (DUT). This problem may include providing a system that is relatively small, has low manufacturing costs, consumes less power than conventional systems, or provides higher fidelity performance relative to conventional systems. In one example, the problem may include providing a comparator for the system with a constant input propagation delay. The problem may also include artifacts in the physical signal system that can cause or lead to signal corruption. Sources of corruption, for example, may include skin effect losses, dielectric loads, conductor resistance, and waveform reflections. Such sources of signal corruption can cause undesirable variations in the DUT signal as the signal propagates between the DUT and, for example, a comparator configured to measure changes in the DUT signal. These undesirable variations in the DUT signal can lead to signal timing errors due to propagation delays, which in turn can result in erroneous or incorrect test results.

[0005] In one example, solutions to these and other problems may include or utilize comparator circuitry or comparator stages in an automated test equipment (ATE) system with loss compensation circuitry. The inventors have recognized that loss compensation circuitry can be configured to address signal errors, such as those caused by conductor or path loads, which can be characterized and quantified. For example, scattering parameters or S-parameters can be measured to describe the non-ideal electrical behavior of the signal path extending between the DUT output node and the comparator circuit input node. The loss compensation circuitry may include a filter based on the measured S-parameters, which represents the inverse function of the non-ideal electrical behavior of the signal path. The filter can then be used to generate a compensation signal, which can be added, for example, to the comparator input signal to provide a corrected output signal. That is, the filter can provide a corrected signal as the inverse response to a lossy input path, and the corrected signal can be added to the input signal to correct it.

[0006] In one example, a solution to the above problem may include a test system comprising a first differential pair circuit configured to generate an intermediate output signal based on the relationship between a test signal received from the device under test (DUT) and a reference signal (Vth). The test system may also include path load compensation circuitry configured to generate an AC-coupled correction signal. In one example, the compensation circuitry includes a transconductance stage configured to provide a DC-coupled intermediate signal to a gain stage, and further includes a signal shaping filter stage configured to provide the correction signal based on the output signal from the gain stage. The test system may also include an output circuitry configured to provide a corrected output signal based on the superposition or combination of the intermediate output signal and the correction signal.

[0007] In one example, a solution to the above problem may include a method comprising: receiving a test signal from a device under test (DUT) at the input node of a comparator; generating an intermediate output signal (Vth) based on a relationship between the test signal from the DUT and a comparator reference signal; providing a DC-coupled signal based on a relationship between the test signal from the DUT and the comparator reference signal; generating an AC-coupled correction signal using the DC-coupled signal, the correction signal providing an inverse response to the lossy input signal path and being applied to a portion of the received test signal; and then providing a corrected output signal based on a combination of the intermediate output signal and the correction signal.

[0008] This overview is not intended to provide an exclusive or exhaustive interpretation of the invention. Detailed descriptions are included to provide further information regarding this patent application. Attached Figure Description

[0009] To facilitate identification of discussions of any particular element or behavior, the highest significant digit in the reference numbers refers to the graphic number at which the element was first introduced.

[0010] Figure 1 An example of a test system topology that includes multiple driver circuits is shown in general.

[0011] Figure 2 An example of a comparator circuit is shown in general.

[0012] Figure 3 An example of a comparator circuit and signal timing diagram is shown in general.

[0013] Figure 4 An example of a comparator system with a non-ideal signal path is shown in general.

[0014] Figure 5 An example of a portion of a comparator circuit is shown in general, which may include a first differential circuit and a first compensation circuit.

[0015] Figure 6 An example of a comparator circuit with a second compensation circuit is shown in general.

[0016] Figure 7 An example of a comparator circuit with a third compensation circuit is shown in general.

[0017] Figure 8 The illustration generally shows an example of a method that may include providing a corrected comparator output using compensation circuitry. Detailed Implementation

[0018] The test system may include a pin driver configured to provide a voltage pulse excitation to the device under test (DUT) at specified times, and may include measurement circuitry for receiving and measuring the response signal from the DUT. The test system can be configured to provide high-fidelity output signal pulses over a relatively large output signal amplitude range to accommodate different tests and different types of DUTs.

[0019] In one example, the test system may include a pin driver architecture that can provide a high-fidelity stimulus signal with minimal overshoot or high-frequency current signal spikes, and can maintain pulse edge placement accuracy and signal bandwidth at high or low power operating levels. In one example, the test system may include one or more driver stages, such as Class A or Class AB driver stages, which can be configured to provide various pulse signals. The system may include control circuitry to precisely control the switching control voltage signal and the switching current signal, and to control the operating mode of the comparator and monitoring or measurement activities.

[0020] In one example, multiple drivers or driver tiers can be used to provide a test system that can be configured to test various semiconductor devices with varying voltage and speed requirements. Furthermore, multiple drivers can be used to enhance or enable "multiplexing" of multi-signal level testing or physical layer testing. During physical layer testing, multiple drivers can be switched simultaneously to provide various different excitation or drive signals to the DUT.

[0021] Test systems may include comparator circuitry or comparator stages configured to receive high-speed voltage or current response signals from the DUT. Typically, a comparator is a decision element that provides information about the relationship between at least two input signals. For example, a comparator may provide a digital output (e.g., a logic high or logic low signal) indicating the relationship between a signal from the DUT and a reference signal (e.g., a reference voltage signal). A comparator may include one or more gain stages, which may be series-coupled to produce a high-gain response. In one example, offset errors, such as those caused by path loads between the DUT and the comparator, can lead to processing errors, which in turn can result in test escape or low yield.

[0022] In some examples, high-speed automated test equipment (ATE) systems have sufficiently high bandwidth that non-ideals in the transmission medium between the device under test (DUT) and the ATE pin electronics can significantly limit overall system performance. This transmission medium or path typically includes several cables, connectors, printed circuit board traces, and "pogo pins" electrically coupled to the DUT. The losses associated with these components primarily manifest as the "skin effect," where the resistance seen by the propagating signal is a function of the signal frequency. Because every signal can be represented by a superposition of many frequency components, some components suffer greater losses than others, resulting in dispersion effects that degrade the received signal. Extreme care must be taken when designing the transmission path if the original signal is to be presented to the pin electronics with minimal distortion. In some cases, the frequency components present in high-speed signals are so high that even the best-quality transmission paths can lead to significant degradation of signal integrity. In such cases, the pin electronics receiver (typically a comparator) can include or use compensation circuitry to compensate for the expected transmission losses. This circuitry can be included as part of the pin electronics comparator and is sometimes referred to as cable loss compensation.

[0023] The systems and methods described herein provide, in particular, a digitally controlled comparator with loss compensation circuitry. This loss compensation circuitry can generate a residual signal, or extract a residual or error signal from the input signal, to provide a correction signal that can be combined with the DUT signal to correct signal fidelity, thereby helping to minimize timing errors due to path load. Some examples in this paper include or illustrate various comparators or comparator circuits in a test system or ATE context; however, other applications are also contemplated. In other words, the systems and methods discussed herein can generally be applied to other receiver circuits that suffer signal distortion in the received transmission medium. Such circuits typically include differential receiver circuitry, such as differential line receivers for clock or data recovery circuitry, or telecommunications input circuitry. An ATE receiver can be considered a special case of such a differential receiver, where one signal (e.g., the DUT output) is received via the transmission medium, and another signal (e.g., a reference signal) is generated locally.

[0024] Figure 1A first example 100 of a test system topology including multiple driver stages and comparator stages is generally shown. The first example 100 includes a first driver AB 102 that may include class AB driver circuitry and a first driver A104 that may include class A driver circuitry. The first example 100 may also include output elements, such as a first resistor 106, which can be configured to provide a specified output or load impedance. In one example, the first example 100 may include comparator circuitry 122 or a first load circuitry 108, such as an active load or other load device. In one example, the test system is configured to provide a first output current 120i_OUT at the DUT signal 130.

[0025] In one example, the first driver AB 102 can be configured to generate a voltage excitation signal by selecting between parallel-connected diode bridges, each bridge being driven by a unique dedicated DC voltage level. Figure 1 In the first example 100, DC voltages Vih 110 and Vil 112 drive the diode bridge in the first driver AB 102. Following the switching stage can be a voltage buffer stage, which can provide power gain, for example, it can be used to generate large currents to serve a 50-ohm DUT environment.

[0026] Compared to the first driver AB 102, the first driver A104 can be configured to generate a transition at the DUT signal 130 using a relatively large current switching stage that can be directly coupled to the DUT signal 130. The current switching stage in the first driver A104 can alternately switch current to and from the DUT signal 130 in response to a control signal swing 118 (e.g., a voltage control signal). For example, the first driver A104 can provide high-speed operation because it is unaffected by the Class AB voltage buffer stage and its associated bandwidth limitations and other performance constraints.

[0027] In one example, the first driver A104 can be configured to provide a relatively low amplitude signal at the DUT signal 130. For example, the first driver A104 can provide a signal with a swing of approximately 2 volts. The first driver AB 102 can be configured to provide a relatively high amplitude signal at the DUT signal 130, ranging from -1.5 to +7 volts. The first driver A104 typically operates with a higher switching speed or bandwidth than the first driver AB 102. In one example, the first driver AB 102 can be configured to sink the switching current from the first driver A104. That is, the first driver AB 102 can be used as a buffer to which the first driver A 104 can provide current, for example, through the first resistor 106.

[0028] One or both of the first driver AB 102 and the first driver A104 can be selected to meet different DUT testing requirements that a single driver might otherwise fail to meet. For example, while both driver circuits can provide DUT waveforms, the first driver AB 102 can be configured to provide a large-amplitude, low-bandwidth stimulus signal, and the first driver A104 can be configured to provide a low-amplitude, high-bandwidth stimulus signal.

[0029] In one example, the first driver AB 102 and the first driver A104 do not share an enable pin. Instead, each driver circuit includes independent enable control via pins EnAB 114 and EnA116. Independent enable control helps the first driver AB 102 function as a low-speed, high-voltage stimulus source and as a static, non-switching buffer to absorb switching current from the first driver A104.

[0030] Figure 1 The system includes comparator circuitry 122. Comparator circuitry 122 may include single-stage or multi-stage comparators configured to receive DUT signal 130 from DUT 124, for example, via DUT signal 130 and a loaded signal path 132. Comparator circuitry 122 may compare the received signal with comparator reference signal 126 (e.g., Vth) and, in response, provide differential comparator output signal 128 (e.g., OP). For example, comparator circuitry 122 may receive a voltage response signal from DUT 124 and compare the amplitude of the voltage response signal with the amplitude of comparator reference signal 126. Comparator circuitry 122 may use differential comparator output signal 128 to provide information about the amplitude relationship, for example, it may include a digital signal or a logic output signal.

[0031] Figure 2 A comparator example 200 is generally shown, which may include comparator circuitry 122. Comparator circuitry 122 may include comparator input node 210, reference signal input node 212, first output node 214, and second output node 216. Comparator circuitry 122 may include multiple different circuit stages provided in series. For example, comparator circuitry 122 may include a comparator stage 206, one or more gain stages, such as first gain stages 202 through nth gain stages 208, and an output stage 204.

[0032] In one example, comparator stage 206 may be configured to receive DUT signal 130 from DUT 124 using comparator input node 210, for example, via loaded signal path 132. Comparator stage 206 may receive comparator reference signal 126Vth using reference signal input node 212. Typically, comparator stage 206 is configured to perform signal comparison operations to determine which of the various signals at comparator input node 210 and reference signal input node 212 has a larger or smaller signal amplitude characteristic, for example, at a specific or specified time. The comparison result or output of comparator stage 206 may be provided to first gain stage 202. In one example, the comparison result includes a differential signal or logic signal, i.e., a signal with two signal components.

[0033] In one example, comparator stage 206 includes a differential amplifier that amplifies the differential voltage received at comparator input node 210 and reference signal input node 212, and suppresses common-mode signal components. Various other comparator stage 206 circuitry can be used, including one or more comparators described by McQuilkin in U.S. Patent 9,813,050, entitled "Comparator Circuit with Input Attenuator," the entire contents of which are incorporated herein by reference. The decision circuitry of comparator stage 206 may include a differential pair that reports when the DUT signal crosses the reference signal voltage Vth, but may also be used as a level shifter to allow subsequent gain stages to operate below ground, for example, to save power.

[0034] The first gain stage 202 may include various gain or amplifier circuits. That is, the first gain stage 202 may include amplifier circuitry, such as operational amplifiers or other arrangements or configurations of transistors or other circuitry, to perform signal amplification or buffering. Multiple gain stage instances may be provided in series, such that each gain stage further amplifies or buffers the output of the previous gain stage. Figure 2 In the example, the first gain stage 202 provides a first gain stage output signal to one or more intermediate gain stages, which in turn use the last or nth gain stage 208 to provide a gain stage output. The nth gain stage 208 can be configured to provide an output signal to a relatively high input impedance receiver in the output stage 204. In response, the output stage 204 can provide an output signal to a low impedance environment. Various gain stages, such as the first gain stage 202, the nth gain stage 208, and any one or more other gain stages, can be configured the same or different.

[0035] In one example, output stage 204 provides differential comparator output signals 128 comprising first and second signal components Q and Qb at first output node 214 and second output node 216, respectively. That is, the comparator stage output signal components can be used to provide a digital output signal indicating the amplitude relationship between the input signals received at comparator input node 210 and reference signal input node 212.

[0036] In one example, any one or more of the comparator stage 206, the first gain stage 202 through the nth gain stage 208, or the output stage 204 may include or use compensation circuitry to update or correct signal characteristics or errors in the DUT signal received at comparator input node 210.

[0037] Figure 3 An example of comparator 300 is shown in general. Comparator 300 includes a schematic diagram of comparator circuit 122 having inputs configured to receive DUT signal 130 and comparator reference signal 126, and outputs configured to provide differential comparator output signal 128 as differential signals Q and Qb.

[0038] Figure 3 This also includes signal timing diagrams. In one example, comparator circuit 122 can be considered an analog-to-digital converter that converts a time-varying analog input (e.g., DUT signal 130) into a digital representation (e.g., differential comparator output signal 128) based on the relationship between the input signal and a reference (e.g., comparator reference signal 126 or Vth). In an ATE system, the comparator can be used to “digitize” the time-dependent voltage signal of the DUT by decomposing the signal into time / voltage data pairs. Therefore, an important high-frequency (AC) performance metric for the comparator is a constant, input-invariant propagation delay to ensure that the data pairs are known or predictable.

[0039] Figure 3 Examples of various time / voltage data pairs are shown to demonstrate the impact of propagation delay. Time / voltage data pairs can be measured by adjusting the threshold voltage and recording the output crossover time. For example, assuming the DUT signal transitions from zero to one volt, the output crossover time occurs at T1 when Vth = Vth1, and at T2 when Vth = Vth2. Therefore, high-resolution Vth increments and an input-invariant propagation delay can produce a faithful copy or digitization of the DUT signal. If the propagation delay is variable or unpredictable, the actual time / voltage data pairs may deviate from known or expected values, which in turn can lead to an inaccurate representation of all or part of the DUT signal.

[0040] Figure 4An example including comparator system 402 and non-ideal signal paths is generally shown. Comparator system 402 can be configured to provide differential comparator output signal 128 based on the corrected DUT signal 416.

[0041] Non-ideal systems compete with various sources of signal corruption. For example, the ATE system competes with non-idealities in the signal path extending between the DUT 124 and, for example, the input node of comparator circuit 122. These non-idealities can exist in each of several different channels between the DUT 124 and comparator circuit 122, and their behavior can differ in each channel. Examples of non-idealities include skin effect loss, PCB dielectric load, transmission line resistance, and waveform reflections, all of which collectively distort the true DUT waveform before comparator circuit 122 can operate the DUT signal.

[0042] exist Figure 4 In the example, the DUT signal generated at DUT 124 may include an unloaded, ideal DUT signal 410 representing the true DUT waveform. The DUT signal 410 may be provided to comparator circuitry 122 using a load signal path 408, which may introduce or cause various variations in the true DUT waveform, resulting in a non-ideal or corrupted DUT signal 412. In one example, if comparator system 402 receives and processes a corrupted DUT signal 412, the differential comparator output signal 128 may include error information.

[0043] The characteristics of a non-ideal or load signal path 408 can be measured, quantified, or characterized. For example, the frequency response of the load signal path 408 can be measured, and S-parameters describing the electrical behavior of the path can be determined. This information about the characteristics of the loaded signal path 408 can be used to determine a signal filter, and the filter can be used to provide an inverse response signal or compensation signal that represents the deviation of the damaged DUT signal 412 from the ideal DUT signal 410. That is, the compensation signal may include a signal having a step response opposite to the path loading response of the loaded signal path 408. The compensation signal can be added to the damaged DUT signal 412 to provide corrected DUT data 416, and the corrected DUT data 416 can be used by the comparator system 402 to generate a differential comparator output signal 128.

[0044] exist Figure 4In the example, comparator system 402 includes compensation circuitry 404 and gain circuitry 406. Compensation circuitry 404 may include passive or active signal filter processing circuitry configured to represent the inverse response of load signal path 408. That is, compensation circuitry 404 may be configured to generate a compensation signal that compensates for losses or variations in a particular signal when the signal path 408 carries the load signal. Parameters of compensation circuitry 404 may be channel-specific and may optionally be adjustable by the user. In other words, components or signal processing configurations of compensation circuitry 404 may be updated or adjusted to accommodate variations in the load signal path 408 between the DUT and comparator system 402.

[0045] Gain circuit 406 may include amplifier circuitry configured to amplify or attenuate the amplitude of the compensation signal provided by compensation circuit 404. In an example, gain circuit 406 includes a digitally controlled amplifier configured to receive a user-specified control signal at compensation control node 420. The control signal can be used to adjust the amount of gain or attenuation provided by gain circuit 406. The output node of gain circuit 406 can provide a correction signal 414. In an example including multiple test signal channels, gain circuit 406 may be configured to provide a different gain adjustment level for each channel to correct for channel-specific losses.

[0046] In one example, the correction signal 414 represents a gain-adjusted version of the compensation signal from the compensation circuit 404. The correction signal 414 can be provided to the summing circuit 418, where the corrupted DUT signal 412 can be combined with the correction signal 414. Therefore, the summing circuit 418 can provide corrected DUT data 416 based on the combination of the corrupted DUT signal 412 and the correction signal 414.

[0047] Figure 5 An example of a portion of a comparator circuit is shown, which may include a first differential circuit 502 and a first compensation circuit 504. The first compensation circuit 504 may include an example of a compensation circuit 404. The outputs from the first differential circuit 502 and the first compensation circuit 504 may be combined to provide a differential comparator output signal 128, for example, which may be provided to a subsequent gain stage in an ATE system.

[0048] exist Figure 5 In the example, the comparator circuit includes a first differential circuit 502, configured to receive an AC DUT signal and provide a differential output current signal based on the amplitude relationship between the DUT signal and the DC reference voltage Vth. Figure 5In the example, the first differential circuit 502 includes a differential pair of NPN transistors with a degraded resistor R1. This differential pair is a transconductance circuit that converts the difference between the DUT voltage and the reference voltage into differential output current signals including signals Iq1 and Iq0. Ideally, if the DUT signal and Vth are equal, Iq1 and Iq0 can have equal current amplitude characteristics. If, under the same input conditions, Iq1 and Iq0 are not equal, the amount of difference between them is considered an offset. Typically, it is desirable for the comparator to exhibit little or no offset. Where an offset exists, it is desirable that this offset be constant and independent of the input signal characteristics or gain settings.

[0049] exist Figure 5 In the example, the first compensation circuit 504 is configured to receive an AC DUT signal. The first compensation circuit 504 may include a differential pair circuit to provide an intermediate differential current signal, typically corresponding to the differential signals Iq1 and Iq0 from the first differential circuit 502. The differential pair circuit in the first compensation circuit 504 can draw current from the current source I... BIAS1 and I BIAS0 The first compensation circuit 504 receives a DC bias signal and may further include a first shaping filter 506, which may be configured, for example, to influence AC signal coupling between branches of the differential pair circuit. In one example, in response to variations in the DUT signal, the differential pair may provide an intermediate differential current signal as a function of the first shaping filter 506. In other words, in response to variations in the received AC DUT signal, the differential pair in the first compensation circuit 504 may apply waveform or signal components dependent on the first shaping filter 506 over the DC bias signal. Therefore, the intermediate differential current signal may include both the DC-coupled signal provided by the first compensation circuit 504 and the AC component.

[0050] The comparator circuit may also include an example of gain circuit 406, which can be configured, for example, by a control signal at compensation control node 420. Figure 5 In the example, the gain circuit 406 can receive the intermediate differential current signal from the first compensation circuit 504 and provide a gain-adjusted differential compensation signal I. C1 and I C0 The gain-adjusted differential compensation signal can be combined with the differential signals Iq1 and Iq0 from the first differential circuit 502 to provide a corrected differential output signal I. SUM1 and I SUM0 .

[0051] Therefore, the output of the first compensation circuit 504 includes an AC compensation component (e.g., generated using the first shaping filter 506) and a component from the current source I. BIAS1 and I BIAS0The gain circuit 406 receives the output from the first compensation circuit 504 and operates the AC and DC compensation components to provide the compensation signal I. C1 and I C0 The inventor has recognized that, Figure 5 The problem with the circuit may include the compensation signal I. C1 and I C0 And therefore in the output signal I SUM1 and I SUM0 The possibility of introducing offsets.

[0052] For example, if the first compensation circuit 504 provides an intermediate differential current signal without an AC component (e.g., because the DUT signal matches the threshold voltage), then due to the current source I... BIAS1 and I BIAS0 The DC bias signal is used, while the intermediate differential signal only includes the DC component. Gain circuit 406 can receive and manipulate the intermediate differential current signal to provide a compensation signal I. C1 and I C0 If the gain circuit 406 is not ideal, then compensation signal I can be applied. C1 and I C0 An offset error is introduced. The result is that the gain circuit 406 controls the associated offset, which may be undesirable.

[0053] Solutions to the offset problem may include providing physically large, high-precision gain components. However, such physically large components may affect bandwidth and other performance characteristics. Another solution may include calibrating the gain circuit 406 for each input code at the compensation control node 420 and for each corresponding test condition or DUT type. In one example, calibration may include generating a correction signal whose magnitude depends on the mismatch between the compensation signals IC1 and IC0 for each input code at the compensation control node 420. However, such calibration may be time-consuming, expensive, and impractical. For example, such calibration may not take into account the drift of the correction signal over time and temperature. Different solutions may include generating and processing the AC and DC components of the correction signal separately to help avoid the effects of control-related offsets.

[0054] Solutions to the offset problem may include providing physically large, high-precision gain components. However, such physically large components may affect bandwidth and other performance characteristics. Another solution may include calibrating the gain circuit 406 for each input code at the compensation control node 420 and for each corresponding test condition or DUT type. In one example, calibration may include generating a correction signal whose magnitude depends on the compensation signal I for each input code at the compensation control node 420. C1and I C0 The amount of mismatch between the two. However, such calibration can be time-consuming, expensive, and impractical. For example, such calibration may not take into account the drift of the correction signal over time and temperature. Different solutions may include generating and processing the AC and DC components of the correction signal separately to help avoid the effects of controllable offsets.

[0055] Figure 6 An example of a comparator circuit with a second compensation circuit 606 is generally shown. The second compensation circuit 606 may include an example of a compensation circuit 404. Output current signals Iq1 and Iq0 from the first differential circuit 502 and output current signal I from the second compensation circuit 606 are also shown. C1 and I C0 They can be combined separately to provide the differential comparator output signal 128, for example, to be provided to the subsequent gain stage in the ATE system.

[0056] exist Figure 6 In the example, the second compensation circuit 606 includes a buffer circuit 602 and a second shaping filter 604. The buffer circuit 602 can be configured to monitor or receive the DUT signal from the DUT and optionally adjust the amplitude characteristics of the signal. The buffer circuit 602 can feed the differential output signal to the second shaping filter 604, which in turn can provide a compensation signal I. C1 and I C0 The buffer circuit 602 may optionally include a unity-gain buffer, or in some examples, it may be omitted from the second compensation circuit 606.

[0057] Figure 7 An example of a comparator circuit with a third compensation circuit 706 is generally shown. The third compensation circuit 706 may include an example of compensation circuit 404 or one or more portions thereof. Figure 7 In the example, the output current signals Iq1 and Iq0 from the first differential circuit 502 and the output current signal I from the third compensation circuit 706 are... AC1 and I AC0 They can be combined separately to provide the differential comparator output signal 128, for example, to be provided to the subsequent gain stage in the ATE system.

[0058] Among other things, the third compensation circuit 706 may include a transconductance circuit 702 and a third shaping filter 704. The third compensation circuit 706 may optionally include a gain circuit 406, or may be coupled to a gain circuit 406.

[0059] Transconducting circuit 702 can be configured to receive DUT signal 130 and, in response, provide a differential DC-coupled signal representing DUT signal 130. That is, transconducting circuit 702 can be configured to generate a DC-coupled current waveform representing the AC voltage characteristics of DUT signal 130, and can further represent or include information about the DC characteristics of DUT signal 130 relative to a threshold voltage Vth. In one example, transconducting circuit 702 may include a degenerate resistor (e.g., Rtran), but other signal processing or AC signal shaping filtering may be omitted.

[0060] The DC-coupled signal can be received and processed by the gain circuit 406, for example, based on the control signal received at the compensation control node 420, to provide an intermediate compensation signal I for gain adjustment. DC1 and I DC0 Therefore, the intermediate compensation signal can include an amplified or attenuated analog voltage of the DUT signal 130. Due to defects in the gain circuit 406, DC mismatch or error can be included in the intermediate compensation signal I. DC1 and I DC0 However, these DC error components can be removed or blocked, for example, using a third shaping filter 704.

[0061] The third shaping filter 704 can receive the intermediate compensation signal I. DC1 and I DC0 In response, a differential correction signal I is provided. AC1 and I AC0 In other words, the third shaping filter 704 can receive differential inputs, such as the intermediate compensation signal I. DC1 and I DC0 This can include DC coupling errors that can be blocked by the third shaping filter 704. The third shaping filter 704 can also be configured to extract the AC coupling component, representing a function of signal loss, such as due to the loaded signal path 408. In other words, the differential correction signal provided by the third shaping filter 704 can include AC coupling components that can be used to correct errors that may exist in the output current signals Iq1 and Iq0 from the first differential circuit 502, thereby correcting loading path errors or losses. The differential correction signal can be combined with the differential signals Iq1 and Iq0 from the first differential circuit 502, respectively, to provide the differential comparator output signal 128, which includes, for example, the differential component Iq1. SUM1 and I SUM0 .

[0062] In one example, the third shaping filter 704 includes various passive or active filtering or signal processing circuitry. The characteristics of the filter and the resulting AC coupling components may be fixed or adjustable, for example, in response to user input. In one example, the third shaping filter 704 may include control circuitry that updates or adjusts various impedance characteristics or component values ​​of the filter. In one example, one or more components or values ​​of the filter may be based in part on characteristics of the DUT signal 130, such as the amplitude or frequency of the DUT signal 130.

[0063] Figure 8 An example of method 800 is generally shown, which may include providing a corrected comparator output using a residual generator or compensation circuitry. At block 802, method 800 may include receiving a test signal from the DUT at an input node of the comparator circuitry or comparator system. In one example, block 802 may include receiving a DUT signal 130 via a loaded signal path 132.

[0064] In block 804, method 800 may include generating differential intermediate output signals (e.g., Iq1 and Iq0) based on the relationship between the received test signal and the comparator reference signal. The intermediate output signals may not be corrected. That is, the intermediate output signals may include various timing or offset errors that may be at least partially attributable to distortion in the received DUT signal 130.

[0065] In block 806, method 800 may include receiving a test signal at the transconductance stage and, in response, providing a corresponding differential DC-coupled signal. In block 808, method 800 may include receiving the DC-coupled signal at an amplifier circuit and buffering or adjusting the amplitude of the DC-coupled signal. In block 810, the buffered or amplitude-adjusted DC-coupled signal may be received and processed by a filter circuit. The filter circuit may be configured to block the DC-coupled component of the DC-coupled signal and extract an AC-coupled correction signal.

[0066] In block 812, method 800 may include providing a corrected comparator output based on a combination of an intermediate output signal (e.g., from block 804) and an AC-coupled correction signal. That is, block 812 may include adding the individual components of the differential intermediate output signal to the components of the AC-coupled correction signal to provide a differential comparator output that compensates for path loss or distortion in the DUT signal 130 and thus resists timing or offset errors.

[0067] Various aspects of this disclosure can help provide solutions to the test system-related problems identified herein. In one example, aspect 1 may include a method comprising: receiving a test signal from a device under test (DUT) at an input node of a comparator; generating an intermediate output signal based on a relationship between the test signal from the DUT and a comparator reference signal; providing a DC-coupled signal based on the relationship between the test signal from the DUT and the comparator reference signal; generating an AC-coupled correction signal using the DC-coupled signal, the correction signal being complementary to a portion of the received test signal; and providing a corrected output signal based on a combination of the intermediate output signal and the correction signal.

[0068] In aspect 2, the subject matter of aspect 1 may include generating a correction signal, including processing a test signal received from the DUT using a filter, wherein the filter is configured to compensate for conductor path loss between the DUT and the input node.

[0069] In aspect 3, any one or more of the topics in aspects 1-2 may include generating a correction signal, including applying a signal filter to a test signal received from the DUT, wherein the time constant characteristics of the signal filter are based on the load characteristics of the signal path coupled to the input node of the comparator.

[0070] In aspect 4, any one or more of the topics in aspects 1-3 may include generating a correction signal, including processing the test signal received from the DUT using a gain stage and a shaping filter.

[0071] In aspect 5, the subject matter of any one or more of aspects 1-4 may include providing a DC-coupled signal, including: receiving a test signal from the DUT at a transconductance stage and generating a corresponding DC-coupled residue, and processing the DC-coupled residue using a gain stage to provide a DC-coupled signal.

[0072] In aspect 6, the subject matter of aspect 5 may include generating DC-coupled residuals, including: updating the bias signal or AC coupling characteristics of the differential pair circuit; and processing test signals from the DUT using the differential pair circuit.

[0073] In aspect 7, any one or more of the topics in aspects 5-6 may include changing the magnitude of the DC coupling residue in the gain stage.

[0074] In aspect 8, the subject of aspect 7 may include receiving information about the DUT (e.g., information about the type of the DUT) and, based on prior information about the DUT itself, changing the magnitude of the DC coupling residual in the gain stage based on the received information about the DUT.

[0075] In aspect 9, the subject matter of any one or more of aspects 5-8 may include providing a DC-coupled signal, including extracting the AC component of the load characteristics of the signal path at the input node of the comparator from the DC-coupled signal.

[0076] In aspect 10, any one or more of the topics in aspects 1-9 may include using differential pair circuitry to generate intermediate output signals to provide information about the relationship between the test signal and the comparator reference signal.

[0077] Aspect 11 may include or use a system for monitoring information from a device under test (DUT), the system comprising: a DUT input node configured to receive a test signal from the DUT via a first signal path; a comparator circuit coupled to the DUT input node and configured to generate an intermediate output signal based on a relationship between the test signal from the DUT and a comparator reference signal; a compensation circuit coupled to the DUT input node and configured to generate a correction signal to compensate for a portion of the received test signal; and an output circuit configured to provide a corrected output signal based on a combination of the intermediate output signal and the correction signal.

[0078] In aspect 12, the subject matter of aspect 11 may include an output circuit configured to add an intermediate output signal and a correction signal to provide a correction output signal.

[0079] In aspect 13, any one or more of the topics in aspects 11-12 may include compensation circuitry including a shaping filter configured to compensate for load effects of the first signal path.

[0080] In aspect 14, the subject matter of aspect 13 may include compensation circuitry, for example, may further include gain circuitry, and the shaping filter may be configured to block the DC component of the output from the gain circuitry.

[0081] In aspect 15, any one or more of the topics in aspects 13-14 may include compensation circuitry, and may also include, for example, a transconductance stage configured to receive voltage information about a test signal and, in response, provide a corresponding DC coupling current signal to a shaping filter.

[0082] In aspect 16, the subject matter of aspect 15 may include an amplifier circuit configured to alter (e.g., amplify or attenuate) the amplitude characteristics of a current signal supplied to a shaping filter.

[0083] In aspect 17, the subject matter of aspect 16 may include an amplifier circuit configured to change the amplitude characteristics of a current signal based on information from user input about a particular device under test.

[0084] In aspect 18, the subject matter of any one or more of aspects 15-17 may include an adjustable bias circuit for a transconductance stage, wherein the magnitude of the current signal depends on the bias conditions set by the adjustable bias circuit to suit a particular device under test.

[0085] Aspect 19 may include or use a test system comprising: a first differential pair circuit configured to generate an intermediate output signal based on a relationship between a test signal received from the device under test (DUT) and a reference signal; a path loading compensation circuit configured to generate an AC-coupled correction signal complementary to a portion of the received test signal, wherein the compensation circuit includes a transconductance stage configured to provide a DC-coupled intermediate signal to a gain stage, and a signal shaping filter stage configured to provide the correction signal based on an output signal from the gain stage; and an output circuit configured to provide a corrected output signal based on a combination of the intermediate output signal and the correction signal.

[0086] In aspect 20, the subject matter of aspect 19 may include a gain stage configured to receive a control signal indicating the desired amplitude characteristics of a correction signal for a particular device under test.

[0087] Aspect 21 is at least one machine-readable medium, including instructions that, when executed by processing circuitry, cause the processing circuitry to perform operations to implement one or more or a portion of aspects 1-20.

[0088] Aspect 22 is an apparatus that includes means for implementing any one or more aspects of aspects 1-20.

[0089] Aspect 23 is a system for implementing any one or more aspects of aspects 1-20.

[0090] Aspect 24 is a method for implementing any one or more aspects of aspects 1-20.

[0091] Each of these non-restrictive aspects may exist independently or may be combined in various permutations or combinations with one or more other aspects, examples, or features discussed elsewhere in this document.

[0092] This detailed description includes references to the accompanying drawings, which form part of the detailed description. The drawings illustrate, by way of illustration, specific embodiments in which the invention can be practiced. These embodiments are also referred to herein as “examples.” These examples may include elements other than those shown or described. However, the inventors also contemplate examples that provide only those elements shown or described. The inventors contemplate examples of any combination or arrangement of those elements (or one or more aspects thereof) shown or described herein, either with respect to a particular example (or more than one aspect thereof), or with respect to other examples (or one or more aspects thereof) shown or described herein.

[0093] In this document, the terms “a” or “an” are common in patent documents and include one or more, independent of any other instances or uses of “at least one” or “one or more”. Unless otherwise stated, “A or B” includes “A but not B”, “B but not A”, and “A and B”. In this document, the terms “comprising” and “wherein” are used as the plain English equivalents of the respective terms “including” and “in”.

[0094] In the following claims, the terms "comprising" and "including" are open-ended, meaning that a system, apparatus, article, composition, formulation, or method that includes elements other than those listed after the term in the claim is still considered to fall within the scope of the claim. Furthermore, in the following claims, the terms "first," "second," and "third," etc., are used merely as labelling and are not intended to impose numerical requirements on their subject matter.

[0095] The methods described herein may be implemented, at least in part, by a machine or computer. Some examples may include computer-readable or machine-readable media encoded with instructions operable to configure an electronic device to perform the methods or circuit operations or circuit configuration instructions described in the examples above. Implementations of this method may include code, such as microcode, assembly language code, high-level language code, etc. Such code may include computer-readable instructions for performing various methods. The code may form part of a computer program product. Furthermore, in one example, the code may be tangibly stored on one or more volatile, non-transitory, or non-volatile tangible computer-readable media, for example, during execution or at other times. Examples of such tangible computer-readable media may include, but are not limited to, hard disks, removable disks, removable optical discs (e.g., compact discs and digital video discs), magnetic tape cassettes, memory cards or sticks, random access memory (RAM), read-only memory (ROM), etc.

[0096] The above description is intended to be illustrative and not restrictive. For example, the examples (or one or more aspects thereof) described above may be used in combination with each other. Other embodiments may be used, for example, by those skilled in the art upon review of the above description. An abstract is provided to allow the reader to quickly determine the nature of the technical disclosure. It should be understood that this document is not intended to interpret or limit the scope or meaning of the claims. Furthermore, in the detailed description above, various features may be grouped together to simplify this disclosure. This should not be construed as meaning that unclaimed disclosed features are essential to any claim. Rather, the subject matter of the invention may reside in fewer than all features of a particular disclosed embodiment. Therefore, the following claims are incorporated herein by way of example or embodiment, wherein each claim is an independent, separate embodiment, and these embodiments are contemplated to be combined with each other in various combinations or arrangements. The scope of the invention should be determined by reference to the appended claims and the full scope of their equivalents.

Claims

1. A method comprising: The test signal is received from the device under test (DUT) at the input node of the comparator. An intermediate output signal is generated in the first signal path of the comparator based on the relationship between the test signal from the DUT and the comparator reference signal. A DC-coupled signal is provided in the second signal path of the comparator based on the relationship between the test signal from the DUT and the comparator reference signal; The DC coupling signal is used to generate an AC coupling correction signal, which is complementary to a portion of the received test signal; and A corrected output signal is provided based on the combination of the intermediate output signal and the correction signal.

2. The method of claim 1, wherein generating the correction signal comprises processing the test signal received from the DUT using a filter, wherein the filter is configured to compensate for conductor path loss between the DUT and the input node.

3. The method of claim 1, wherein generating the correction signal comprises applying a signal filter to a test signal received from the DUT, wherein the time constant characteristic of the signal filter is based on the load characteristics of the signal path coupled to the input node of the comparator.

4. The method of claim 1, wherein generating the correction signal comprises processing the test signal received from the DUT using a gain stage and a shaping filter.

5. The method of claim 1, wherein providing the DC coupling signal comprises: The transconductance stage receives the test signal from the DUT and generates the corresponding DC coupling residue, and the gain stage processes the DC coupling residue to provide the DC coupling signal.

6. The method of claim 5, wherein generating the DC coupling residual comprises: Update the bias signal or AC coupling characteristics of the differential pair circuit; and The differential pair circuit is used to process the test signals from the DUT.

7. The method of claim 5, further comprising changing the amplitude of the DC coupling residual in the gain stage.

8. The method of claim 7, further comprising receiving information about the DUT and, based on the received information about the DUT, changing the amplitude of the DC coupling residual in the gain stage.

9. The method of claim 5, wherein providing the DC coupling signal further comprises filtering the DC coupling signal to extract the AC component of the load characteristics of the signal path at the input node of the comparator.

10. The method of claim 1, wherein generating the intermediate output signal includes using a differential pair circuit to provide information about the relationship between the test signal and the comparator reference signal.

11. A system for monitoring information from a device under test (DUT), the system comprising: The DUT input node is configured to receive test signals from the DUT via a first signal path; A comparator circuit, coupled to the input node of the DUT, is configured to generate an intermediate output signal based on the relationship between the test signal from the DUT and the comparator reference signal; A compensation circuit, coupled to the DUT input node and configured to generate a correction signal to compensate for a portion of the received test signal; and The output circuit is configured to provide a corrected output signal based on a combination of the intermediate output signal and the correction signal.

12. The system of claim 11, wherein the output circuit is configured to add the intermediate output signal to the correction signal to provide the corrected output signal.

13. The system of claim 11, wherein the compensation circuit includes a shaping filter configured to compensate for the load effect of the first signal path.

14. The system of claim 13, wherein the compensation circuit further includes a gain circuit, and the shaping filter is configured to block the DC component of the output from the gain circuit.

15. The system of claim 13, wherein the compensation circuit further comprises a transconductance stage configured to receive voltage information about the test signal and, in response, provide a corresponding DC coupling current signal to the shaping filter.

16. The system of claim 15 further includes an amplifier circuit configured to change the amplitude characteristics of the current signal supplied to the shaping filter.

17. The system of claim 16, wherein the amplifier circuit is configured to change the amplitude characteristics of the current signal based on information from user input regarding the DUT being tested.

18. The system of claim 15, further comprising an adjustable bias circuit for the transconductance stage, wherein, The amplitude of the current signal depends on the bias conditions set by the adjustable bias circuit to suit the DUT being tested.

19. A testing system, comprising: The first differential pair circuit is configured to generate an intermediate output signal based on the relationship between the test signal received from the device under test (DUT) and the reference signal. A path loading compensation circuit is configured to generate an AC-coupled correction signal that is complementary to a portion of the received test signal, wherein the compensation circuit includes a transconductance stage configured to provide a DC-coupled intermediate signal to a gain stage, and a signal shaping filter stage configured to provide a correction signal based on an output signal from the gain stage. and The output circuit is configured to provide a corrected output signal based on a combination of the intermediate output signal and the correction signal.

20. The test system of claim 19, wherein the gain stage is configured to receive a control signal indicating the desired amplitude characteristics of the correction signal of the DUT being tested.

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