Layout element key information extraction method and terminal

Abstract

The application discloses a kind of layout component key information extraction method and terminal, belong to compound semiconductor layout design and manufacturing technical field, including the following steps: chip feature box information is obtained to the layout is identified and cut groove process layer;Chip size information and position information are obtained according to chip feature box information;Chip is classified and handled according to chip size information;The component key information of each kind of chip is obtained, including feature graphic information and coordinate point information.The application obtains chip feature box information, chip size information and position information in turn, and classified and handles chip, and then obtains the component key information contained in each kind of chip, i.e. Information such as component type, size and position distribution, to realize the efficient processing of layout component information, which can provide information reference and guidance for process optimization.

Description

Technical Field

[0001] This invention relates to the field of compound semiconductor layout design and manufacturing technology, and in particular to a method and terminal for extracting key information of layout components. Background Technology

[0002] Compound semiconductor circuits, taking group III / V gallium arsenide and gallium nitride compound semiconductors as examples, possess advantages such as high current density, high operating frequency, and high output power density, making them particularly suitable for radio frequency microwave circuits and systems. With the continuous improvement of compound semiconductor integrated circuit technology, monolithic microwave integrated circuits (MMICs) are gradually being widely adopted. However, traditional single-function circuits are no longer sufficient to meet application requirements, and the integration requirements of circuits and systems are becoming increasingly stringent. The development trend of integrated circuits is towards multifunctionality, high frequency, high power, high integration, high reliability, and low cost, which places higher demands on integrated circuit manufacturing technology.

[0003] To ensure high repeatability, reliability, and yield in integrated circuit manufacturing processes, the MMIC (Mechanical, Manufacturing, and Microcontroller) layout requires optimization design in the early stages of manufacturing, along with process and circuit design rule checks (DRC) and layout pattern checks (JDV). DRC is a crucial step in achieving the capabilities and limits between design and process. Traditional DRC software is limited to checking limitations such as component appearance, size, spacing, layer definitions, and connection logic. It cannot provide comprehensive statistical information on component types, sizes, and distribution within the layout, nor can it perform further targeted performance statistical analysis on process capabilities and process fluctuations. For compound semiconductor chip R&D and manufacturing, which is still in its nascent stage, this lack of DRC-based information support is insufficient.

[0004] On the other hand, compound integrated circuit manufacturing processes are characterized by both versatility and specialization. Versatility is reflected in the fact that processes such as the 0.25μm GaAs / GaN pHEMT / HEMT process, to meet a wide range of circuit applications, often have relatively large upper and lower limits for the performance parameters (spec), resulting in fluctuations of 5-10% from the target value. Although these performance fluctuations can be incorporated into component models for yield simulation analysis of chip circuits, the target values ​​are usually defined for specific component sizes and cannot accurately cover a wide range of component size variations. The situation worsens when the component sizes used in the chip circuit deviate from these specific values; for example, a performance error of 15% in a small capacitor would cause its application in the millimeter-wave band to deviate significantly from the target design. The specialization of compound integrated circuit manufacturing is reflected in the fact that, compared to the large-scale mass production and high-yield manufacturing processes of silicon, the demand for compound integrated circuits is smaller. It typically requires small-scale customized optimization of specific chip circuits to improve product yield and chip performance. This necessitates first obtaining relevant information about the chip components, including component types, sizes, and distribution, and then performing corresponding statistical analysis to guide further process optimization. In summary, identifying the types, sizes, and distribution of components in the layout is a pressing technical problem that needs to be solved. Summary of the Invention

[0005] The purpose of this invention is to overcome the problems of the prior art and provide a method and terminal for extracting key information of layout components.

[0006] The objective of this invention is achieved through the following technical solution: a method for extracting key information of layout components, the method comprising the following steps:

[0007] Identify the dicing process layer in the layout and obtain chip feature box information;

[0008] Obtain chip size and location information based on chip feature box information;

[0009] Chips are classified according to their size information;

[0010] Obtain key component information for various chips, including feature graphic information and coordinate point information.

[0011] In one example, after obtaining the key component information of various chips, the process further includes:

[0012] Establish a layout component information tree, which includes a multi-level hierarchical directory, and the hierarchical directory includes chip type, component type, and key component information.

[0013] In one example, obtaining the chip feature box information includes:

[0014] Boolean and scaling operations are performed on the dicing process layer to obtain the chip feature box graphic.

[0015] In one example, obtaining the chip feature box information further includes:

[0016] Calculate the coordinate information of the chip based on the feature box graphic.

[0017] In one example, obtaining the chip size information and location information includes:

[0018] The chip size and location information are obtained by using the coordinates of the chip feature box.

[0019] In one example, the classification process for first and second chips of the same size also includes:

[0020] BOOLEAN AND all drawing layers with the second chip frame and set them to the first temporary layer;

[0021] Move the first temporary layer to the origin of the second chip frame coordinates, and then perform a BOOLEAN DIFFERENT operation on the second temporary layer. Determine whether the second temporary layer exists within the range of the first chip. If not, the first chip and the second chip are of the same type; otherwise, the first chip and the second chip are of different types.

[0022] In one example, obtaining key component information for various types of chips includes:

[0023] Select any one chip from each type of chip as a representative chip;

[0024] The Boolean operation is performed between the feature box representing the chip and the device layer to confirm the recognition range. Then, based on the graphic structure features of the component, the feature layer representing the component is obtained, and the coordinate point information of the component is calculated.

[0025] Extract key information about components based on their coordinate points.

[0026] In one example, the extraction of key component information based on the component's coordinate point information includes:

[0027] The appearance of the graphic is determined based on the number of coordinate points, and then it is verified whether the current object being captured is a component. If it is, the key information of the component is extracted; otherwise, the extraction of key information is stopped.

[0028] In one example, after obtaining the key component information of various chips, the process further includes:

[0029] Calculate the extreme value information of the components based on their key information.

[0030] It should be further noted that the technical features corresponding to the above examples can be combined or replaced to form new technical solutions.

[0031] The present invention also includes a storage medium storing computer instructions thereon, which, when executed, perform the steps of the layout component key information extraction method formed by any or more of the above examples.

[0032] The present invention also includes a terminal comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, and the processor executes the steps of the layout component key information extraction method formed by any or more of the above examples when executing the computer instructions.

[0033] Compared with the prior art, the beneficial effects of the present invention are:

[0034] 1. In one example, by sequentially acquiring chip feature box information, chip size information, and location information, and classifying the chips, key information of the components contained in each type of chip can be obtained, namely, information such as component type, size, and location distribution. This enables efficient processing of layout component information and provides information reference and guidance for process optimization. At the same time, by automatically identifying information such as component type, size, and location distribution, this invention supplements the traditional DRC function, which can make up for the shortcomings of manual inspection of layout component information, such as easy omission and low efficiency, and realize the accuracy and batch processing of layout component information.

[0035] 2. In one example, by establishing an information tree, key information of components can be quickly obtained through hierarchical targets, which facilitates the management of a large amount of key information of components, and provides data statistical analysis and management, realizing the informatization and intelligent application of layout component graphic data.

[0036] 3. In one example, secondary classification and identification of chips of the same size can ensure the accuracy of chip classification, thereby extracting key component information of each type of chip without omission, and ensuring the comprehensiveness of key component information extraction.

[0037] 4. In one example, the number of coordinate points is used to further identify the current object being crawled, eliminating some interference items such as layer indentation, thus ensuring the accuracy of extracting key information about the components. Attached Figure Description

[0038] The specific embodiments of the present invention will be further described in detail below with reference to the accompanying drawings, which are used to provide a further understanding of the present application and constitute a part of the present application. The same reference numerals are used in these drawings to denote the same or similar parts. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation of the present application.

[0039] Figure 1 This is a flowchart of a method in an example of the present invention;

[0040] Figure 2 This is a schematic diagram of the chip classification result obtained by secondary classification processing in an example of the present invention;

[0041] Figure 3 This is a schematic diagram of an information tree established in an example of the present invention;

[0042] Figure 4 This is a statistical chart showing the capacitance distribution in an example of the present invention;

[0043] Figure 5 This is a flowchart illustrating a preferred example method of the present invention. Detailed Implementation

[0044] The technical solution of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0045] In the description of this invention, it should be noted that the directions or positional relationships indicated by terms such as "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer" are based on the directions or positional relationships shown in the accompanying drawings. They are used only for the convenience of describing this invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention. Furthermore, the use of ordinal numbers (e.g., "first and second," "first to fourth," etc.) is for distinguishing objects and is not limited to this order, and should not be construed as indicating or implying relative importance.

[0046] In the description of this invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "joining" should be interpreted broadly. For example, they can refer to fixed connections, detachable connections, or integral connections; they can refer to mechanical connections or electrical connections; they can refer to direct connections or indirect connections through an intermediate medium; and they can refer to the internal communication between two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0047] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0048] In one example, such as Figure 1 As shown, a method for extracting key information of components in a layout is described. This method specifically includes the following steps:

[0049] S1: Identify the dicing process layer of the layout and obtain chip feature box information;

[0050] S2: Obtain chip size and location information based on chip feature box information;

[0051] S3: Classify chips based on chip size information;

[0052] S4: Obtain key component information for various chips, including feature graphic information and coordinate point information.

[0053] Specifically, dicing grooves typically define the chip boundaries. Taking GaAs pHEMT process as an example, the dicing process layer is the BS layer. By identifying the BS layer, the chip feature bounding box can be obtained. The chip feature bounding box can characterize the chip's size information, and the chip's position information can be obtained based on the location of the chip feature bounding box. Therefore, in this example, the chip feature bounding box information is first obtained by identifying the layout. The chip feature bounding box information includes its size information and position information.

[0054] Furthermore, different types of chips generally have different sizes. Therefore, chips can be classified by their size information. Chips with the same length and width are of the same type, while those with different lengths and widths are of different types. This is how different types (models) of chips can be distinguished.

[0055] Furthermore, since each type of chip implements the same circuit function, the circuit design of chips of the same type is identical, and the corresponding layout design must also be identical. Based on the chip classification process, by using any chip of the same type as the information extraction object, the key information of the components in the current category of chips can be extracted. Among them, the feature image information in the key information includes the shape, size, and distance from the edge of the component, and the position information includes coordinate information and the number of coordinate points. Based on the shape, size, and number of coordinate points of the component, its category can be determined. The component categories include: active components: transistors, diodes, switching transistors, logic devices, etc.; passive components: transmission lines, inductors, capacitors, resistors, pads, vias, etc.

[0056] In this example, by sequentially acquiring chip feature box information, chip size information, and location information, and classifying the chips, key information about the components contained in each type of chip is obtained, namely, the type, size, and location distribution of the components. This enables efficient processing of layout component information and provides information reference and guidance for process optimization. At the same time, by automatically identifying information such as component type, size, and location distribution, this invention supplements the traditional DRC function, which can overcome the shortcomings of manual inspection of layout component information, such as easy omission and low efficiency, and achieves accurate and batch processing of layout component information.

[0057] As an option, steps S3 and S4 can be executed interchangeably. In this case, the key component information of all chips is obtained first, and then the chips are classified.

[0058] In one example, obtaining chip feature bounding box information includes:

[0059] S11: Perform Boolean and scaling operations on the dicing process layer to obtain the chip feature box pattern. Specifically, when extracting information about each component from a 10000μm x 10000μm layout, during the chip feature box pattern extraction process, the BS layer is subjected to Boolean and AND operations, then enlarged by 100000μm, reduced by 100000μm, and then subjected to Boolean DIFFERENT operations to obtain the chip feature box pattern.

[0060] In one example, after obtaining the chip feature bounding box graphic, the following is also included:

[0061] S12: Calculate the coordinate information of the chip feature bounding box based on the chip feature shape. Specifically, the module containing the chip feature shape is passed into the programming module, the coordinates of all feature shape points are obtained through the position capture function, it is determined whether they are standard rectangular coordinates, and then stored in an array.

[0062] In one example, obtaining chip size and location information includes:

[0063] The chip size and location information are obtained by using the coordinates of the chip feature box. Specifically, key chip parameters are extracted based on the coordinates of the chip feature box; that is, the coordinates of the chip feature box are the corresponding chip coordinates. By combining these coordinates, the length and width dimensions of the chip, as well as the coordinates of each coordinate relative to the chip's center point, can be calculated.

[0064] Furthermore, a complete process layout typically includes a PCM area, which is a specific area for process and control and is not the focus of automatic component identification processing. Therefore, this invention does not identify this area. Specifically, it excludes information identification processing of this area by recognizing unique graphics, thereby reducing the amount of computation and increasing the processing speed.

[0065] In one example, chips of different sizes are different types of chips, while chips of the same size are not necessarily of the same type. Therefore, for the first and second chips of the same size, a secondary classification process is required. That is, for chips with the same length and width dimensions, the dimensions and shapes of all layers within their respective regions are compared to see if they are completely identical. If they are identical, then the two are the same type of chip. The specific steps include:

[0066] S31: AND all drawing layers with the second chip frame using BOOLEAN and then set to the first temporary layer;

[0067] S32: Move the first temporary layer to the origin of the first chip frame coordinate system, with the second chip frame coordinate system origin as the reference point;

[0068] S33: Move the BOOLEAN DIFFERENT operation to the second temporary layer;

[0069] S34: Determine whether a second temporary layer exists within the range of the first chip. If not, the first chip and the second chip are of the same type; otherwise, the first chip and the second chip are of different types. Figure 2 This is a schematic diagram of the chip classification results obtained after secondary classification processing.

[0070] In this example, secondary classification and identification of chips of the same size ensures the accuracy of chip classification and allows for the extraction of key component information from each type of chip without omission, thus guaranteeing the comprehensiveness of the extraction of key component information.

[0071] In one example, obtaining key component information for various types of chips includes:

[0072] S41: Perform calculations on the feature layer of the component to capture the coordinate point information of the component; specifically, select any chip from each type of chip as a representative chip, draw a chip box according to its coordinates, perform a BOOLEAN operation between it and the component layer, confirm the recognition range, capture the feature layer of the representative component according to the structural features of the component, and then obtain its coordinate points. Taking the passive device capacitor of GaAs pHEMT process as an example, in the S12 coordinate group, the first coordinate group (0,0) and (800,800) are used to draw the layer TEMP1. SPN NV2 (the second nitride via layer) is subjected to BOOLEAN AND operation with TEMP1. Then, the results of the two are subjected to SPNNV2OUTSIDE (non-overlapping) operation and then passed to the programming module through CALLBACK. The coordinate points of all feature graphics are captured by the function as (73,91.5), (73,116.5), (103.5,117) and (103.5,91).

[0073] S42: Extract key parameters of feature graphics based on coordinate points. Calculate the shape, size, and distance from the edge of the capacitor device based on the coordinate points. Given the input coordinate group 1, (73,91.5), (73,116.5), (103,116.5), (103,91.5), the device graphic type is calculated to be rectangular, with side lengths of 25μm and 30μm respectively.

[0074] In one example, after extracting key parameters from the feature image, the extreme value information of the component is calculated based on the key information of the component. Specifically, the extreme value information of the component's performance parameters is calculated based on information such as the component's size and shape. For example, in step S42, when the component's side length is obtained as 25μm and 30μm, the area of ​​the capacitor is 750μm. 2 Based on the capacitance density, the capacitance value was calculated to be 0.3075pF, and its distance to the chip edge was calculated to be 73μm. The coordinates of the capacitor center point were (88, 104). Furthermore, the minimum and maximum capacitor areas, the capacitor closest to the edge, and the capacitance density were statistically determined. The capacitor component information is shown in Table 1.

[0075] Table 1 Capacitor Component Information Sheet

[0076]

[0077] In one example, extracting key component information based on the component's coordinates includes:

[0078] The number of coordinate points determines the appearance of the graphic, which then verifies whether the current object being crawled is a component. If so, key component information is extracted; otherwise, extraction stops. Specifically, different processing is applied based on the number of coordinate points. Some interference items, such as layer indentation, are excluded, while irregular and abnormal graphics are retained (without key information extraction). Then, the coordinate points of regular graphics are calculated to obtain information about the component, including but not limited to its size, shape, area, and distance from the chip edge. Based on this, its maximum and minimum values ​​and component distribution density are calculated. In this example, the number of coordinate points is used to further identify the current object being crawled, excluding some interference items, such as layer indentation, ensuring the accuracy of key component information extraction.

[0079] In one example, after obtaining the key component information for various chips, the process also includes:

[0080] S5: Establish a layout component information tree and perform data statistical processing. The established information tree is as follows: Figure 3 As shown, the system consists of hierarchical directories. Chip information (chip type) is the first-level directory, component type is the second-level directory, and key component information is the third-level directory. The key information is extracted through batch processing. Furthermore, statistical analysis can be performed on the data. In this example, taking all capacitors of all chips in the captured layout as an example, the statistical distribution of capacitance values ​​is as follows: Figure 4 As shown. Finally, by analyzing the key information of the components automatically identified and statistically analyzed, the ease or difficulty of manufacturing process can be comprehensively evaluated, and optimization guidance and reference can be provided for the process, realizing the informatization and intelligent application of the graphic data of the component layout.

[0081] Combining the above examples yields preferred examples of the present invention, such as... Figure 5 As shown, the method includes the following steps:

[0082] S1': Identify the dicing process layer of the layout and obtain chip feature box information;

[0083] S2': Obtain chip size and location information based on chip feature box information;

[0084] S3': Classify chips based on chip size information, and perform secondary classification for chips of the same size;

[0085] S4': Obtain key component information for various chips, including feature graphic information and coordinate point information;

[0086] S5': Establish a layout component information tree and perform data statistical processing.

[0087] This application also includes a storage medium having the same inventive concept as the layout component key information extraction method consisting of any or more of the above examples, wherein computer instructions are stored thereon, and the computer instructions execute the steps of the layout component key information extraction method described above when they are run.

[0088] Based on this understanding, the technical solution of this embodiment, or the part that contributes to the prior art, or a part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of the present invention. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0089] This application also includes a terminal having the same inventive concept as the layout component key information extraction method comprising any or more of the above examples, including a memory and a processor. The memory stores computer instructions executable by the processor, and the processor executes the steps of the layout component key information extraction method described above when executing the computer instructions. The processor may be a single-core or multi-core central processing unit or a specific integrated circuit, or one or more integrated circuits configured to implement the present invention.

[0090] In the embodiments provided by the present invention, each functional unit can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0091] The above detailed embodiments are a description of the present invention. It should not be considered that the specific embodiments of the present invention are limited to these descriptions. For those skilled in the art, several simple deductions and substitutions can be made without departing from the concept of the present invention, and all of these should be considered to fall within the protection scope of the present invention.

Claims

1. A method for extracting key information of components in a layout, characterized in that: It includes the following steps: Identify the dicing process layer in the layout and obtain chip feature box information; Obtain chip size and location information based on chip feature box information; Chips are classified according to their size information; Obtain key component information for various chips, including feature graphic information and coordinate point information; For the first and second chips of the same size, the classification process also includes: BOOLEAN AND all drawing layers with the second chip frame and set them to the first temporary layer; Move the first temporary layer to the origin of the second chip frame coordinates, then use the BOOLEANDIFFERENT operation to move it to the second temporary layer. Determine if the second temporary layer exists within the range of the first chip. If not, the first chip and the second chip are of the same type; otherwise, the first chip and the second chip are of different types.

2. The method for extracting key information of layout components according to claim 1, characterized in that: After obtaining the key component information of various chips, the process also includes: Establish a layout component information tree, which includes a multi-level hierarchical directory, and the hierarchical directory includes chip type, component type, and key component information.

3. The method for extracting key information of layout components according to claim 1, characterized in that: The acquisition of chip feature box information includes: Boolean and scaling operations are performed on the dicing process layer to obtain the chip feature box graphic.

4. A method for extracting key information of layout components according to claim 1 or 3, characterized in that: The acquisition of chip feature box information also includes: Calculate the coordinate information of the chip based on the feature box graphic.

5. The method for extracting key information of layout components according to claim 4, characterized in that: The acquisition of chip size and location information includes: The chip size and location information are obtained by using the coordinates of the chip feature box.

6. The method for extracting key information of layout components according to claim 1, characterized in that: The key component information for various types of chips obtained includes: Select any one chip from each type of chip as a representative chip; The Boolean operation is performed between the feature box representing the chip and the device layer to confirm the recognition range. Then, based on the graphic structure features of the component, the feature layer representing the component is obtained, and the coordinate point information of the component is calculated. Extract key information about components based on their coordinate points.

7. The method for extracting key information of layout components according to claim 6, characterized in that: The extraction of key component information based on the component's coordinate point information includes: The appearance of the graphic is determined based on the number of coordinate points, and then it is verified whether the current object being captured is a component. If it is, the key information of the component is extracted; otherwise, the extraction of key information is stopped.

8. The method for extracting key information of layout components according to claim 1, characterized in that: After obtaining the key component information of various chips, the process also includes: Calculate the extreme value information of the components based on their key information.

9. A terminal comprising a memory and a processor, wherein the memory stores computer instructions executable on the processor, characterized in that: When the processor executes the computer instructions, it performs the steps of the layout component key information extraction method according to any one of claims 1-8.

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