A method for manufacturing a long-wavelength VCSEL and a structure

Abstract

The application relates to the field of semiconductor devices and provides a preparation method of a long-wavelength VCSEL, which comprises the following steps: sequentially laminating and growing an N-InP buffer layer, a bottom DBR structure and an N-InP space layer on an N-InP substrate to form a first epitaxial wafer; taking out the first epitaxial wafer, taking photoresist as a mask, injecting H ions into the N-InP space layer by using an ion implantation technology, further passivating part of the N-InP space layer to form a passivation area, and forming a light-emitting area by the unpassivated N-InP space layer; removing the mask to obtain a second epitaxial wafer; annealing the second epitaxial wafer and cleaning the surface; sequentially laminating and growing a P-InAlAs space layer, a quantum well area, an N-InAlAs space layer and a top DBR structure on the N-InP space layer of the second epitaxial wafer to form a third epitaxial wafer; and preparing the third epitaxial wafer by using a conventional optoelectronic device preparation method to obtain a long-wavelength VCSEL device. The process is simple.

Description

Technical Field

[0001] This invention relates to the field of semiconductor devices, and specifically to a method and structure for fabricating a long-wavelength VCSEL. Background Technology

[0002] A VCSEL (Vertical Cavity Surface Emitting Laser) is a semiconductor laser diode developed based on semiconductor materials such as gallium arsenide. VCSELs differ from other light sources such as LEDs (Light Emitting Diodes) and LDs (Laser Diodes). Unlike traditional edge-emitting lasers, VCSELs emit high-power optical laser beams vertically from their top surface. They offer advantages such as small size, circular output spot, natural 2D structured light, single longitudinal mode output, low threshold current, wide operating temperature range, low cost, and easy integration into large-area arrays. They are widely used in optical communication, optical interconnects, and optical storage.

[0003] Although VCSELs have made significant progress as core components in 3D imaging and sensing systems across various fields, the fabrication and development of long-wavelength VCSELs, such as those at 1310nm and 1550nm, still face considerable challenges. For instance, most methods for fabricating long-wavelength VCSELs employ the buried tunnel junction method. Since this method requires secondary epitaxy, it increases the complexity of the fabrication process and reduces the yield rate of long-wavelength VCSELs. Summary of the Invention

[0004] This application provides a method and structure for fabricating long-wavelength VCSELs, which solves the problems of complex processing technology and low yield of current long-wavelength VCSEL devices.

[0005] The first aspect of this application provides a method for fabricating a long-wavelength VCSEL, comprising:

[0006] On a pre-placed N-InP substrate, an N-InP buffer layer, a bottom DBR structure, and an N-InP space layer are sequentially stacked to form the first epitaxial wafer;

[0007] Take out the first epitaxial wafer, use photoresist as a mask, and use ion implantation technology to implant H ions into the N-InP space layer, thereby passivating part of the N-InP space layer to form a passivation region. The unpassivated N-InP space layer forms a light-emitting region.

[0008] Remove the mask to obtain the second epitaxial wafer;

[0009] The second epitaxial wafer undergoes annealing and surface cleaning.

[0010] A third epitaxial wafer is formed by sequentially stacking a P-InAlAs space layer, a quantum well region, an N-InAlAs space layer, and a top DBR structure on the N-InP space layer of the second epitaxial wafer.

[0011] Using conventional optoelectronic device fabrication methods, trenches are etched on the third epitaxial wafer, and an upper electrode is fabricated on the top of the third epitaxial wafer, while a lower electrode is fabricated on the bottom of the third epitaxial wafer, to obtain a long-wavelength VCSEL device.

[0012] In one feasible embodiment, the step of sequentially growing an N-InP buffer layer, a bottom DBR structure, and an N-InP space layer on a pre-placed N-InP substrate to form a first epitaxial wafer includes:

[0013] An N-InP buffer layer, a bottom DBR structure, and an N-InP space layer are sequentially grown on the N-InP substrate using a molecular beam epitaxy apparatus to form a first epitaxial wafer.

[0014] The process of sequentially stacking and growing a P-InAlAs space layer, a quantum well region, an N-InAlAs space layer, and a top DBR structure on the N-InP space layer of the second epitaxial wafer to form a third epitaxial wafer includes:

[0015] A third epitaxial wafer is formed by sequentially growing a P-InAlAs space layer, a quantum well region, an NI nAlAs space layer, and a top DBR structure on the NI nP space layer of the second epitaxial wafer using a molecular beam epitaxy (MBE) apparatus.

[0016] In one feasible embodiment, the step of sequentially stacking and growing an NI nP buffer layer, a bottom DBR structure, and an NI nP space layer on a pre-placed NI nP substrate to form a first epitaxial wafer includes:

[0017] The NI nP buffer layer is grown on a pre-placed NI nP substrate;

[0018] The bottom DBR structure is grown on the NI nP buffer layer;

[0019] The NI nP space layer is grown on the bottom DBR structure.

[0020] In one possible implementation, the bottom DBR structure comprises an N-type InAlAs / InGaAlAs DBR structure;

[0021] The process of growing the bottom DBR structure on the NI nP buffer layer includes:

[0022] N-type InAlAs DBR structures and N-type InGaAlAs DBR structures are periodically grown on the NI nP buffer layer, wherein the period is 30-50.

[0023] In one possible implementation, the third epitaxial wafer is formed by sequentially stacking and growing a PI nAlAs space layer, a quantum well region, an NI nAlAs space layer, and a top DBR structure on the NI nP space layer of the second epitaxial wafer, comprising:

[0024] The PI nAlAs space layer is grown on the NI nP space layer of the second epitaxial wafer;

[0025] The quantum well region is grown on the PI nAlAs space layer;

[0026] A Ni nAlAs space layer is grown on the quantum well region;

[0027] The top DBR structure is grown on the NI nAlAs space layer.

[0028] In one possible implementation, the top DBR structure comprises an N-type InAlAs / InGaAlAs DBR structure;

[0029] The growth of the top DBR structure on the Ni nAlAs space layer includes:

[0030] N-type InAlAs DBR structures and N-type InGaAlAs DBR structures are periodically grown on the InAlAs space layer, wherein the period is 30-50; the bottom DBR structure and the top DBR structure form a reflector.

[0031] In one possible implementation, the NI nP space layer includes a passivation region and heavily doped N. + -I nP and P + -I nP;

[0032] The process of using photoresist as a mask and employing ion implantation technology to implant H ions into the NI nP space layer, and passivating a portion of the NI nP space layer, includes:

[0033] The heavily doped N₂ is grown sequentially on the bottom DBR structure. + -I nP and P + -I nP, so as to form a tunnel junction layer on the bottom DBR structure;

[0034] In P +The photoresist is coated onto the N-type substrate, and the photoresist is irradiated according to the mask, so that the N-type substrate... + -I nP and the P + -I nP passivation forms a passivation region, wherein, apart from the passivation region, the N + -I nP and the P + -I nP forms the luminescent region.

[0035] In one possible implementation, before removing the first epitaxial wafer, the following steps are included:

[0036] The first epitaxial wafer is fabricated into a circle with a diameter of 10 to 100 μm using photolithography.

[0037] In one possible implementation, the annealing treatment of the second epitaxial wafer and the cleaning of the surface include:

[0038] After the second epitaxial wafer is annealed, the surface of the second epitaxial wafer is sequentially cleaned with acetone, alcohol, and deionized water.

[0039] A second aspect of this application provides a structure for a long-wavelength VCSEL applied to the aforementioned method, the structure comprising:

[0040] A pre-placed NI nP substrate;

[0041] The NI nP buffer layer is grown on the NI nP substrate;

[0042] The bottom DBR structure is grown on the NI nP buffer layer;

[0043] NI nP space layer, grown on the underlying DBR structure;

[0044] A PI nAlAs space layer is grown on the NI nP space layer;

[0045] Quantum well regions are grown on the PI nAlAs space layer;

[0046] A NI nAlAs space layer is grown on the quantum well region;

[0047] The top DBR structure is grown on the Ni nAlAs space layer;

[0048] The lower electrode is used to grow the NI nP substrate on the side opposite to the NI nP buffer layer.

[0049] The upper electrode is grown on the side of the top DBR structure opposite to the Ni nAlAs space layer; wherein,

[0050] The NI nP space layer includes a passivation region and a light-emitting region, with the light-emitting region located at the center of the passivation region.

[0051] Beneficial effects of this invention:

[0052] This invention provides a method and structure for fabricating a long-wavelength VCSEL. A first epitaxial wafer is formed by sequentially stacking an NI nP buffer layer, a bottom DBR structure, and an NI nP space layer on a pre-placed NI nP substrate. Using photoresist as a mask, H ions are implanted into the NI nP space layer using ion implantation technology, and a portion of the N-InP space layer is passivated to form a passivation region. The unpassivated NI nP space layer forms the light-emitting region. Next, the mask is removed to obtain a second epitaxial wafer. The second epitaxial wafer is annealed and its surface is cleaned. Then, a PI nAlAs space layer, a quantum well region, another NI nAlAs space layer, and a top DBR structure are sequentially stacked on the NI nP space layer of the second epitaxial wafer to form a third epitaxial wafer. Finally, using conventional optoelectronic device fabrication methods, trenches are etched on the third epitaxial wafer, and a top electrode is fabricated on the top and a bottom electrode is fabricated on the bottom of the third epitaxial wafer to obtain a long-wavelength VCSEL device. The above method utilizes material deposition and selective etching passivation to replace the direct etching method for fabricating surface gratings. This avoids the stringent requirements of single-material etching on etching parameters and improves the morphology quality after etching. It also reduces the dependence of long-wavelength VCSEL fabrication methods on growth processes and equipment, lowers the process threshold, and improves fabrication efficiency. Attached Figure Description

[0053] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0054] Figure 1 This is a flowchart illustrating a method for fabricating a long-wavelength VCSEL according to this application;

[0055] Figure 2 This is a schematic diagram of the structure of a long-wavelength VCSEL according to this application.

[0056] Figure label:

[0057] 1-NI nP substrate; 2-NI nP buffer layer; 3-Bottom DBR structure; 4-NI nP space layer; 41-N + -I nP; 42-passivation region; 43-P+ -I nP; 5-PI nAlAs space layer; 6-Quantum well region; 7-NI nAlAs space layer; 8-Top DBR structure; 9-Lower electrode; 10-Upper electrode. Detailed Implementation

[0058] The technical solution of the present invention will be clearly and completely described below with reference to the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0059] In the description of this invention, it should be understood that the terms "center," "longitudinal," "lateral," "length," "width," "thickness," "upper," "lower," "front," "rear," "left," "right," "vertical," "horizontal," "top," "bottom," "inner," "outer," "clockwise," and "counterclockwise," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing this invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on this invention.

[0060] Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the stated features. In the description of this invention, "a plurality of" means two or more, unless otherwise explicitly specified. Furthermore, the terms "installed," "connected," and "linked" should be interpreted broadly; for example, they may refer to a fixed connection, a detachable connection, or an integral connection; they may refer to a mechanical connection or an electrical connection; they may refer to a direct connection or an indirect connection through an intermediate medium; and they may refer to the internal connection of two components. Those skilled in the art can understand the specific meaning of the above terms in this invention based on the specific circumstances.

[0061] To facilitate understanding of the technical solution of this application, some concepts involved in this application will be explained first below.

[0062] DBR, Distributed Bragg Ref lector, refers to the resonant cavity formed in a VCSEL type laser.

[0063] Epi-ready refers to a pre-prepared substrate that is ready for immediate use.

[0064] Molecular beam epitaxy (MBE) is a physical deposition technique for compound semiconductor multilayer thin films. In MBE, under ultra-high vacuum conditions, the elements constituting the thin film are heated in their respective molecular beam furnaces to form oriented molecular beams, which are then incident onto a heated substrate to grow the film.

[0065] With the development of IoT, AI, and 5G technologies, 3D imaging and sensing technologies have experienced rapid growth, not only driving the development of multiple fields such as smartphones, AR / VR, and smart cars, but also accelerating the arrival of the era of the Internet of Everything. Among these, VCSELs, as core devices in 3D imaging and sensing systems, are at the pinnacle of the smart interconnected industry. Currently, short-wavelength infrared VCSELs based on gallium arsenide substrates, such as those with wavelengths of 850nm and 980nm, have seen significant development and widespread application. They have played a crucial role in the research and application of VCSELs in these wavelength bands. However, in the fabrication and development of long-wavelength VCSELs, such as those with wavelengths of 1310nm and 1550nm, the fabrication and development of DBRs (Dielectric-to-Body-Jet) junctions are challenging due to difficulties in fabricating them and achieving current limiting. Therefore, the fabrication process for long-wavelength VCSELs mostly employs the buried tunnel junction method. This method increases the complexity of the fabrication process for long-wavelength VCSEL devices, leading to low yield rates and consequently high prices, hindering the widespread adoption of long-wavelength VCSELs.

[0066] In view of this, see Figure 1 This application provides a method for fabricating a long-wavelength VCSEL, comprising the following steps:

[0067] S100: On a pre-placed NI nP substrate, an NI nP buffer layer, a bottom DBR structure, and an NI nP space layer are sequentially stacked to form the first epitaxial wafer.

[0068] The pre-placed NI nP substrate is an epi-ready NI nP substrate, and then the outer edge growth is performed on the NI nP substrate using a molecular beam outer edge (MBE) device.

[0069] Specifically, an N-InP buffer layer is grown on an epi-ready NI nP substrate using a molecular beam edge spectrometer; next, a bottom DBR structure is grown on the NI nP buffer layer; finally, an NI nP space layer is grown on the bottom DBR structure to form the first epitaxial wafer.

[0070] It should be noted that NI nP is N-type indium phosphide, meaning that the NI nP substrate is an N-type indium phosphide substrate; the N-InP buffer layer is an N-type indium phosphide buffer layer; and the NI nP space layer is an N-type indium phosphide space layer. The thicknesses of the NI nP substrate, N-InP buffer layer, bottom DBR structure, and NI nP space layer can be set as needed, and this application does not impose any limitations on them.

[0071] Among them, the bottom DBR structure includes the N-type InAlAs / InGaAlAs DBR structure.

[0072] The step of growing the base DBR structure on the NI nP buffer layer includes periodically growing N-type InAlAs DBR structures and N-type InGaAlAs DBR structures on the NI nP buffer layer, wherein the period is 30-50. For example, N-type InAlAs DBR structures, N-type InGaAlAs DBR structures, N-type InAlAs DBR structures, N-type InGaAlAs DBR structures, N-type InGaAlAs DBR structures, N-type InAlAs DBR structures, and N-type InGaAlAs DBR structures are sequentially stacked on the NI nP buffer layer to form periodic growth, and the growth period on the N-InP buffer layer can be 30-50. Preferably, the growth period on the NI nP buffer layer is 40 times. The period of periodic growth of the N-type InAlAs DBR structures and N-type InGaAlAs DBR structures on the N-InP buffer layer can be set as needed, and this application does not limit it.

[0073] Among them, the N-type InAlAs DBR structure is the N-type indium aluminum arsenide DBR structure, and the N-type InGaAlAs DBR structure is the N-type DBR structure.

[0074] It should also be noted that when an NI nP buffer layer is grown on an NI nP substrate, since they have the same chemical composition, and when the bottom DBR structure grown on the NI nP buffer layer is an N-type InAlAs / InGaAlAs DBR structure, the NI nP buffer layer and the N-type InAlAs / InGaAlAs DBR structure have the same elemental composition, the lattice mismatch between the NI nP substrate and the bottom DBR structure can be effectively reduced.

[0075] The NI nP space layer is used to form the light-emitting channel of the long-wavelength VCSEL on the bottom DBR structure.

[0076] S200: Take out the first epitaxial wafer, use photoresist as a mask, and use ion implantation technology to implant H ions into the NI nP space layer, thereby passivating part of the NI nP space layer to form a passivation region. The unpassivated NI nP space layer forms the light-emitting region.

[0077] The NI nP space layer may include passivation regions and heavily doped N. + -I nP and P + -I nP. Specifically, N + -InP and P + -I nP grows in successive layers on the bottom DBR structure to form tunnel layers on the bottom DBR structure.

[0078] In some embodiments, after removing the first epitaxial wafer, photoresist is applied to the first epitaxial wafer, that is, on the P... + - Photoresist is coated onto the NI nP. Next, a pre-placed mask is placed on the photoresist. Using ion implantation technology, H ions are implanted into the NI nP spaced layer. The H ions pass through the mask and strike the photoresist, forming an etching effect on the photoresist, thus completing the etching of the heavily doped N. + -I nP and P + -I nP passivation, thereby forming a passivation region. Specifically, the N-doped N-type nanoparticles on the NI nP space layer of the first epitaxial wafer... + -InP and P + The passivated region of -I nP forms a non-luminescent region, while the unpassivated region is heavily doped N. + -I nP and P + -I nP is the luminescent region.

[0079] By using ion implantation technology to passivate the NI nP space layer, the surface of the passivation region of the NI nP space layer is made smooth. This facilitates the subsequent growth of other structures on the surface of the passivation region. In addition, the smooth surface of the NI nP space layer using ion implantation technology eliminates the need for secondary epitaxy of the NI nP space layer, reducing the complexity of the fabrication process. This reduction in fabrication process complexity increases the yield of the final long-wavelength VCSEL device.

[0080] For example, the edges of the NI nP space layer are passivated so that the passivation area is annular in shape, and the center surrounded by the passivation area forms the light-emitting area. In this way, the light emitted from the light-emitting area can be prevented from passing out through the edge of the NI nP space layer, causing light leakage. In addition, this NI nP space layer structure with the light-emitting area as the center and the passivation edge can also enable light to propagate between the bottom DBR structure and the top DBR structure, thereby improving the light emission effect of the light-emitting area.

[0081] S300: Remove the mask to obtain the second epitaxial wafer.

[0082] In this process, after the passivation region is formed in the NI nP space layer, the mask is removed to obtain the second epitaxial wafer.

[0083] S400: Annealing treatment of the second epitaxial wafer and cleaning of the surface.

[0084] In this process, the second epitaxial wafer is placed in an oven for annealing. For example, the second epitaxial wafer can be placed in an oven equipped with a halogen infrared lamp, using the halogen infrared lamp as a heat source. Through an extremely rapid heating rate, the second epitaxial wafer is heated to 300℃-1200℃ in a very short time, eliminating defects inside the second epitaxial wafer, activating the doped elements in the second epitaxial wafer, and thus improving product performance.

[0085] Further, after annealing, the second epitaxial wafer is removed and its surface is cleaned. The cleaning method may include acetone cleaning, alcohol cleaning, and deionized water cleaning. For example, the annealed second epitaxial wafer is sequentially cleaned with acetone, alcohol, and deionized water to remove impurities and oil from its surface, facilitating subsequent processing.

[0086] S500: A third epitaxial wafer is formed by sequentially stacking a PI nAlAs space layer, a quantum well region, a NI nAlAs space layer, and a top DBR structure on the NI nP space layer of the second epitaxial wafer.

[0087] After the second epitaxial wafer is cleaned, it is placed in a molecular beam epitaxy (MBE) apparatus. The MBE apparatus is used to sequentially grow a PI nAlAs spatial layer, a quantum well region, an NI nAlAs spatial layer, and a top DBR structure on the second epitaxial wafer to form a third epitaxial wafer.

[0088] Specifically, a PI nAlAs spatial layer is grown on the NI nP spatial layer of the second epitaxial wafer using a molecular beam edge detection device; next, a quantum well region is grown on the PI nAlAs spatial layer; then, an NI nAlAs spatial layer is grown on the quantum well region; finally, a top DBR structure is grown on the NI nAlAs spatial layer to obtain the third epitaxial wafer.

[0089] It should be noted that the PI nAlAs space layer is a P-type indium aluminum arsenide. The PI nAlAs space layer has two functions. First, it can serve as an optical waveguide structure, that is, as a light propagation channel. Second, the P-InAlAs space layer can be used to adjust the overall thickness of long-wavelength VCSEL devices. In other words, the thickness of the PI nAlAs space layer can be adjusted as needed, thereby adjusting the overall thickness of long-wavelength VCSEL devices.

[0090] The role of the quantum well region is to form electron-hole vacancies.

[0091] The NI nAlAs space layer is an N-type indium aluminum arsenide. The NI nAlAs space layer has two functions. First, it can serve as an optical waveguide structure, that is, as a light propagation channel. Second, it can be used to adjust the overall thickness of long-wavelength VCSEL devices. The function of the NI nAlAs space layer is the same as that of the PI nAlAs space layer, and will not be repeated here.

[0092] Top-level DBR structures may include N-type InAlAs / InGaAlAs DBR structures.

[0093] The step of growing the top DBR structure on the NI nAlAs spatial layer includes periodically growing N-type InAlAs DBR structures and N-type InGaAlAs DBR structures on the NI nAlAs spatial layer, with a period of 30-50. The bottom DBR structure and the top DBR structure form a reflector. For example, N-type InAlAs DBR structures, N-type InGaAlAs DBR structures, N-type InAlAs DBR structures, N-type InGaAlAs DBR structures, N-type InAlAs DBR structures, and N-type InGaAlAs DBR structures are sequentially stacked on the NI nAlAs spatial layer, and the growth period on the NI nAlAs spatial layer can be 30-50, preferably 40 times. The period of periodically growing the N-type InAlAs DBR structures and N-type InGaAlAs DBR structures on the NI nAlAs spatial layer can be set as needed, and this application does not limit it.

[0094] S600: Using conventional optoelectronic device fabrication methods, trenches are etched on the third epitaxial wafer, and an upper electrode is fabricated on the top of the third epitaxial wafer and a lower electrode is fabricated on the bottom of the third epitaxial wafer to obtain a long-wavelength VCSEL device.

[0095] The method utilizes conventional optoelectronic device fabrication methods, such as conventional LED fabrication methods. Trenches are etched on a third epitaxial wafer. Next, exemplarily, upper and lower electrodes are formed at the top and bottom of the third epitaxial wafer, respectively, by evaporation or thermal evaporation. Further, the upper electrode can be a p-type electrode, and the lower electrode can be an n-type electrode. It should be noted that the LED fabrication method can be a conventional LED fabrication method.

[0096] Once the upper and lower electrodes are fabricated on the third epitaxial wafer, a long-wavelength VCSEL device can be obtained.

[0097] In one embodiment, before removing the first epitaxial wafer, the first epitaxial wafer is prepared into a circle with a diameter of 10 to 100 μm using photolithography. Preferably, the first epitaxial wafer is one of 10 μm, 20 μm, 30 μm, 40 μm, 50 μm, 60 μm, 70 μm, 80 μm, 90 μm or 100 μm. This size of first epitaxial wafer facilitates subsequent processing.

[0098] See Figure 2 This application also provides a long-wavelength VCSEL structure for application in the aforementioned method. The long-wavelength VCSEL structure includes: an NI nP substrate 1, an NI nP buffer layer 2, a bottom DBR structure 3, an NI nP space layer 4, a NI nAlAs space layer 5, a quantum well region 6, an NI nAlAs space layer 7, a top DBR structure 8, a lower electrode 9, and an upper electrode 10.

[0099] Specifically, an NI nP substrate 1 is pre-formed; an NI nP buffer layer 2 is grown on the NI nP substrate 1; a bottom DBR structure 3 is grown on the NI nP buffer layer 2; an NI nP space layer 4 is grown on the bottom DBR structure 3; a PI nAlAs space layer 5 is grown on the NI nP space layer 4; a quantum well region 6 is grown on the PI nAlAs space layer 5; an NI nAlAs space layer 7 is grown on the quantum well region 6; a top DBR structure 8 is grown on the NI nAlAs space layer 7; a lower electrode 9 is grown on the side of the NI nP substrate 1 opposite to the NI nP buffer layer 2; and an upper electrode 10 is grown on the side of the top DBR structure 8 opposite to the NI nAlAs space layer 7.

[0100] The NI nP space layer 4 includes a passivation region 42 and a light-emitting region, with the light-emitting region located at the center of the passivation region 42. Specifically, the light-emitting region includes heavily doped N₂. + -I nP 41 and P + -I nP 42, heavily doped N + -I nP 41 and P + -I nP 42 grows sequentially on the bottom DBR structure 3.

[0101] In summary, the long-wavelength VCSEL fabrication method provided in this application utilizes proton implantation technology to smooth the surface of the first epitaxial wafer, thus avoiding the secondary epitaxy required for VCSEL device fabrication. This application obtains a second epitaxial wafer by processing the first epitaxial wafer, then grows a third epitaxial wafer from the second epitaxial wafer, and finally processes the third epitaxial wafer using conventional LED fabrication methods to obtain the VCSEL device.

[0102] This application employs a method combining material deposition and selective etching to replace the traditional direct etching method for fabricating surface gratings. Selective etching avoids the stringent requirements on etching parameters inherent in single-material etching, thereby improving the morphology quality after etching. It also reduces the dependence of the fabrication method on growth processes and equipment, lowering the process threshold and increasing fabrication efficiency.

[0103] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method of fabricating a long wavelength VCSEL, the method comprising: The method comprises the following steps: ​ a first epitaxial wafer is formed by sequentially growing a N-InP buffer layer, a bottom DBR structure and a N-InP spacer layer on a preset N-InP substrate; the first epitaxial wafer is taken out, photoresist is used as a mask, H ions are injected into the N-InP spacer layer by using an ion implantation technology, and part of the N-InP spacer layer is passivated to form a passivation region, and the N-InP spacer layer which is not passivated forms a light-emitting region; the mask is removed to obtain a second epitaxial wafer; the second epitaxial wafer is annealed and the surface is cleaned; a third epitaxial wafer is formed by sequentially growing a P-InAlAs spacer layer, a quantum well region, an N-InAlAs spacer layer and a top DBR structure on the N-InP spacer layer of the second epitaxial wafer; a long-wavelength VCSEL device is obtained by etching a groove on the third epitaxial wafer and manufacturing an upper electrode on the top of the third epitaxial wafer and a lower electrode on the bottom of the third epitaxial wafer by using a conventional photoelectric device manufacturing method. The N-InP spatial layer includes a passivation region, and a heavily doped N + - InP and P + - InP; The method of injecting H ions into the N-InP spacer layer by using the ion implantation technology and passivating part of the N-InP spacer layer with the photoresist as the mask comprises the following steps: stacked on the bottom DBR structure are the heavily doped N + - InP and P + - InP, so as to form a tunnel junction layer on the bottom DBR structure; InP + - applying said photoresist on said InP, irradiating said photoresist according to said mask, removing said photoresist, and removing said N + - applying said photoresist on said InP and said P + - passivating said InP, forming a passivation region, wherein said N + - applying said photoresist on said InP and said P + - forming a light emitting region in said InP; Before the first epitaxial wafer is taken out, the method comprises the following steps: The first epitaxial wafer is prepared into a circle with a diameter of 10-100 um by using a photoetching technology.

2. The method of claim 1, wherein, The method of sequentially growing a N-InP buffer layer, a bottom DBR structure and a N-InP spacer layer on a preset N-InP substrate to form a first epitaxial wafer comprises the following steps: The first epitaxial wafer is formed by sequentially growing a N-InP buffer layer, a bottom DBR structure and a N-InP spacer layer on the N-InP substrate by using a molecular beam epitaxy device. The method of sequentially growing a P-InAlAs spacer layer, a quantum well region, an N-InAlAs spacer layer and a top DBR structure on the N-InP spacer layer of the second epitaxial wafer to form a third epitaxial wafer comprises the following steps: The third epitaxial wafer is formed by sequentially growing a P-InAlAs spacer layer, a quantum well region, an N-InAlAs spacer layer and a top DBR structure on the N-InP spacer layer of the second epitaxial wafer by using a molecular beam epitaxy device.

3. The method of claim 1, wherein, The method of sequentially growing a N-InP buffer layer, a bottom DBR structure and a N-InP spacer layer on a preset N-InP substrate to form a first epitaxial wafer comprises the following steps: The N-InP buffer layer is grown on the preset N-InP substrate; The bottom DBR structure is grown on the N-InP buffer layer; The N-InP spacer layer is grown on the bottom DBR structure.

4. The method according to claim 3, wherein The bottom DBR structure comprises an N-type InAlAs / InGaAlAs DBR structure; The method of growing the bottom DBR structure on the N-InP buffer layer comprises the following steps: The N-type InAlAs DBR structure and the N-type InGaAlAs DBR structure are periodically grown on the N-InP buffer layer, and the period is 30-50.

5. The method of claim 1, wherein, The P-InAlAs spacer layer, the quantum well region, the N-InAlAs spacer layer and the top DBR structure are sequentially grown on the N-InP spacer layer of the second epitaxial wafer to form a third epitaxial wafer, comprising: growing the P-InAlAs spacer layer on the N-InP spacer layer of the second epitaxial wafer; growing the quantum well region on the P-InAlAs spacer layer; growing the N-InAlAs spacer layer on the quantum well region; growing the top DBR structure on the N-InAlAs spacer layer.

6. The method of claim 5, wherein, the top DBR structure comprises an N-type InAlAs / InGaAlAs DBR structure; the growing the top DBR structure on the N-InAlAs spacer layer comprises: periodically growing an N-type InAlAs DBR structure and an N-type InGaAlAs DBR structure on the N-InAlAs spacer layer, wherein the period is 30-50; and the bottom DBR structure and the top DBR structure form a mirror.

7. The method of claim 1, wherein, the annealing treatment of the second epitaxial wafer and the surface cleaning, comprising: after the annealing treatment of the second epitaxial wafer, sequentially performing acetone cleaning, alcohol cleaning and deionized water cleaning on the surface of the second epitaxial wafer.

8. A structure of a long-wavelength VCSEL, characterized by The structure is applied to the method of any one of claims 1-7, comprising: a preset N-InP substrate; an N-InP buffer layer grown on the N-InP substrate; a bottom DBR structure grown on the N-InP buffer layer; an N-InP spacer layer grown on the bottom DBR structure; a P-InAlAs spacer layer grown on the N-InP spacer layer; a quantum well region grown on the P-InAlAs spacer layer; an N-InAlAs spacer layer grown on the quantum well region; a top DBR structure grown on the N-InAlAs spacer layer; a lower electrode grown on the N-InP substrate away from the N-InP buffer layer; an upper electrode grown on the top DBR structure away from the N-InAlAs spacer layer; wherein, the N-InP spacer layer comprises a passivation region and a light emitting region, and the light emitting region is arranged at the center of the passivation region.

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