A multi-voltage domain wide voltage stabilizing circuit

Abstract

The present invention discloses a multi-voltage domain wide voltage stabilization circuit, comprising a first voltage stabilization circuit, a second voltage stabilization circuit, and a first voltage judgment circuit. The first voltage judgment circuit is connected to the second voltage stabilization circuit. Both the first voltage stabilization circuit and the second voltage stabilization circuit comprise a voltage stabilization module and are commonly connected to a voltage input terminal. The first voltage stabilization circuit further comprises a first resistor R1, one end of the first resistor R1 being connected to the voltage input terminal and the other end being connected to the voltage stabilization module, the other end of the voltage stabilization module being grounded. The common end of the first resistor R1 and the voltage stabilization module is a VDD voltage output terminal. The second voltage stabilization circuit further comprises a second resistor R2, a third resistor R3, a first PMOS transistor MP1, and a first NMOS transistor MN1. The present invention comprises the first voltage stabilization circuit and the second voltage stabilization circuit, each comprising a stable voltage output with a different current driving force. The specific structure of the second voltage stabilization circuit is also compatible with a wider voltage input value.

Description

Technical Field

[0001] The present invention relates to the technical field of semiconductor integrated circuits, and in particular to a multi-voltage domain wide voltage stabilizing circuit. Background Art

[0002] With the advancement of semiconductor integrated circuit technology, the scale of circuit integration has increased. A single semiconductor integrated circuit contains multiple modules, each with different voltage and current driving requirements. This results in a single semiconductor integrated circuit requiring multiple voltage domains for power supply, which greatly complicates its design. How to accurately and efficiently power multiple different voltage domains within a single circuit while using a single external power supply is a technical challenge facing those skilled in the art. Summary of the Invention

[0003] In response to the above shortcomings of the prior art, the present invention discloses a multi-voltage domain wide voltage stabilization circuit. The technical solution includes a first voltage stabilization circuit and a second voltage stabilization circuit. The first voltage stabilization circuit and the second voltage stabilization circuit respectively include stable voltage outputs with different current driving forces. The technical solution of the present invention is specifically as follows:

[0004] A multi-voltage domain wide voltage stabilization circuit comprises a first voltage stabilization circuit, a second voltage stabilization circuit and a first voltage judgment circuit, wherein the first voltage judgment circuit is connected to the second voltage stabilization circuit, and the first voltage stabilization circuit and the second voltage stabilization circuit both comprise voltage stabilization modules and are commonly connected to a voltage input terminal.

[0005] In a further technical solution, the first voltage stabilizing circuit further includes a first resistor R1, one end of the first resistor R1 is connected to the voltage input end, and the other end is connected to the voltage stabilizing module, and the other end of the voltage stabilizing module is grounded; the common end of the first resistor R1 and the voltage stabilizing module is the VDD voltage output end.

[0006] The second voltage stabilizing circuit further includes a second resistor R2, a third resistor R3, a first PMOS transistor MP1, and a first NMOS transistor MN1.

[0007] One end of the second resistor R2 is connected to the voltage input end, and the other end is connected to the drain of the first NMOS transistor MN1. The source and substrate of the first NMOS transistor MN1 are grounded, and the gate is connected to the first voltage judgment circuit.

[0008] The source and substrate of the first PMOS transistor MP1 are connected to the voltage input terminal, the gate is connected to the drain of the first NMOS transistor MN1, the drain is connected to the voltage stabilizing module, and the other end of the voltage stabilizing module is grounded.

[0009] One end of the third resistor R3 is connected to the voltage input end, and the other end is connected to the voltage stabilizing module. The common end of the third resistor R3 and the voltage stabilizing module is the Vout voltage output end.

[0010] In a further technical solution, the wide voltage stabilizing circuit further includes a second voltage determination circuit; the second stabilizing circuit further includes a fourth resistor R4, a fifth resistor R5, a second PMOS transistor MP2 and a second NMOS transistor MN2.

[0011] One end of the fifth resistor R5 is connected to the drain of the first PMOS transistor MP1 , and the other end is connected to the drain of the second NMOS transistor MN2 . The source of the second NMOS transistor MN2 and the substrate are grounded, and the gate is connected to the second voltage judgment circuit.

[0012] The second PMOS transistor MP2 is arranged between the first PMOS transistor MP1 and the voltage stabilizing module. The source and substrate of the second PMOS transistor MP2 are connected to the drain of the first PMOS transistor MP1. The drain of the second PMOS transistor MP2 is connected to the voltage stabilizing module, and the gate is connected to the drain of the second NMOS transistor MN2.

[0013] The fourth resistor R4 is connected in series with the third resistor R3, one end of which is connected to the third resistor R3, and the other end of which is connected to the voltage stabilizing module. The common end of the fourth resistor R4 and the third resistor R3 is connected to the drain of the first PMOS transistor MP1, and the common end of the fourth resistor R4 and the voltage stabilizing module is the Vout voltage output end.

[0014] In a further technical solution, the wide voltage stabilizing circuit further includes a third voltage judgment circuit; the second voltage stabilizing circuit further includes a sixth resistor R6, a seventh resistor R7, a third PMOS transistor MP3 and a third NMOS transistor MN3.

[0015] One end of the seventh resistor R7 is connected to the drain of the second PMOS transistor MP2, and the other end is connected to the drain of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 and the substrate are grounded, and the gate is connected to the third voltage judgment circuit.

[0016] The third PMOS transistor MP3 is arranged between the second PMOS transistor MP2 and the voltage stabilizing module. The source and substrate of the third PMOS transistor MP3 are connected to the drain of the second PMOS transistor MP2. The drain of the third PMOS transistor MP3 is connected to the voltage stabilizing module, and the gate is connected to the drain of the third NMOS transistor MN3.

[0017] The sixth resistor R6 is connected in series with the fourth resistor R4 and the third resistor R3, one end of which is connected to the fourth resistor R4, and the other end of which is connected to the voltage stabilizing module. The common end of the sixth resistor R6 and the fourth resistor R4 is connected to the drain of the second PMOS transistor MP2, and the common end of the sixth resistor R6 and the voltage stabilizing module is the Vout voltage output end.

[0018] In this technical solution, the first voltage determination circuit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a first comparator U1.

[0019] One end of the eighth resistor R8 is connected to the voltage input end, and the other end is connected to the ninth resistor R9, and the other end of the ninth resistor R9 is grounded; one end of the tenth resistor R10 is connected to the Vout voltage output end, and the other end is connected to the eleventh resistor R11, and the other end of the eleventh resistor R11 is grounded.

[0020] The positive input terminal of the first comparator U1 is connected to the common terminal of the tenth resistor R10 and the eleventh resistor R11, the negative input terminal of the first comparator U1 is connected to the common terminal of the eighth resistor R8 and the ninth resistor R9, and the output terminal of the first comparator U1 is connected to the gate of the first NMOS transistor MN1.

[0021] In this technical solution, the second voltage determination circuit includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and a second comparator U2.

[0022] One end of the twelfth resistor R12 is connected to the voltage input end, and the other end is connected to the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is grounded; one end of the fourteenth resistor R14 is connected to the Vout voltage output end, and the other end is connected to the fifteenth resistor R15, and the other end of the fifteenth resistor R15 is grounded.

[0023] The positive input terminal of the second comparator U2 is connected to the common terminal of the fourteenth resistor R14 and the fifteenth resistor R15, the negative input terminal of the second comparator U2 is connected to the common terminal of the twelfth resistor R12 and the thirteenth resistor R13, and the output terminal of the second comparator U2 is connected to the gate of the second NMOS transistor MN2.

[0024] In this technical solution, the third voltage determination circuit includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19 and a third comparator U3.

[0025] One end of the sixteenth resistor R16 is connected to the voltage input end, and the other end is connected to the seventeenth resistor R17, and the other end of the seventeenth resistor R17 is grounded; one end of the eighteenth resistor R18 is connected to the Vout voltage output end, and the other end is connected to the nineteenth resistor R19, and the other end of the nineteenth resistor R19 is grounded.

[0026] The positive input terminal of the third comparator U3 is connected to the common terminal of the eighteenth resistor R18 and the nineteenth resistor R19, the negative input terminal of the third comparator U3 is connected to the common terminal of the sixteenth resistor R16 and the seventeenth resistor R17, and the output terminal of the third comparator U3 is connected to the gate of the third NMOS transistor MN3.

[0027] In this technical solution, the voltage stabilizing module includes a 20th resistor R20, a 21st resistor R21, a 22nd resistor R22, a 23rd resistor R23, a 24th resistor R24, a 25th resistor R25, a 26th resistor R26, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fourth PMOS transistor MP4, a first capacitor C1 and a second capacitor C2.

[0028] One end of the 20th resistor R20 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the 21st resistor R21. The other end of the 21st resistor R21 is connected to the 22nd resistor R22. The other end of the 22nd resistor R22 is connected to the 23rd resistor R23. The other end of the 23rd resistor R23 is grounded.

[0029] One end of the twenty-fourth resistor R24 ​​is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the drain of the fourth NMOS transistor MN4. The substrate of the fourth NMOS transistor MN4 is grounded, and the gate is connected to the common end of the twenty-first resistor R21 and the twenty-second resistor R22. The source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5. The gate and drain of the fifth NMOS transistor MN5 are connected. The source and substrate of the fifth NMOS transistor MN5 are grounded.

[0030] The source of the fourth PMOS transistor MP4 is connected to the substrate of the VDD voltage output terminal or the Vout voltage output terminal, the gate is connected to the common terminal of the twenty-fourth resistor R24 ​​and the fourth NMOS transistor MN4, the drain of the fourth PMOS transistor MP4 is connected to the twenty-fifth resistor R25, the other end of the twenty-fifth resistor R25 is connected to the twenty-sixth resistor R26, and the other end of the twenty-sixth resistor R26 is grounded.

[0031] The drain of the sixth NMOS transistor MN6 is connected to the VDD voltage output terminal or the Vout voltage output terminal, the gate is connected to the common terminal of the fourth PMOS transistor MP4 and the twenty-fifth resistor R25, and the source of the sixth NMOS transistor MN6 and the substrate are grounded.

[0032] One end of the first capacitor C1 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the gate of the sixth NMOS transistor MN6.

[0033] One end of the second capacitor C2 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is grounded.

[0034] The present invention provides a multi-voltage domain wide voltage stabilizing circuit, which includes a first voltage stabilizing circuit and a second voltage stabilizing circuit. The first voltage stabilizing circuit and the second voltage stabilizing circuit respectively include stable voltage outputs with different current driving forces. The specific structure of the second voltage stabilizing circuit can also be compatible with a wider voltage input value. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] Figure 1 A schematic structural diagram of an embodiment of a multi-voltage domain wide voltage stabilizing circuit of the present invention.

[0036] Figure 2 A schematic structural diagram of another embodiment of a multi-voltage domain wide voltage stabilizing circuit of the present invention.

[0037] Figure 3 A schematic structural diagram of another embodiment of a multi-voltage domain wide voltage stabilizing circuit of the present invention.

[0038] Figure 4 A schematic structural diagram of a first voltage judgment circuit in a multi-voltage domain wide voltage stabilization circuit of the present invention.

[0039] Figure 5 A schematic structural diagram of a second voltage judgment circuit in a multi-voltage domain wide voltage stabilization circuit of the present invention.

[0040] Figure 6 A schematic structural diagram of a third voltage judgment circuit in a multi-voltage domain wide voltage stabilization circuit of the present invention.

[0041] Figure 7 A schematic diagram of the circuit structure of a voltage stabilizing module in a multi-voltage domain wide voltage stabilizing circuit of the present invention. Implementation Method

[0042] The present invention will be further described in detail below with reference to the accompanying drawings.

[0043] To better illustrate this embodiment, some components in the drawings may be omitted, enlarged, or reduced, and do not represent the actual dimensions of the product. Those skilled in the art will understand that some well-known structures and their descriptions are omitted in the drawings. The same or similar reference numerals correspond to the same or similar components.

[0044] Modern semiconductor integrated circuits are system-level projects, encompassing multiple digital and analog modules. However, each module has different voltage and current requirements, placing high demands on the power supply. While the concept of multi-voltage domain power supply is already established, achieving more accurate and efficient multi-voltage domain power supply still presents technical challenges.

[0045] In view of the shortcomings of the existing technology, the present invention provides a multi-voltage domain wide voltage stabilization circuit. This technical solution can provide multi-voltage domain voltage outputs with different current driving forces according to different requirements. In addition, this technical solution can also be compatible with wider voltage input values.

[0046] Specifically, this technical solution includes three voltage domains, namely the input voltage (or voltage input) directly from the voltage input terminal, the VDD voltage output from the VDD voltage output terminal, and the Vout voltage output from the Vout voltage output terminal.

[0047] The voltage input terminal has a wide range of input voltages, allowing it to vary between 5V and 30V. This technical solution is compatible with a wider range of voltage inputs. The VDD voltage output terminal and the Vout voltage output terminal both have values ​​between 5V and 6V, but the Vout voltage output terminal has a higher drive current.

[0048] The specific embodiments of the present invention are as follows: Example 1

[0049] This embodiment Figure 1 As shown, a multi-voltage domain wide voltage stabilizing circuit includes a first voltage stabilizing circuit 1, a second voltage stabilizing circuit 2 and a first voltage judgment circuit 31. The first voltage judgment circuit 31 is connected to the second voltage stabilizing circuit 2. The first voltage stabilizing circuit 1 and the second voltage stabilizing circuit 2 both include a voltage stabilizing module 10 and are commonly connected to the voltage input end.

[0050] It should be noted that the applicable range of the input voltage value Vin of this embodiment is between 5V and 14V.

[0051] In a further solution of this embodiment, the first voltage stabilizing circuit 1 further includes a first resistor R1, one end of the first resistor R1 is connected to the voltage input end, and the other end is connected to the voltage stabilizing module 10, and the other end of the voltage stabilizing module 10 is grounded.

[0052] In this embodiment, the common terminal of the first resistor R1 and the voltage stabilizing module 10 is the VDD voltage output terminal. It should be noted that the VDD voltage outputted from the VDD voltage output terminal is used to power the chip internally (the present invention is used for semiconductor integrated circuits inside the chip).

[0053] In a further solution of this embodiment, the second voltage stabilizing circuit 2 further includes a second resistor R2, a third resistor R3, a first PMOS transistor MP1, and a first NMOS transistor MN1.

[0054] One end of the second resistor R2 is connected to the voltage input end, and the other end is connected to the drain of the first NMOS transistor MN1 . The source and substrate of the first NMOS transistor MN1 are grounded, and the gate is connected to the first voltage judgment circuit 31 .

[0055] The source and substrate of the first PMOS transistor MP1 are connected to the voltage input terminal, the gate is connected to the drain of the first NMOS transistor MN1, the drain is connected to the voltage stabilizing module, and the other end of the voltage stabilizing module is grounded.

[0056] One end of the third resistor R3 is connected to the voltage input end, and the other end is connected to the voltage stabilizing module. The common end of the third resistor R3 and the voltage stabilizing module is the Vout voltage output end.

[0057] It should be noted that, in this embodiment, the drain of the first NMOS transistor MN1 is a high-voltage-resistant terminal and can withstand high voltage values. The first NMOS transistor MN1 will not be damaged when the drain terminal is connected to a 30V voltage.

[0058] In this embodiment, the first voltage determination circuit 31 is connected to the gate of the first NMOS transistor MN1 to provide an enable signal for the first NMOS transistor MN1 .

[0059] This embodiment Figure 4 As shown, the first voltage determination circuit 31 includes an eighth resistor R8 , a ninth resistor R9 , a tenth resistor R10 , an eleventh resistor R11 and a first comparator U1 .

[0060] One end of the eighth resistor R8 is connected to the voltage input end, and the other end is connected to the ninth resistor R9, and the other end of the ninth resistor R9 is grounded; one end of the tenth resistor R10 is connected to the Vout voltage output end, and the other end is connected to the eleventh resistor R11, and the other end of the eleventh resistor R11 is grounded.

[0061] The positive input terminal of the first comparator U1 is connected to the common terminal of the tenth resistor R10 and the eleventh resistor R11, the negative input terminal of the first comparator U1 is connected to the common terminal of the eighth resistor R8 and the ninth resistor R9, and the output terminal of the first comparator U1 is connected to the gate of the first NMOS transistor MN1.

[0062] This embodiment Figure 7 As shown, the voltage stabilizing module 10 includes a 20th resistor R20, a 21st resistor R21, a 22nd resistor R22, a 23rd resistor R23, a 24th resistor R24, a 25th resistor R25, a 26th resistor R26, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fourth PMOS transistor MP4, a first capacitor C1 and a second capacitor C2.

[0063] One end of the 20th resistor R20 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the 21st resistor R21. The other end of the 21st resistor R21 is connected to the 22nd resistor R22. The other end of the 22nd resistor R22 is connected to the 23rd resistor R23. The other end of the 23rd resistor R23 is grounded.

[0064] One end of the twenty-fourth resistor R24 ​​is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the drain of the fourth NMOS transistor MN4. The substrate of the fourth NMOS transistor MN4 is grounded, and the gate is connected to the common end of the twenty-first resistor R21 and the twenty-second resistor R22. The source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5. The gate and drain of the fifth NMOS transistor MN5 are connected. The source and substrate of the fifth NMOS transistor MN5 are grounded.

[0065] The source of the fourth PMOS transistor MP4 is connected to the substrate of the VDD voltage output terminal or the Vout voltage output terminal, the gate is connected to the common terminal of the twenty-fourth resistor R24 ​​and the fourth NMOS transistor MN4, the drain of the fourth PMOS transistor MP4 is connected to the twenty-fifth resistor R25, the other end of the twenty-fifth resistor R25 is connected to the twenty-sixth resistor R26, and the other end of the twenty-sixth resistor R26 is grounded.

[0066] The drain of the sixth NMOS transistor MN6 is connected to the VDD voltage output terminal or the Vout voltage output terminal, the gate is connected to the common terminal of the fourth PMOS transistor MP4 and the twenty-fifth resistor R25, and the source of the sixth NMOS transistor MN6 and the substrate are grounded.

[0067] One end of the first capacitor C1 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the gate of the sixth NMOS transistor MN6.

[0068] One end of the second capacitor C2 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is grounded.

[0069] It should be noted that when the voltage stabilizing module 10 is used in the first voltage stabilizing circuit 1, the common end of the 20th resistor R20, the 24th resistor R24, the fourth PMOS transistor MP4, the sixth NMOS transistor MN6, the first capacitor C1, and the second capacitor C2 is connected to the VDD voltage output terminal. When the voltage stabilizing module 10 is used in the second voltage stabilizing circuit 2, the common end of the 20th resistor R20, the 24th resistor R24, the fourth PMOS transistor MP4, the sixth NMOS transistor MN6, the first capacitor C1, and the second capacitor C2 is connected to the Vout voltage output terminal.

[0070] The working principle of this embodiment is as follows:

[0071] This embodiment is applicable to the case where the input voltage value of the voltage input terminal Vin is in the range of 5V-14V.

[0072] like Figure 1 As shown, in the first voltage stabilizing circuit 1, under the action of the first resistor R1 and the voltage stabilizing module 10, the VDD voltage output terminal can stably output a VDD voltage of 5-6V. It should be noted that the VDD voltage here is used to power the internal part of the chip.

[0073] When a power source with a stronger driving force is required externally, the second voltage stabilizing circuit 2 is required to provide a driving voltage, ie, a Vout voltage.

[0074] In the second voltage stabilizing circuit 2, the first NMOS transistor MN1 is a high-voltage MOS transistor, and its drain can withstand high voltage. The first voltage determination circuit 31 outputs an enable signal according to the Vin voltage and the Vout voltage.

[0075] 1. When the input voltage of the voltage input terminal Vin is between 5V and 6V (in practice, the input voltage can be less than 5V and greater than 3V and can also work normally), the first voltage judgment circuit 31 determines that the input voltage of Vin is between 5V and 6V and outputs an enable signal to control the first NMOS transistor MN1 to turn on. At this time, the gate of the first PMOS transistor MP1 is equivalent to being grounded, and the first PMOS transistor MP1 is turned on.

[0076] At this time, the conduction circuit of the second voltage stabilizing circuit 2 is: voltage input terminal Vin - first PMOS transistor MP1 - Vout voltage output terminal. Ultimately, with the participation of the voltage stabilizing module 10, the Vout voltage output terminal is guaranteed to output a stable 5V-6V voltage with strong driving force.

[0077] 2. When the input voltage of the voltage input terminal Vin is between 6V and 14V, the first voltage judgment circuit 31 judges that the input voltage of Vin is between 6V and 14V and outputs an enable signal to control the first NMOS transistor MN1 to be turned off. At this time, the gate of the first PMOS transistor MP1 is at a high potential, that is, the first PMOS transistor MP1 is also turned off.

[0078] The conductive path of the second voltage stabilization circuit 2 is: voltage input terminal Vin - third resistor R3 - Vout voltage output terminal. The third resistor R3 acts as a voltage divider, ultimately ensuring that the Vout voltage output terminal outputs a stable and powerful 5V-6V voltage with the help of the voltage stabilization module 10. Example 2

[0079] The difference between this embodiment and embodiment 1 is that the wide voltage stabilizing circuit further includes a second voltage judgment circuit; the second voltage stabilizing circuit 2 further includes a fourth resistor R4, a fifth resistor R5, a second PMOS transistor MP2 and a second NMOS transistor MN2. Figure 2 shown.

[0080] One end of the fifth resistor R5 is connected to the drain of the first PMOS transistor MP1 , and the other end is connected to the drain of the second NMOS transistor MN2 . The source of the second NMOS transistor MN2 and the substrate are grounded, and the gate is connected to the second voltage determination circuit 32 .

[0081] The second PMOS transistor MP2 is arranged between the first PMOS transistor MP1 and the voltage stabilizing module. The source and substrate of the second PMOS transistor MP2 are connected to the drain of the first PMOS transistor MP1. The drain of the second PMOS transistor MP2 is connected to the voltage stabilizing module, and the gate is connected to the drain of the second NMOS transistor MN2.

[0082] The fourth resistor R4 is connected in series with the third resistor R3 , one end of which is connected to the third resistor R3 , and the other end of which is connected to the voltage stabilizing module. A common end of the fourth resistor R4 and the third resistor R3 is connected to the drain of the first PMOS transistor MP1 .

[0083] At this time, the common end of the fourth resistor R4 and the voltage stabilizing module is the Vout voltage output end.

[0084] This embodiment Figure 5 As shown, the second voltage determination circuit includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and a second comparator U2.

[0085] One end of the twelfth resistor R12 is connected to the voltage input end, and the other end is connected to the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is grounded; one end of the fourteenth resistor R14 is connected to the Vout voltage output end, and the other end is connected to the fifteenth resistor R15, and the other end of the fifteenth resistor R15 is grounded.

[0086] The positive input terminal of the second comparator U2 is connected to the common terminal of the fourteenth resistor R14 and the fifteenth resistor R15, the negative input terminal of the second comparator U2 is connected to the common terminal of the twelfth resistor R12 and the thirteenth resistor R13, and the output terminal of the second comparator U2 is connected to the gate of the second NMOS transistor MN2.

[0087] This embodiment is compatible with a wider input voltage range, and the input voltage value range of the voltage input terminal Vin can be expanded to 5V-22V.

[0088] The working principle of this embodiment is as follows:

[0089] like Figure 2 As shown, in the first voltage stabilizing circuit 1, under the action of the first resistor R1 and the voltage stabilizing module 10, the VDD voltage output terminal can stably output a VDD voltage of 5-6V. The VDD voltage is used to power the internal part of the chip.

[0090] When a power source with a stronger driving force is required externally, the second voltage stabilizing circuit 2 is required to provide a driving voltage, ie, a Vout voltage.

[0091] In this embodiment, the drains of the first NMOS transistor MN1 and the second NMOS transistor MN2 in the second voltage-stabilizing circuit 2 are high-voltage terminals capable of withstanding high voltages. The first and second voltage determination circuits 31 and 32 respectively control the conduction and cutoff of the first and second NMOS transistors MN1 and MN2 based on the enable signals output by the Vin and Vout voltages.

[0092] 1. When the input voltage of the voltage input terminal Vin is between 5V and 6V (in practice, the input voltage can be less than 5V and greater than 3V and can also work normally), the first PMOS transistor MP1 and the second PMOS transistor MP2 are both turned on.

[0093] Specific operation: When the first voltage judgment circuit 31 determines that the input voltage of Vin is between 5V and 6V, it outputs an enable signal to control the first NMOS transistor MN1 to turn on. At this time, the gate of the first PMOS transistor MP1 is equivalent to ground, and the first PMOS transistor MP1 is turned on; when the second voltage judgment circuit 32 determines that the input voltage of Vin is between 5V and 6V, it outputs an enable signal to control the second NMOS transistor MN2 to turn on. At this time, the gate of the second PMOS transistor MP2 is equivalent to ground, and the second PMOS transistor MP2 is turned on.

[0094] In this case, the conduction path of the second voltage stabilizing circuit 2 is: voltage input terminal Vin—first PMOS transistor MP1—second PMOS transistor MP2—Vout voltage output terminal. Finally, with the participation of the voltage stabilizing module 10, the Vout voltage output terminal is guaranteed to output a stable 5V-6V voltage with strong driving force.

[0095] 2. When the input voltage of the voltage input terminal Vin is between 6V and 14V, the first PMOS transistor MP1 is turned off and the second PMOS transistor MP2 is turned on.

[0096] Specific work:

[0097] When the first voltage judgment circuit 31 determines that the input voltage of Vin is between 6V and 14V, it outputs an enable signal to control the first NMOS transistor MN1 to be turned off. At this time, the gate of the first PMOS transistor MP1 is at a high potential, and the first PMOS transistor MP1 is turned off. When the second voltage judgment circuit 32 determines that the input voltage of Vin is between 6V and 14V, it outputs an enable signal to control the second NMOS transistor MN2 to be turned on. At this time, the gate of the second PMOS transistor MP2 is equivalent to being grounded, and the second PMOS transistor MP2 is turned on.

[0098] At this point, the conductive path of the second voltage-stabilizing circuit 2 is: voltage input terminal Vin - third resistor R3 - second PMOS transistor MP2 - Vout voltage output terminal. The voltage divider function of the third resistor R3 and the voltage-stabilizing module 10 ensure that the Vout voltage output terminal outputs a stable 5V-6V voltage with high driving force.

[0099] 3. When the input voltage of the voltage input terminal Vin is between 14V and 22V, both the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off.

[0100] Specific operation: When the first voltage judgment circuit 31 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the first NMOS transistor MN1 to be turned off. At this time, the gate of the first PMOS transistor MP1 is at a high potential, and the first PMOS transistor MP1 is turned off; when the second voltage judgment circuit 32 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the second NMOS transistor MN2 to be turned off. At this time, the gate of the second PMOS transistor MP2 is at a high potential, and the second PMOS transistor MP2 is turned off.

[0101] At this point, the conductive path of the second voltage-stabilizing circuit 2 is: voltage input terminal Vin - third resistor R3 - fourth resistor R4 - Vout voltage output terminal. The voltage divider function of the third resistor R3 and fourth resistor R4, along with the voltage-stabilizing module 10, ensures that the Vout voltage output terminal outputs a stable and powerful 5V-6V voltage. Example 3

[0102] The difference between this embodiment and embodiment 2 is that the wide voltage stabilizing circuit further includes a third voltage judging circuit 33; the second voltage stabilizing circuit further includes a sixth resistor R6, a seventh resistor R7, a third PMOS transistor MP3 and a third NMOS transistor MN3. Figure 3 shown.

[0103] One end of the seventh resistor R7 is connected to the drain of the second PMOS transistor MP2, and the other end is connected to the drain of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 and the substrate are grounded, and the gate is connected to the third voltage judgment circuit.

[0104] In this embodiment, the third PMOS transistor MP3 is arranged between the second PMOS transistor MP2 and the voltage stabilizing module. The source and substrate of the third PMOS transistor MP3 are connected to the drain of the second PMOS transistor MP2. The drain of the third PMOS transistor MP3 is connected to the voltage stabilizing module, and the gate is connected to the drain of the third NMOS transistor MN3.

[0105] In this embodiment, the sixth resistor R6 is connected in series with the fourth resistor R4 and the third resistor R3, one end of which is connected to the fourth resistor R4, and the other end of which is connected to the voltage stabilizing module. The common end of the sixth resistor R6 and the fourth resistor R4 is connected to the drain of the second PMOS transistor MP2, and the common end of the sixth resistor R6 and the voltage stabilizing module is the Vout voltage output end.

[0106] This embodiment Figure 6 As shown, the third voltage determination circuit 33 includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19 and a third comparator U3.

[0107] One end of the sixteenth resistor R16 is connected to the voltage input end, and the other end is connected to the seventeenth resistor R17, and the other end of the seventeenth resistor R17 is grounded; one end of the eighteenth resistor R18 is connected to the Vout voltage output end, and the other end is connected to the nineteenth resistor R19, and the other end of the nineteenth resistor R19 is grounded.

[0108] The positive input terminal of the third comparator U3 is connected to the common terminal of the eighteenth resistor R18 and the nineteenth resistor R19, the negative input terminal of the third comparator U3 is connected to the common terminal of the sixteenth resistor R16 and the seventeenth resistor R17, and the output terminal of the third comparator U3 is connected to the gate of the third NMOS transistor MN3.

[0109] This embodiment is compatible with a wider input voltage range, and the input voltage value range of the voltage input terminal Vin can be expanded to 5V-30V.

[0110] The working principle of this embodiment is as follows:

[0111] like Figure 3 As shown, in the first voltage stabilizing circuit 1, under the action of the first resistor R1 and the voltage stabilizing module 10, the VDD voltage output terminal can stably output a VDD voltage of 5-6V. The VDD voltage is used to power the internal part of the chip.

[0112] When a power source with a stronger driving force is required externally, the second voltage stabilizing circuit 2 is required to provide a driving voltage, ie, a Vout voltage.

[0113] In this embodiment, the drains of the first, second, and third NMOS transistors MN1, MN2, and MN3 in the second voltage-stabilizing circuit 2 are high-voltage terminals capable of withstanding high voltages. The first, second, and third voltage-determination circuits 31, 32, and 33, based on the enable signals output by the Vin and Vout voltages, respectively, control the conduction and cutoff of the first and second NMOS transistors MN1 and MN2.

[0114] 1. When the input voltage of the voltage input terminal Vin is between 5V and 6V (in practice, the input voltage can be less than 5V and greater than 3V and can also work normally), the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are all turned on.

[0115] Specific operation: When the first voltage judgment circuit 31 determines that the input voltage of Vin is between 5V and 6V, it outputs an enable signal to control the first NMOS transistor MN1 to turn on. At this time, the gate of the first PMOS transistor MP1 is equivalent to ground, and the first PMOS transistor MP1 is turned on; when the second voltage judgment circuit 32 determines that the input voltage of Vin is between 5V and 6V, it outputs an enable signal to control the second NMOS transistor MN2 to turn on. At this time, the gate of the second PMOS transistor MP2 is equivalent to ground, and the second PMOS transistor MP2 is turned on; when the third voltage judgment circuit 33 determines that the input voltage of Vin is between 5V and 6V, it outputs an enable signal to control the third NMOS transistor MN3 to turn on. At this time, the gate of the third PMOS transistor MP3 is equivalent to ground, and the third PMOS transistor MP3 is turned on.

[0116] At this time, the conduction path of the second voltage stabilizing circuit 2 is: voltage input terminal Vin—first PMOS transistor MP1—second PMOS transistor MP2—third PMOS transistor MP3—Vout voltage output terminal. Finally, with the participation of the voltage stabilizing module 10, the Vout voltage output terminal is guaranteed to output a stable 5V-6V voltage with strong driving force.

[0117] 2. When the input voltage of the voltage input terminal Vin is between 6V and 14V, the first PMOS transistor MP1 is turned off, and the second PMOS transistor MP2 and the third PMOS transistor MP3 are turned on.

[0118] Specific work:

[0119] When the first voltage judgment circuit 31 determines that the input voltage of Vin is between 6V and 14V, it outputs an enable signal to control the first NMOS transistor MN1 to be turned off. At this time, the gate of the first PMOS transistor MP1 is at a high potential, and the first PMOS transistor MP1 is turned off. When the second voltage judgment circuit 32 determines that the input voltage of Vin is between 6V and 14V, it outputs an enable signal to control the second NMOS transistor MN2 to be turned on. At this time, the gate of the second PMOS transistor MP2 is equivalent to ground, and the second PMOS transistor MP2 is turned on. When the third voltage judgment circuit 33 determines that the input voltage of Vin is between 6V and 14V, it outputs an enable signal to control the third NMOS transistor MN3 to be turned on. At this time, the gate of the third PMOS transistor MP3 is equivalent to ground, and the third PMOS transistor MP3 is turned on.

[0120] At this time, the conduction path of the second voltage stabilizing circuit 2 is: voltage input terminal Vin—third resistor R3—second PMOS transistor MP2—third PMOS transistor MP3—Vout voltage output terminal. Under the voltage dividing effect of the third resistor R3 and the participation of the voltage stabilizing module 10, the Vout voltage output terminal is guaranteed to output a stable 5V-6V voltage with strong driving force.

[0121] 3. When the input voltage of the voltage input terminal Vin is between 14V and 22V, the first PMOS transistor MP1 and the second PMOS transistor MP2 are turned off, and the third PMOS transistor MP3 is turned on.

[0122] Specific work:

[0123] When the first voltage judgment circuit 31 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the first NMOS transistor MN1 to be turned off. At this time, the gate of the first PMOS transistor MP1 is at a high potential, and the first PMOS transistor MP1 is turned off. When the second voltage judgment circuit 32 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the second NMOS transistor MN2 to be turned off. At this time, the gate of the second PMOS transistor MP2 is at a high potential, and the second PMOS transistor MP2 is turned off. When the third voltage judgment circuit 33 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the third NMOS transistor MN3 to be turned on. At this time, the gate of the third PMOS transistor MP3 is equivalent to being grounded, and the third PMOS transistor MP3 is turned on.

[0124] At this time, the conduction path of the second voltage stabilizing circuit 2 is: voltage input terminal Vin—third resistor R3—fourth resistor R4—third PMOS transistor MP3—Vout voltage output terminal. Under the voltage divider effect of the third resistor R3 and the fourth resistor R4, and with the participation of the voltage stabilizing module 10, the Vout voltage output terminal is guaranteed to output a stable 5V-6V voltage with strong driving force.

[0125] 4. When the input voltage of the voltage input terminal Vin is between 22V and 30V, the first PMOS transistor MP1, the second PMOS transistor MP2 and the third PMOS transistor MP3 are all turned off.

[0126] When the first voltage judgment circuit 31 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the first NMOS transistor MN1 to be turned off. At this time, the gate of the first PMOS transistor MP1 is at a high potential, and the first PMOS transistor MP1 is turned off. When the second voltage judgment circuit 32 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the second NMOS transistor MN2 to be turned off. At this time, the gate of the second PMOS transistor MP2 is at a high potential, and the second PMOS transistor MP2 is turned off. When the third voltage judgment circuit 33 determines that the input voltage of Vin is between 14V and 22V, it outputs an enable signal to control the third NMOS transistor MN3 to be turned off. At this time, the gate of the third PMOS transistor MP3 is at a high potential, and the third PMOS transistor MP3 is turned off.

[0127] At this time, the conduction path of the second voltage stabilizing circuit 2 is: voltage input terminal Vin—third resistor R3—fourth resistor R4—sixth resistor R6—Vout voltage output terminal. Under the voltage dividing effect of the third resistor R3, the fourth resistor R4 and the sixth resistor R6, and with the participation of the voltage stabilizing module 10, the Vout voltage output terminal is guaranteed to output a stable 5V-6V voltage with a large driving force.

[0128] Obviously, the above embodiments of the present invention are merely examples for the purpose of clearly illustrating the present invention, and are not intended to limit the embodiments of the present invention. Those skilled in the art will appreciate that other variations or modifications can be made based on the above description. It is not necessary and impossible to enumerate all embodiments here. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention shall be included within the scope of protection of the claims of the present invention.

Claims

1. A multi-voltage range wide voltage stabilizing circuit, comprising a first voltage stabilizing circuit, a second voltage stabilizing circuit, and a first voltage determination circuit, characterized in that: The first voltage judgment circuit is connected to the second voltage stabilizing circuit, the first voltage stabilizing circuit and the second voltage stabilizing circuit both include a voltage stabilizing module and are commonly connected to the voltage input terminal; The voltage input terminal is compatible with an input voltage range of 5V-30V; The first voltage stabilizing circuit further includes a first resistor R1, one end of the first resistor R1 is connected to the voltage input end, and the other end is connected to the voltage stabilizing module of the first voltage stabilizing circuit, and the other end of the voltage stabilizing module of the first voltage stabilizing circuit is grounded; the common end of the first resistor R1 and the voltage stabilizing module of the first voltage stabilizing circuit is the VDD voltage output end; The second voltage stabilizing circuit further includes a second resistor R2, a third resistor R3, a first PMOS transistor MP1 and a first NMOS transistor MN1; One end of the second resistor R2 is connected to the voltage input end, and the other end is connected to the drain of the first NMOS transistor MN1. The source and substrate of the first NMOS transistor MN1 are grounded, and the gate is connected to the first voltage judgment circuit. The source and substrate of the first PMOS transistor MP1 are connected to the voltage input terminal, the gate is connected to the drain of the first NMOS transistor MN1, the drain is connected to the voltage stabilizing module of the second voltage stabilizing circuit, and the other end of the voltage stabilizing module of the second voltage stabilizing circuit is grounded; One end of the third resistor R3 is connected to the voltage input end, and the other end is connected to the voltage stabilizing module of the second voltage stabilizing circuit. The common end of the third resistor R3 and the voltage stabilizing module of the second voltage stabilizing circuit is the Vout voltage output end.

2. The multi-voltage domain wide voltage stabilizing circuit according to claim 1, wherein: The wide voltage stabilizing circuit further includes a second voltage judging circuit; the second stabilizing circuit further includes a fourth resistor R4, a fifth resistor R5, a second PMOS transistor MP2 and a second NMOS transistor MN2; One end of the fifth resistor R5 is connected to the drain of the first PMOS transistor MP1, and the other end is connected to the drain of the second NMOS transistor MN2. The source of the second NMOS transistor MN2 and the substrate are grounded, and the gate is connected to the second voltage judgment circuit. The second PMOS transistor MP2 is arranged between the first PMOS transistor MP1 and the voltage stabilizing module of the second voltage stabilizing circuit. The source and substrate of the second PMOS transistor MP2 are connected to the drain of the first PMOS transistor MP1. The drain of the second PMOS transistor MP2 is connected to the voltage stabilizing module of the second voltage stabilizing circuit. The gate of the second PMOS transistor MP2 is connected to the drain of the second NMOS transistor MN2. The fourth resistor R4 is connected in series with the third resistor R3, one end of which is connected to the third resistor R3, and the other end of which is connected to the voltage stabilizing module of the second voltage stabilizing circuit. The common end of the fourth resistor R4 and the third resistor R3 is connected to the drain of the first PMOS transistor MP1, and the common end of the fourth resistor R4 and the voltage stabilizing module of the second voltage stabilizing circuit is the Vout voltage output end.

3. The multi-voltage domain wide voltage stabilizing circuit according to claim 2, wherein: The wide voltage stabilizing circuit further includes a third voltage judging circuit; the second voltage stabilizing circuit further includes a sixth resistor R6, a seventh resistor R7, a third PMOS transistor MP3 and a third NMOS transistor MN3; One end of the seventh resistor R7 is connected to the drain of the second PMOS transistor MP2, and the other end is connected to the drain of the third NMOS transistor MN3. The source of the third NMOS transistor MN3 and the substrate are grounded, and the gate is connected to the third voltage judgment circuit. The third PMOS transistor MP3 is arranged between the second PMOS transistor MP2 and the voltage stabilizing module of the second voltage stabilizing circuit. The source and substrate of the third PMOS transistor MP3 are connected to the drain of the second PMOS transistor MP2. The drain of the third PMOS transistor MP3 is connected to the voltage stabilizing module of the second voltage stabilizing circuit. The gate of the third PMOS transistor MP3 is connected to the drain of the third NMOS transistor MN3. The sixth resistor R6 is connected in series with the fourth resistor R4 and the third resistor R3, one end of which is connected to the fourth resistor R4, and the other end of which is connected to the voltage stabilizing module of the second voltage stabilizing circuit. The common end of the sixth resistor R6 and the fourth resistor R4 is connected to the drain of the second PMOS transistor MP2, and the common end of the sixth resistor R6 and the voltage stabilizing module of the second voltage stabilizing circuit serves as the Vout voltage output end.

4. The multi-voltage domain wide voltage regulator circuit according to any one of claims 1 to 3, wherein: The first voltage determination circuit includes an eighth resistor R8, a ninth resistor R9, a tenth resistor R10, an eleventh resistor R11 and a first comparator U1; One end of the eighth resistor R8 is connected to the voltage input terminal, and the other end is connected to the ninth resistor R9, and the other end of the ninth resistor R9 is grounded; one end of the tenth resistor R10 is connected to the Vout voltage output terminal, and the other end is connected to the eleventh resistor R11, and the other end of the eleventh resistor R11 is grounded; The positive input terminal of the first comparator U1 is connected to the common terminal of the tenth resistor R10 and the eleventh resistor R11, the negative input terminal of the first comparator U1 is connected to the common terminal of the eighth resistor R8 and the ninth resistor R9, and the output terminal of the first comparator U1 is connected to the gate of the first NMOS transistor MN1.

5. The multi-voltage domain wide voltage stabilizing circuit according to claim 2 or 3, characterized in that: The second voltage determination circuit includes a twelfth resistor R12, a thirteenth resistor R13, a fourteenth resistor R14, a fifteenth resistor R15 and a second comparator U2; One end of the twelfth resistor R12 is connected to the voltage input terminal, and the other end is connected to the thirteenth resistor R13, and the other end of the thirteenth resistor R13 is grounded; one end of the fourteenth resistor R14 is connected to the Vout voltage output terminal, and the other end is connected to the fifteenth resistor R15, and the other end of the fifteenth resistor R15 is grounded; The positive input terminal of the second comparator U2 is connected to the common terminal of the fourteenth resistor R14 and the fifteenth resistor R15, the negative input terminal of the second comparator U2 is connected to the common terminal of the twelfth resistor R12 and the thirteenth resistor R13, and the output terminal of the second comparator U2 is connected to the gate of the second NMOS transistor MN2.

6. The multi-voltage domain wide voltage stabilizing circuit according to claim 3, wherein: The third voltage determination circuit includes a sixteenth resistor R16, a seventeenth resistor R17, an eighteenth resistor R18, a nineteenth resistor R19 and a third comparator U3; One end of the sixteenth resistor R16 is connected to the voltage input terminal, and the other end is connected to the seventeenth resistor R17, and the other end of the seventeenth resistor R17 is grounded; one end of the eighteenth resistor R18 is connected to the Vout voltage output terminal, and the other end is connected to the nineteenth resistor R19, and the other end of the nineteenth resistor R19 is grounded; The positive input terminal of the third comparator U3 is connected to the common terminal of the eighteenth resistor R18 and the nineteenth resistor R19, the negative input terminal of the third comparator U3 is connected to the common terminal of the sixteenth resistor R16 and the seventeenth resistor R17, and the output terminal of the third comparator U3 is connected to the gate of the third NMOS transistor MN3.

7. The multi-voltage domain wide voltage stabilizing circuit according to claim 6, wherein: The voltage stabilizing module includes a 20th resistor R20, a 21st resistor R21, a 22nd resistor R22, a 23rd resistor R23, a 24th resistor R24, a 25th resistor R25, a 26th resistor R26, a fourth NMOS transistor MN4, a fifth NMOS transistor MN5, a sixth NMOS transistor MN6, a fourth PMOS transistor MP4, a first capacitor C1, and a second capacitor C2. One end of the 20th resistor R20 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the 21st resistor R21. The other end of the 21st resistor R21 is connected to the 22nd resistor R22. The other end of the 22nd resistor R22 is connected to the 23rd resistor R23. The other end of the 23rd resistor R23 is grounded. One end of the twenty-fourth resistor R24 ​​is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the drain of the fourth NMOS transistor MN4. The substrate of the fourth NMOS transistor MN4 is grounded, and the gate is connected to the common end of the twenty-first resistor R21 and the twenty-second resistor R22. The source of the fourth NMOS transistor MN4 is connected to the drain of the fifth NMOS transistor MN5. The gate and drain of the fifth NMOS transistor MN5 are connected. The source and substrate of the fifth NMOS transistor MN5 are grounded. The source and substrate of the fourth PMOS transistor MP4 are connected to the VDD voltage output terminal or the Vout voltage output terminal, the gate is connected to the common terminal of the twenty-fourth resistor R24 ​​and the fourth NMOS transistor MN4, the drain of the fourth PMOS transistor MP4 is connected to the twenty-fifth resistor R25, the other end of the twenty-fifth resistor R25 is connected to the twenty-sixth resistor R26, and the other end of the twenty-sixth resistor R26 is grounded; The drain of the sixth NMOS transistor MN6 is connected to the VDD voltage output terminal or the Vout voltage output terminal, the gate is connected to the common terminal of the fourth PMOS transistor MP4 and the twenty-fifth resistor R25, and the source of the sixth NMOS transistor MN6 and the substrate are grounded; One end of the first capacitor C1 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is connected to the gate of the sixth NMOS transistor MN6; One end of the second capacitor C2 is connected to the VDD voltage output terminal or the Vout voltage output terminal, and the other end is grounded.

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