A numerical control unit, a microstrip and an antenna unit of a satellite distributed configuration

Abstract

The application is suitable for the field of silicon-based radio frequency and millimeter wave integrated circuit technology, and provides a satellite distributed configuration numerical control unit, a micro single sheet and an antenna unit, which comprises a decoupling capacitor module, a main control module and a distributed satellite module; the positive electrode of the decoupling capacitor module and the power supply pin of the main control module are connected with the power supply pin of the numerical control unit, and the negative electrode of the decoupling capacitor module and the ground pin of the main control module are connected with the ground pin of the numerical control unit; the distributed satellite module comprises a first satellite sub-module, a second satellite sub-module, a third satellite sub-module and a fourth satellite sub-module, and the connection mode of the first satellite sub-module with the main control module, the connection mode of the second satellite sub-module with the main control module, the connection mode of the third satellite sub-module with the main control module and the connection mode of the fourth satellite sub-module with the main control module are the same. The numerical control unit has the bandwidth universality suitable for various microwave bands and the universality suitable for various semiconductor manufacturing processes.

Description

Technical Field

[0001] This application belongs to the field of silicon-based radio frequency and millimeter wave integrated circuit technology, and particularly relates to a satellite distributed configuration numerical control unit, microwave monolith and antenna unit. Background Technology

[0002] Silicon-based microwave monolithic multifunctional integrated circuit chips typically integrate a digital control unit to drive and control the attenuators, phase shifters, amplifiers, and other multifunctional unit circuits within the chip. Microwave monoliths integrating two or more channels often require independent power supply ports for each transceiver channel, allowing other channels to be shut down during debugging of each channel to avoid inter-channel interference. However, as the number of channels increases, the port resources occupied by the channel power supply also increase, increasing the design difficulty of the transceiver module. The increased number of transceiver channels within the microwave monolith and the higher performance requirements for attenuators and phase shifters make the layout and wiring between the digital control unit and the multifunctional unit more complex, significantly increasing the workload and design difficulty of microwave RF circuits. The digital control unit has high voltage stability requirements; power supply ripple and noise can affect its normal operation. Although external capacitors have good filtering and voltage regulation effects, their capacitance values ​​are sometimes insufficient to meet the stable operation requirements of the digital control unit circuit due to the size limitations of the transceiver module. Summary of the Invention

[0003] This application provides a numerical control unit, microwave monolith, and antenna unit for a satellite distributed configuration, so that the numerical control unit has bandwidth versatility applicable to various microwave bands and versatility applicable to various semiconductor manufacturing processes.

[0004] This application is achieved through the following technical solution:

[0005] In a first aspect, embodiments of this application provide a numerical control unit for a satellite distributed configuration, including: a decoupling capacitor module, a main control module, and a distributed satellite module;

[0006] The positive terminal of the decoupling capacitor module is connected to the power supply pin of the CNC unit, and the negative terminal of the decoupling capacitor module is connected to the ground pin of the CNC unit.

[0007] The power supply pin of the main control module is connected to the power supply pin of the CNC unit, and the ground pin of the main control module is connected to the ground pin of the CNC unit. The main control module adopts a data input method that samples serial data on the rising edge of the clock and transmits the most significant bit first. The main control module adopts a data output method that outputs serial data on the falling edge of the clock and transmits the most significant bit first. The main control module is connected to the distributed satellite module.

[0008] The distributed satellite module includes a first satellite submodule, a second satellite submodule, a third satellite submodule, and a fourth satellite submodule. The power supply pin of the first satellite submodule is connected to the power supply pin of the CNC unit, and the ground pin of the first satellite submodule is connected to the ground pin of the CNC unit. The power supply pin of the second satellite submodule is connected to the power supply pin of the CNC unit, and the ground pin of the second satellite submodule is connected to the ground pin of the CNC unit. The power supply pin of the third satellite submodule is connected to the power supply pin of the CNC unit, and the ground pin of the third satellite submodule is connected to the ground pin of the CNC unit. The power supply pin of the fourth satellite submodule is connected to the power supply pin of the CNC unit, and the ground pin of the fourth satellite submodule is connected to the ground pin of the CNC unit.

[0009] Each time the CNC unit receives a frame of serial data, the main control module, the first satellite submodule, the second satellite submodule, the third satellite submodule, and the fourth satellite submodule simultaneously receive this frame of serial data; each time the CNC unit receives a frame of serial data, there is a corresponding read feedback or write feedback; each time the CNC unit receives a frame of serial data, it performs a read operation or write operation on at least one of the main control module, the first satellite submodule, the second satellite submodule, the third satellite submodule, or the fourth satellite submodule.

[0010] In conjunction with the first aspect, in some possible implementations, the main control module includes: a main shift serial-to-parallel module, a main buffer module, a main common control signal register module, and a main logic control module. When the main control module is working, serial data is input to the main shift serial-to-parallel module via the main control serial data input pin when the main control chip select enable and first-level latch signal input pins are low. When the main control chip select enable and first-level latch signal input pins are at rising edges, the main shift serial-to-parallel module converts the data into parallel data and transmits it to the main buffer module. Simultaneously, the main logic control module extracts key function bits to determine whether the input data is a common control write instruction, a common control signal readback instruction, or an irrelevant instruction. If the input data is determined to be a common control write instruction, when the main control second-level latch and readback control signal input pins are at rising edges, the corresponding data registered in the main buffer module is written to the main common control signal register module. The main logic control module extracts the address information from this write instruction data and updates the data information therein to the corresponding common control signal output pin or reserved control signal output pin. Specifically, updating the reserved control signal output... When the pin's status value is displayed, the main logic control module extracts the soft reset function bit data and generates a low-level pulse signal lasting for 2 CLK cycles after a delay of 1.5 CLK cycles, which is output by the main control soft reset signal output pin. If the input data is determined to be a common control signal readback instruction, when the main control secondary latch and readback control signal input pin is at its rising edge, the instruction information stored in the main cache module and the corresponding control data information in the main common control signal register module are combined to form new parallel data. This data is filled into the main shift serial-to-parallel module at the rising edge of the first CLK signal after the main control secondary latch and readback control signal input pin reaches a high level, and is serially output through the main control serial output pin at the same time as the next frame of serial data input. If the input data is determined to be an irrelevant instruction, the main control module does not perform any read or write operations on the main common control signal register module. The main logic control module detects the rising edge of the main control secondary latch and readback control signal input pin and extracts a signal of one CLK pulse cycle length after the rising edge, which is output by the main control LD detection signal output pin.

[0011] In conjunction with the first aspect, in some possible implementations, the decoupling capacitor module is a CMOS circuit, which includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor is a P-channel field-effect transistor, and the second field-effect transistor is an N-channel field-effect transistor. The source and substrate of the first field-effect transistor are the positive terminals of the decoupling capacitor module, and the gate of the first field-effect transistor is connected to the drain of the second field-effect transistor. The source and substrate of the second field-effect transistor are the negative terminals of the decoupling capacitor module, and the gate of the second field-effect transistor is connected to the drain of the first field-effect transistor.

[0012] In conjunction with the first aspect, in some possible implementations, the CNC unit also includes a reset module; the power supply pin of the reset module is connected to the power supply pin of the CNC unit, the ground pin of the reset module is connected to the ground pin of the CNC unit, and the reset signal output pin of the reset module is connected to the main control module, the first satellite sub-module, the second satellite sub-module, the third satellite sub-module and the fourth satellite sub-module respectively, providing a reset signal during the power-on and power-off processes of the CNC unit.

[0013] In conjunction with the first aspect, in some possible implementations, the internal structure and pinout of the first satellite submodule, the second satellite submodule, the third satellite submodule, and the fourth satellite submodule are all identical.

[0014] In conjunction with the first aspect, in some possible implementations, the first satellite submodule includes: a sub-shift serial-to-parallel module, a sub-buffer module, a TR channel enable and amplitude / phase control module, and a sub-logic control module; the first satellite submodule adopts a data input method that samples serial data on the rising edge of the clock and transmits the most significant bit first, and a data output method that outputs serial data on the falling edge of the clock and transmits the most significant bit first; when the first satellite submodule is working, serial data is input to the sub-shift serial-to-parallel module through the sub-module serial data input pin when the sub-module chip select enable and first-level latch signal input pins are at a low level; when the sub-module chip select enable and first-level latch signal input pins are at a rising edge, the sub-shift serial-to-parallel module converts the data into parallel data and transmits it to the sub-buffer module, while the sub-logic control module extracts the key function bit data to determine whether this parallel data is a TR channel enable or amplitude / phase control write instruction, a TR channel enable or amplitude / phase control status readback instruction, or an irrelevant instruction; if it is a TR channel enable or amplitude / phase control write instruction, then the sub-module two... When the input pin of the secondary latch and readback control signal is at a rising edge, the data stored in the sub-buffer module is written to the TR channel enable and amplitude-phase control module. Subsequently, the corresponding channel switch and TR enable or amplitude-phase control data control the multi-functional circuit unit of the corresponding channel in the microwave single chip according to the channel addressing information extracted by the sub-logic control module. If the input data is determined to be a TR channel enable or amplitude-phase control state readback instruction, when the input pin of the secondary latch and readback control signal of the sub-module is at a rising edge, the instruction information stored in the sub-buffer module and the corresponding control data information in the TR channel enable and amplitude-phase control module are combined to form new parallel data. When the first CLK signal after the input pin of the secondary latch and readback control signal of the sub-module reaches a high level is at a rising edge, it is filled into the sub-shift serial-to-parallel module and read back to the main control module by the readback data output pin at the same time as the next frame of serial data input and output through the main control serial output pin. If the input data is determined to be an irrelevant instruction, the first satellite sub-module has no read or write operation on the TR channel enable and amplitude-phase control module.

[0015] In conjunction with the first aspect, in some possible implementations, the equivalent capacitance value of the decoupling capacitor module is calculated using the following formula:

[0016]

[0017] Where i is the current of the small signal applied across the decoupling capacitor module, v is the voltage of the small signal applied across the decoupling capacitor module, and f is the frequency of the small signal applied across the decoupling capacitor module.

[0018] Secondly, embodiments of this application provide a microwave monolith, characterized in that it includes a numerical control unit as described in any of the first aspects.

[0019] In conjunction with the second aspect, in some possible implementations, the microwave monolith also includes: an amplifier and a power divider; the amplifier is used to amplify the signal input to the microwave monolith to obtain a first signal; the power divider is used to divide the first signal to obtain multiple sets of power-divided signals, and input the multiple sets of power-divided signals into the microwave monolith.

[0020] Thirdly, embodiments of this application provide an antenna unit, characterized in that it includes a numerical control unit as described in any of the first aspects.

[0021] It is understood that the beneficial effects of the second and third aspects mentioned above can be found in the relevant descriptions in the first aspect mentioned above, and will not be repeated here.

[0022] The beneficial effects of the embodiments of this application compared with the prior art are:

[0023] This application divides the multiple channels of the microwave monolith into four working areas through a main control module and four satellite sub-modules, and places the four satellite sub-modules in each working area to reduce the wiring length and complexity from the CNC unit output pins to the multi-functional circuit unit, thereby further reducing the design difficulty of the multi-channel microwave monolith and the design and debugging difficulty of the microwave TR components; the decoupling capacitor module improves the CNC unit's power supply filtering and voltage regulation capabilities, and improves the stability of the circuit when the CNC unit is working; therefore, the CNC unit has the versatility of bandwidth applicable to various microwave bands and the versatility applicable to various semiconductor manufacturing processes.

[0024] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this specification. Attached Figure Description

[0025] To more clearly illustrate the technical solutions in the embodiments of this application, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0026] Figure 1 This is a schematic diagram of the connection relationship of a numerical control unit provided in an embodiment of this application;

[0027] Figure 2 This is a schematic diagram of the main control module provided in one embodiment of this application;

[0028] Figure 3 This is a schematic diagram of the structure of a satellite submodule provided in an embodiment of this application;

[0029] Figure 4 This is a schematic diagram of the working timing provided in an embodiment of this application;

[0030] Figure 5 This is a reference timing diagram of the common control signal output pin of the main control module provided in an embodiment of this application for inputting a frame of write instructions to control its main control module;

[0031] Figure 6 This is a reference timing diagram provided in an embodiment of the present application for inputting a soft reset write instruction to reset all output pins in the numerical control unit to their initial state;

[0032] Figure 7 This is a reference timing diagram provided in one embodiment of the present application for inputting a frame read instruction to read back the common control signal output pin data of its main control module;

[0033] Figure 8 This is a reference timing diagram of an embodiment of the present application that provides inputting a frame write instruction to control the TR channel switch and enable signal output pin of its satellite submodule;

[0034] Figure 9 This is a reference timing diagram of the TR channel switch and enable signal output pin data of a satellite submodule provided in one embodiment of the present application for inputting a frame read command to read back the data.

[0035] Figure 10 This is a reference timing diagram of the TR channel amplitude and phase control signal output pin of a satellite submodule provided in an embodiment of this application for inputting a frame write instruction to control its satellite submodule.

[0036] Figure 11 This is a reference timing diagram provided in one embodiment of the present application for inputting a frame read command to read back the amplitude and phase control signal output pin data of its satellite submodule's TR channel. Detailed Implementation

[0037] In the following description, specific details such as particular system architectures and techniques are set forth for illustrative purposes and not for limitation, in order to provide a thorough understanding of the embodiments of this application. However, those skilled in the art will understand that this application may also be implemented in other embodiments without these specific details. In other instances, detailed descriptions of well-known systems, apparatuses, circuits, and methods have been omitted so as not to obscure the description of this application with unnecessary detail.

[0038] It should be understood that, when used in this application specification and the appended claims, the term "comprising" indicates the presence of the described features, integrals, steps, operations, elements and / or components, but does not exclude the presence or addition of one or more other features, integrals, steps, operations, elements, components and / or a collection thereof.

[0039] It should also be understood that the term “and / or” as used in this application specification and the appended claims means any combination of one or more of the associated listed items and all possible combinations, and includes such combinations.

[0040] As used in this application specification and the appended claims, the term "if" may be interpreted, depending on the context, as "when," "once," "in response to determination," or "in response to detection." Similarly, the phrase "if determined" or "if detected [the described condition or event]" may be interpreted, depending on the context, as meaning "once determined," "in response to determination," "once detected [the described condition or event]," or "in response to detection [the described condition or event]."

[0041] Furthermore, in the description of this application and the appended claims, the terms "first," "second," "third," etc., are used only to distinguish descriptions and should not be construed as indicating or implying relative importance.

[0042] References to "one embodiment" or "some embodiments" as described in this specification mean that one or more embodiments of this application include a specific feature, structure, or characteristic described in connection with that embodiment. Therefore, the phrases "in one embodiment," "in some embodiments," "in other embodiments," "in still other embodiments," etc., appearing in different parts of this specification do not necessarily refer to the same embodiment, but rather mean "one or more, but not all, embodiments," unless otherwise specifically emphasized. The terms "comprising," "including," "having," and variations thereof mean "including but not limited to," unless otherwise specifically emphasized.

[0043] Silicon-based microwave monolithic multifunctional integrated circuit chips typically integrate a digital control unit to drive and control attenuators, phase shifters, amplifiers, and other multifunctional units within the chip. Microwave monoliths integrating two or more channels often require independent power supply ports for each transceiver channel to allow other channels to be shut down during debugging of each channel, thus avoiding mutual interference. However, as the number of channels increases, the port resources occupied by the channel power supply also increase, which increases the design difficulty of the transceiver module. The increase in the number of transceiver channels within the microwave monolith and the higher performance requirements for attenuators, phase shifters, etc., make the layout and wiring between the digital control unit and the multifunctional units more cumbersome, significantly increasing the workload and design difficulty of microwave RF circuits. The digital control unit has high requirements for voltage stability; power supply ripple and noise can affect its normal operation. Although external capacitors have good filtering and voltage regulation effects, their capacitance values ​​are sometimes insufficient to meet the stable operation requirements of the digital control unit circuit due to the size limitations of the transceiver module.

[0044] Based on the above problems, embodiments of this application illustrate a numerical control unit with a satellite distributed configuration, such as... Figure 1 As shown, it includes: a decoupling capacitor module 1001, a main control module 1002 based on the SPI communication protocol, and a distributed satellite module 1003 based on the SPI communication protocol.

[0045] The positive terminal of decoupling capacitor module 1001 is connected to the power supply pin of the CNC unit, and the negative terminal of decoupling capacitor module 1001 is connected to the ground pin of the CNC unit. The presence of decoupling capacitor module 1001 can improve the filtering and voltage regulation capability of the CNC unit, and improve its stability during operation.

[0046] For example, the decoupling capacitor module 1001 is a CMOS circuit. The decoupling capacitor module 1001 includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor is a P-channel field-effect transistor, and the second field-effect transistor is an N-channel field-effect transistor. The source and substrate of the first field-effect transistor are the positive terminals of the decoupling capacitor module 1001, and the gate of the first field-effect transistor is connected to the drain of the second field-effect transistor. The source and substrate of the second field-effect transistor are the negative terminals of the decoupling capacitor module 1001, and the gate of the second field-effect transistor is connected to the drain of the first field-effect transistor.

[0047] For example, the equivalent capacitance value of the decoupling capacitor module is calculated using the following formula:

[0048]

[0049] Where i is the current of the small signal applied across the decoupling capacitor module, v is the voltage of the small signal applied across the decoupling capacitor module, and f is the frequency of the small signal applied across the decoupling capacitor module.

[0050] In some specific embodiments, the gate widths and lengths of the P-channel and N-channel field-effect transistors in the decoupling capacitor module are 1.5µm and 4µm, and 1.5µm and 2.5µm, respectively. The small-signal voltage v is 1V and f = 0.15. The small-signal current value in the simulation result is its capacitance value. It can be seen that when the operating voltage reaches 1.5V or above, its equivalent capacitance value is at least 17.5fF.

[0051] For example, the CNC unit also includes a reset module 1004, the power supply pin of the reset module 1004 being connected to the power supply pin of the CNC unit, and the ground pin of the reset module 1004 being connected to the ground pin of the CNC unit.

[0052] In some specific embodiments, the reset module 1004 may include a power-on reset submodule and a power-off reset submodule, distributing the functions of power-on reset and power-off reset in two modules. Each case has a corresponding processing module, which improves the working efficiency of the reset module 1004.

[0053] The power supply pin of the main control module 1002 is used to connect to an external power supply, and the ground pin of the main control module 1002 is grounded. The main control module 1002 adopts a data input method that samples serial data on the rising edge of the clock and transmits the most significant data first. The main control module 1002 adopts a data output method that outputs serial data on the falling edge of the clock and transmits the most significant data first. The main control module 1002 is connected to the distributed satellite module 1003.

[0054] For example, the distributed satellite module 1003 may include a first satellite submodule 10031, a second satellite submodule 10032, a third satellite submodule 10033, and a fourth satellite submodule 10034. The connection methods between the first satellite submodule 10031 and the main control module 1002, the second satellite submodule 10032 and the main control module 1002, the third satellite submodule 10033 and the main control module 1002, and the fourth satellite submodule 10034 and the main control module 1002 are the same. The reset signal output pin of the reset module 1004 is connected to the main control module 1002, the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034, respectively. During the power-on and power-off processes of the numerical control unit, the reset module 1004 provides a reset signal, ensuring that the multi-functional unit connected to the numerical control unit in the microwave microcontroller has a reference initial state available for debugging after power-on.

[0055] Each time the CNC unit receives a frame of serial data, the main control module 1002, the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 simultaneously receive this frame of serial data. Each time the CNC unit receives a frame of serial data, there is a corresponding read feedback or write feedback. Each time the CNC unit receives a frame of serial data, it performs a read operation or write operation on at least one of the following modules: the main control module 1002, the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, or the fourth satellite submodule 10034.

[0056] Specifically, such as Figure 2 As shown, exemplarily, the main control module 1002 includes: a main shift serial-to-parallel module, a main buffer module, a main common control signal register module, and a main logic control module. The main control module 1002 also includes: a main control power supply pin, a main control ground pin, a main control asynchronous reset input pin RSTN1, a main control clock signal input pin CLK1, a main control serial data input pin DATA1, a main control chip select enable and first-level latch signal input pin CS1, a main control second-level latch and readback control signal input pin LD, a main control 4-bit serial readback data input pin RD_DIN<3:0>, a main control soft reset signal output pin SftRstN, a main control LD detection signal output pin LD_POS, a main control serial output pin DOUT, a first common control signal output pin M_COM_CTRL_0, a second common control signal output pin M_COM_CTRL_1, a third common control signal output pin M_COM_CTRL_2, a fourth common control signal output pin M_COM_CTRL_3, and a main control reserved control signal output pin RESERVED_CTRL.

[0057] The main control module 1002's asynchronous reset input pin is connected to the reset signal output pin of the reset module, receiving the reset signal from the reset module during the microwave microcontroller's power-on and power-off processes. The main shift register-to-parallel converter module consists of a shift register circuit with asynchronous reset and digital logic gates. Its inputs are connected to the main control asynchronous reset input pin, the main control clock signal input pin, the main control serial data input pin, the main control chip select enable and first-level latch signal input pin, and the main logic control module. Its outputs are connected to the main buffer module and the main logic control module. The main buffer module consists of a parallel circuit of D flip-flops with asynchronous reset and digital logic gates. In addition to the aforementioned connections, its inputs are connected to the main control asynchronous reset input pin and the main control chip select enable and first-level latch signal input pin. Its outputs are connected to the main function identifier module and the main logic control module. The main common control signal register module consists of a parallel circuit of D flip-flops with asynchronous reset and a digital logic gate circuit. In addition to the aforementioned connections, its input terminals are connected to the main control asynchronous reset input pin, the main control soft reset signal output pin SftRstN, the main control LD detection signal output pin LD_POS, and the main logic control module. Its output terminals are connected to the first common control signal output pin M_COM_CTRL_0, the second common control signal output pin M_COM_CTRL_1, the third common control signal output pin M_COM_CTRL_2, the fourth common control signal output pin M_COM_CTRL_3, the main control reserved control signal output pin RESERVED_CTRL, and the main logic control module. The main logic control module consists of a read / write control module, a soft reset signal extraction module, an LD_POS signal generation module, and a serial output logic control module. In addition to the aforementioned connections, its inputs are connected to the main control asynchronous reset input pin, the main control clock signal input pin, the main control chip select enable and first-level latch signal input pin, the main control second-level latch and readback control signal input pin LD, and the main control 4-bit serial readback data input pin RD_DIN<3:0>. Its outputs are connected to the main control LD detection signal output pin LD_POS, the main control soft reset signal output pin SftRstN, and the main control serial output pin DOUT. After the microwave microcontroller is powered on, the main control module 1002 receives the reset signal from the reset module, resetting all its internal registers to their initial state.

[0058] The main shift serial-to-parallel module consists of a 32-bit shift register circuit with asynchronous reset and digital logic gate circuits. Its input terminals are connected to the RSTN1, CLK1, DATA1, CS1 pins and the SftRstN pin and 32-bit readback data pin of the main logic control module. Its output terminals are connected to the 32-bit parallel data input pin of the main cache module and the main module serial output strobe pin of the main logic control module.

[0059] The main cache module consists of a parallel circuit of 32-bit D flip-flops with asynchronous reset and digital logic gate circuits. In addition to the aforementioned connection relationship, its input terminal is connected to the CS1 and RSTN1 pins, and its output terminal is connected to the 8-bit parallel data input pin of the main common control signal register module and the function identifier and address bit extraction pin of the main logic control module.

[0060] The main common control signal register module consists of five parallel circuits of 8-bit D flip-flops with asynchronous reset and digital logic gate circuits. In addition to the aforementioned connection relationships, its input terminals are connected to the RSTN1 pin and the SftRstN pin, LD_POS pin, and write logic control group (MS, RW) of the main logic control module. Its output terminals are connected to the M_COM_CTRL_0, M_COM_CTRL_1, M_COM_CTRL_2, M_COM_CTRL_3, RESERVED_CTRL pins and the soft reset signal extraction pin of the main logic control module.

[0061] The main logic control module consists of a read / write selection control module, a soft reset signal extraction module, an LD_POS signal generation module, and a serial output logic control module. In addition to the aforementioned connection relationships, its input terminals are connected to RSTN1, CLK1, CS1, LD, and RD_DIN<3:0>, and its output terminals are connected to the LD_POS, SftRstN, and DOUT pins.

[0062] When the main control module 1002 is working, serial data is input to the main shift serial-to-parallel module through the main control serial data input pin when the main control chip select enable and the first-level latch signal input pin are at a low level.

[0063] When the main control chip select enable and the first-level latch signal input pin CS1 are on the rising edge, the main shift serial-to-parallel module will convert the data into parallel data and transmit it to the main buffer module. At the same time, the main logic control module extracts the key function bit data to determine whether the input data is a common control write instruction, a common control signal readback instruction, or an irrelevant instruction.

[0064] If the input data is determined to be a common control write instruction, when the main control secondary latch and readback control signal input pin is at the rising edge, the corresponding data registered in the main cache module is written to the main common control signal register module. The main logic control module extracts the address information in this write instruction data and updates the data information therein to the corresponding common control signal output pin or reserved control signal output pin. When updating the state value of the reserved control signal output pin, the main logic control module extracts the soft reset function bit data therein and generates a low-level pulse signal that lasts for 2 clock cycles after a delay of 1.5 clock cycles, which is output by the main control soft reset signal output pin SftRstN.

[0065] If the input data is determined to be a common control signal readback instruction, when the main control secondary latch and readback control signal input pin CS1 is at the rising edge, the instruction information stored in the main buffer module and the corresponding control data information in the main common control signal register module are combined to form new parallel data. This data is then filled into the main shift serial-to-parallel module at the rising edge of the first CLK1 signal after the main control secondary latch and readback control signal input pin LD reaches a high level, and is serially output through the main control serial output pin DOUT at the same time as the next frame of serial data input.

[0066] If the input data is determined to be an irrelevant instruction, the main control module 1002 will not perform any read or write operations on the main common control signal register module; the main logic control module detects the rising edge of the main control secondary latch and readback control signal input pin LD and extracts the signal of the main control secondary latch and readback control signal input pin for one clock cycle after the rising edge, which is output by the main control LD detection signal output pin LD_POS.

[0067] For example, the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 have the same internal structure and pins. Dividing the four satellite submodules into four quadrant working areas can reduce the wiring length and complexity from the CNC unit output pins to the multi-functional circuit unit, thereby further reducing the design difficulty of multi-channel microwave monolithic chips.

[0068] For example, such as Figure 3 As shown, the first satellite submodule 10031 includes: a sub-shift serial-to-parallel module, a sub-buffer module, a TR channel enable and amplitude / phase control module, and a sub-logic control module.

[0069] Specifically, such as Figure 3As shown, the first satellite submodule 10031 also includes: submodule power supply pin, submodule ground pin, submodule asynchronous reset input pin RSTN2, submodule soft reset input pin SFTRSN, submodule clock signal input pin CLK2, submodule serial data input pin DATA2, submodule chip select enable and first-level latch signal input pin CS2, submodule second-level latch and readback control signal input pin LD_RW, global test input pin AL_SUB_TST, satellite submodule addressing pin Q_ADDR_SEL, readback data output pin RD_DOUT, and first TR channel amplitude and phase control signal output pin. The control signal output pins are: A_P_CTRL_CH0, A_P_CTRL_CH1 (second TR channel amplitude and phase control signal output pin), A_P_CTRL_CH2 (third TR channel amplitude and phase control signal output pin), A_P_CTRL_CH3 (fourth TR channel amplitude and phase control signal output pin), S_COM_CTRL_0 (first TR channel switch and enable signal output pin), S_COM_CTRL_1 (second TR channel switch and enable signal output pin), S_COM_CTRL_2 (third TR channel switch and enable signal output pin), and S_COM_CTRL_3 (fourth TR channel switch and enable signal output pin).

[0070] For example, the power supply pin (submodule power supply pin) of the first satellite submodule 10031 is connected to the power supply pin of the CNC unit, and the ground pin (submodule ground pin) of the first satellite submodule 10031 is connected to the ground pin of the CNC unit.

[0071] The power supply pin (submodule power supply pin) of the second satellite submodule 10032 is connected to the power supply pin of the CNC unit, and the ground pin (submodule ground pin) of the second satellite submodule 10023 is connected to the ground pin of the CNC unit.

[0072] The power supply pin (submodule power supply pin) of the third satellite submodule 10033 is connected to the power supply pin of the CNC unit, and the ground pin (submodule ground pin) of the third satellite submodule 10033 is connected to the ground pin of the CNC unit.

[0073] The power supply pin (submodule power supply pin) of the fourth satellite submodule 10034 is connected to the power supply pin of the CNC unit, and the ground pin (submodule ground pin) of the fourth satellite submodule 10034 is connected to the ground pin of the CNC unit.

[0074] Specifically, for the main control clock signal input pin CLK1, the main control serial data input pin DATA1, the main control chip select enable and first-level latch signal input pin CS1, the submodule clock signal input pin CLK2, the submodule serial data input pin DATA2, and the submodule chip select enable and first-level latch signal input pin CS2, the main control clock signal input pin CLK1 and the submodule clock signal input pin CLK2 constitute the clock signal pin CLK of the CNC unit in this satellite distributed configuration. The main control serial data input pin DATA1 and the submodule serial data input pin DATA2 constitute the serial data input pin DATA of the CNC unit in this satellite distributed configuration. The main control chip select enable and first-level latch signal input pin CS1 and the submodule chip select enable and first-level latch signal input pin CS2 constitute the chip select enable and first-level latch signal input pin CS of the CNC unit in this satellite distributed configuration.

[0075] Specifically, the SFTRSN and LD_RW pins of the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 are connected to the SftRstN and LD_POS pins of the main control module 1002, respectively; the CS2, CLK2, and DATA2 pins of the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 are connected to the CS1, CLK1, and DATA1 pins of the main control module 1002, respectively; and the RD_DOUT pins of the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 are connected to the RD_DIN<3:0> pins of the main control module, respectively.

[0076] The sub-shift serial-to-parallel module consists of a 32-bit shift register with asynchronous reset and digital logic gates. Its inputs are connected to the RSTN2, SFTRSN, CLK2, DATA2, and CS2 pins, as well as the readback logic control group (corresponding to MS and RW in the function identifier bits) and the 32-bit readback data pin of the sub-logic control module. Its outputs are connected to the 32-bit parallel data input pin of the sub-buffer module and the serial output strobe pin of the sub-logic control module.

[0077] The sub-buffer module consists of a parallel circuit of 32-bit D flip-flops with asynchronous reset and digital logic gate circuits. In addition to the aforementioned connection relationships, its input terminals are connected to the CS2 and RSTN2 pins, and its output terminals are connected to the TR channel enable and the 20-bit parallel data input pin of the amplitude and phase control module, the function identifier bits (MS, RW, DC) and address bit (ADDR) extraction pin of the sub-logic control module.

[0078] The TR channel enable and amplitude / phase control module comprises two parts: a channel switch and TR enable module, and an amplitude / phase control module. The channel switch and TR enable module consists of four sets of 8-bit D flip-flops in parallel circuits with asynchronous reset and digital logic gates. The amplitude / phase control module consists of four sets of 20-bit D flip-flops in parallel circuits with asynchronous reset and digital logic gates. In addition to the aforementioned connections, the inputs of the TR channel enable and amplitude / phase control module are connected to the SFTRSN pin, the LD_RW pin, and the write logic control group of the sub-logic control module (corresponding to the MS, RW, DC function identifiers and the Q_ADDR, CH_ADDR address bits). Its outputs are connected by the TR enable module to the S_COM_CTRL_0, S_COM_CTRL_1, S_COM_CTRL_2, and S_COM_CTRL_3 pins, and by the amplitude / phase control module to the A_P_CTRL_CH0, A_P_CTRL_CH1, A_P_CTRL_CH2, and A_P_CTRL_CH3 pins.

[0079] The sub-logic control module consists of a read / write selection control module and a serial output logic control module. In addition to the aforementioned connection relationships, its input terminals are connected to the CLK2 and LD_RW pins.

[0080] Specifically, the asynchronous reset input pin RSTN2 of the first satellite submodule 10031 is connected to the reset signal output pin of the reset module 1004, receiving the reset signal from the reset module during the power-on and power-off processes of the microwave microcontroller. The SFTRSN and LD_RW pins of the first satellite submodule 10031 are connected to the SftRstN and LD_POS pins of the main control module 1002. The RD_DOUT pins of the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 are respectively connected to the RD_DIN pin of the main control module 1002. <0> RD_DIN <1> RD_DIN <2> RD_DIN <3> The pin connections are as follows: The sub-shift serial-to-parallel module consists of a shift register with asynchronous reset and digital logic gates. Its inputs are connected to the sub-module asynchronous reset input pin RSTN2, the sub-module clock signal input pin CLK2, the sub-module serial data input pin DATA2, the sub-module chip select enable and first-level latch signal input pin CS2, and the sub-logic control module. Its outputs are connected to the sub-buffer module and the sub-logic control module. The sub-buffer module consists of a parallel circuit of D flip-flops with asynchronous reset and digital logic gates. In addition to the aforementioned connections, its inputs are connected to the sub-module chip select enable and first-level latch signal input pin CS2, and its outputs are connected to the TR channel enable and amplitude / phase control module and the sub-logic control module. The TR channel enable and amplitude / phase control module comprises two parts: a channel switch and a TR enable module, and an amplitude / phase control module. The former consists of four sets of parallel D flip-flops with asynchronous reset and digital logic gates. In addition to the aforementioned connections, its inputs are connected to the SFTRSN and LD_RW pins and the sub-logic control module, while its outputs are connected to the S_COM_CTRL_0, S_COM_CTRL_1, S_COM_CTRL_2, and S_COM_CTRL_3 output pins. The latter consists of four sets of parallel D flip-flops with asynchronous reset and digital logic gates. In addition to the aforementioned connections, its inputs are connected to the LD_RW pin and the sub-logic control module, while its outputs are connected to the A_P_CTRL_CH0, A_P_CTRL_CH1, A_P_CTRL_CH2, and A_P_CTRL_CH3 pins. The sub-logic control module consists of a read / write selection control module and a serial output logic control module. In addition to the aforementioned connections, its inputs are connected to the sub-module clock signal input pin and the LD_RW pin. After the microwave chip is powered on, the satellite submodule receives the reset signal from the reset module, which resets all its internal registers to their initial state.

[0081] The first satellite submodule 10031 adopts a data input method that samples serial data on the rising edge of the clock and transmits the most significant data first, and a data output method that outputs serial data on the falling edge of the clock and transmits the most significant data first.

[0082] When the first satellite submodule 10031 is working, serial data is input to the sub-shift serial-to-parallel module through the submodule serial data input pin when the submodule chip select enable and the first-level latch signal input pin CS2 are at a low level.

[0083] When the submodule chip select enable and the first-level latch signal input pin CS2 are on the rising edge, the sub-shift serial-to-parallel module will convert the parallel data and transmit it to the sub-buffer module. At the same time, the sub-logic control module will extract the key function bit data to determine whether the parallel data is a TR channel enable or amplitude-phase control write instruction, a TR channel enable or amplitude-phase control status readback instruction, or an irrelevant instruction.

[0084] If it is a TR channel enable or amplitude / phase control write instruction, when the LD_RW input pin of the submodule's secondary latch and readback control signal is on the rising edge, the data registered in the sub-buffer module is written to the TR channel enable and amplitude / phase control module. Then, the corresponding channel switch and TR enable or amplitude / phase control data control the multi-functional circuit unit of the corresponding channel in the microwave microcontroller according to the channel addressing information extracted by the sub-logic control module.

[0085] If the input data is determined to be a TR channel enable or amplitude-phase control status readback instruction, when the submodule secondary latch and readback control signal input pin LD_RW is at the rising edge, the instruction information retained in the sub-buffer module is combined with the corresponding control data information in the TR channel enable and amplitude-phase control modules to form new parallel data. When the first CLK2 signal after the submodule secondary latch and readback control signal input pin LD_RW reaches a high level is at the rising edge, it is filled into the sub-shift serial-to-parallel module. At the same time as the next frame of serial data input, it is read back to the main control module 1002 by the readback data output pin RD_DOUT and output through the main control serial output pin DOUT.

[0086] If the input data is determined to be an irrelevant instruction, the first satellite submodule 10031 will not perform any read or write operations on the TR channel enable and amplitude / phase control module.

[0087] The design of the aforementioned distributed satellite module 1003, by designing channel switches and TR enable submodules and corresponding control signal pins in the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 respectively, enables the switching control of each transceiver channel without adding independent power supply ports for the channels, thereby reducing the design and debugging difficulty of the microwave TR component.

[0088] Specifically, each time the CNC unit receives a frame of serial data, the main control module 1002, the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033, and the fourth satellite submodule 10034 simultaneously receive this frame of serial data. Furthermore, each time the CNC unit receives a frame of serial data, there is a corresponding read feedback or write feedback. Furthermore, each time the CNC unit receives a frame of serial data, it enables at least one module in the amplitude and phase control module to perform a read or write operation on the TR channel of the common control signal register module in the main control module 1002, or the first satellite submodule 10031, or the second satellite submodule 10032, or the third satellite submodule 10033, or the fourth satellite submodule 10034.

[0089] In some specific embodiments, the numerical control unit receives a frame of 32-bit serial data each time, and the main control module 1002, the first satellite submodule 10031, the second satellite submodule 10032, the third satellite submodule 10033 and the fourth satellite submodule 10034 receive this frame of serial data synchronously.

[0090] Specifically, taking the main control module 1002 and the first satellite submodule 10031 as examples, the frame structures of the input 32-bit serial data control code corresponding to the main control module 1002 and the first satellite submodule 10031 are shown in Table 1 and Table 2, respectively: MS is the main / submodule identification bit. When it is logic "1" (i.e., high level, the same below), the CNC unit performs read / write operations on the main control module 1002. When it is logic "0" (i.e., low level, the same below), the CNC unit performs read / write operations on the first satellite submodule 10031. RW is the read / write function control bit. When its value is logic "1", the CNC unit reads the specified value from the main control module 1002 or the first satellite submodule 10031. When the data in the register is logic "0", the CNC unit writes a specific position from the input data into a designated register in the main control module 1002 or the first satellite submodule 10031. DC is the register selection flag; when its value is logic "1", the CNC unit performs read / write operations on the amplitude and phase control module of the first satellite submodule 10031; when its value is logic "0", the CNC unit performs read / write operations on the channel switch and TR enable modules of the first satellite submodule 10031. ADDR is the common control signal register address of the main control module 1002. When MS is logic "1", the CNC unit reads / writes the corresponding register in the common control signal register module according to the ADDR signal. Q_ADDR is the working area address of the distributed satellite module 1003, and CH_ADDR is the TR channel read / write address of the distributed satellite module 1003. When MS is logic "0", the CNC unit reads / writes the enable or amplitude and phase control status signal of the TR channel corresponding to CH_ADDR in the distributed satellite module 1003 specified by Q_ADDR. DATA is the data bit, which is determined by MS, RW, DC, ADDR, Q_ADDR, and CH_ADDR to control the read / write operation of the main control module 1002 or the first satellite submodule 10031.

[0091] Furthermore, each time the CNC unit receives a frame of 32-bit serial data from the outside, it enables the TR channel of at least one satellite submodule of the main control module 1002 or one satellite submodule of the distributed satellite module 1003 to perform read or write operations with one module of the amplitude and phase control module.

[0092] Table 1. Serial data control code frame structure of input main control module 1002

[0093]

[0094] Table 2. Serial data control code frame structure of input distributed satellite module 1003

[0095]

[0096] Specifically, the working sequence of the CNC unit is as follows: Figure 4As shown, when CS1 is low, 32-bit serial data (D31~D0) is synchronously written to the main shift serial-to-parallel module of the main control module 1002 and the sub-shift serial-to-parallel modules of the four satellite sub-modules of the distributed satellite module 1003 in the order of D31 to D0 via DATA1 at the rising edge of CLK1, and is converted into 32-bit parallel data. At this time, the operation of pin CS2 is consistent with that of pin CS1, pin CLK2 is consistent with that of pin CLK1, and pin DATA2 is consistent with that of pin DATA1. That is, while writing data to the main control module 1002, data is also being written to the four sub-modules in the distributed satellite module 1003.

[0097] Furthermore, still taking the main control module 1002 and the first satellite sub-module 10031 as examples, when CS1 rises, 32-bit parallel data is written into the main cache module of the main control module 1002 or the sub-cache module of the first satellite sub-module 10031; furthermore, when LD rises, the main logic control module of the main control module 1002 or the sub-logic control module in the first satellite sub-module 10031 extracts the function identifier bit and address bit data in the input data (the main control module 1002 extracts D31~D30, D28~D26, i.e. MS, RW, ADDR; the first satellite sub-module 10031 extracts D31~D25, i.e. MS, RW, DC, Q_ADDR, CH_ADDR) to determine whether the input data is a read instruction or a write instruction, thereby reading the current control data of the corresponding multi-functional circuit unit in the microwave single chip or sending the control data in the input data to the corresponding multi-functional unit control terminal in the microwave single chip.

[0098] Specifically, to input write command data into the CNC unit and update the control value of the common control signal output pin of its main control module 1002, refer to... Figure 5In the 32-bit serial data, MS represents logic "1", RW represents logic "0", and the value of ADDR is consistent with the output pin of the common control signal (ADDR = "000" corresponds to the M_COM_CTRL_0<7:0> pin, ADDR = "001" corresponds to the M_COM_CTRL_1<7:0> pin, ADDR = "010" corresponds to the M_COM_CTRL_2<7:0> pin, ADDR = "011" corresponds to the M_COM_CTRL_3<7:0> pin, ADDR = "100" corresponds to the RESERVED_CTRL<5:0> pin, and so on). DATA1[7:0] is the data value that controls the output pin of the common control signal to the required state. Furthermore, the 32-bit data input at the rising edge of CS1 is loaded into the main buffer module of the main control module. Furthermore, at the rising edge of LD, DATA1[7:0] of the 32-bit data stored in the main cache module is loaded into the register in the main common control signal register module specified by ADDR, and then the corresponding common control signal output pin is updated to the required level state. Specifically, when the M_COM_CTRL_i<7:0> (i=0~3) pin state is updated, the high bits are updated to D7~D0 respectively, and when the RESERVED_CTRL<5:0> pin state is updated, the high bits are updated to D7~D2 respectively; preferably, when ADDR=“100”, the data D0 in the main common control signal module is loaded into the main logic control module, delayed by 1.5 clock cycles, and output through the SftRstN pin as the soft reset signal of the CNC unit. That is, if D0 is logic “0” at this time, after 1.5 clock cycles after the rising edge of LD, the output pins in the CNC unit are all reset to the initial state, refer to Figure 6 .

[0099] Specifically, to input read command data into the CNC unit and thus read the control value of the common control signal output pin of its main control module 1002, refer to... Figure 7 In the 32-bit serial data, MS is logic "1", RW is logic "1", the value of ADDR is consistent with the common control signal output pin, and DATA[7:0] is 8 bits of logic "0". Further, the 32-bit data input at the rising edge of CS1 is loaded into the main cache module of the main control module 1002. Further, at the rising edge of LD, the high 8 bits of the 32-bit data stored in the main cache module are combined with the 8 bits of data in the register pointed to by ADDR in the main common control signal register module to form a new 32-bit parallel data (the low 16 bits are all padded with logic "1"). It is written back to the main shift serial-to-parallel module at the first rising edge of CLK1 after LD reaches a high level, and output through DOUT at the same time as the next frame of data input.

[0100] Specifically, to input write command data into the CNC unit to update the control values ​​of the TR channel switch and enable signal output pins of its distributed satellite module 1003, taking the first satellite submodule 10031 as an example, its Q_ADDR_SEL pin is connected to a "00" level, and the input data references... Figure 8 In the 32-bit serial data, MS is logic "0", RW is logic "0", DC is logic "0", Q_ADDR[1:0] is "00", and CH_ADDR[1:0] is consistent with the TR channel switch and enable signal output pins (CH_ADDR = "00" corresponds to the S_COM_CTRL_0<7:0> pin, CH_ADDR = "01" corresponds to the S_COM_CTRL_1<7:0> pin, CH_ADDR = "10" corresponds to the S_COM_CTRL_2<7:0> pin, CH_ADDR = "11" corresponds to the S_COM_CTRL_3<7:0> pin, and so on). Bits D7 to D0 of DATA[19:0] are the data values ​​that control the TR channel switch and enable signal output pins to the required state, and bits D19 to D9 are logic "0". Furthermore, the 32-bit data input at the rising edge of CS2 is loaded into the sub-buffer module of the first satellite submodule 10031. Furthermore, on the rising edge of LD_RW, bits D7 to D0 of the 32-bit data in the sub-buffer module are loaded into the register pointed to by CH_ADDR in the channel switch and TR enable module, and then the corresponding TR channel switch and enable signal output pins are updated to the required level state. Specifically, each time the S_COM_CTRL_j<7:0> (j=0~3) pin state is updated, the bits from high to low are updated to D7 to D0 respectively.

[0101] Specifically, to input read instruction data into the CNC unit of this embodiment of the invention, thereby reading the control values ​​of the TR channel switch and enable signal output pin of its distributed satellite module 1003, taking the first satellite submodule 10031 as an example, its Q_ADDR_SEL pin is connected to the "00" level, and the input data references... Figure 9In the 32-bit serial data, MS is logic "0", RW is logic "1", DC is logic "0", Q_ADDR[1:0] is "00", CH_ADDR[1:0] is consistent with the TR channel switch and enable signal output pin, and DATA[19:0] is 20 bits of logic "0". Further, at the rising edge of CS, the 32-bit data is loaded into the sub-buffer module of the first satellite submodule 10031; further, at the rising edge of LD_RW, the high 8 bits of the 32-bit data stored in the sub-buffer module of the first satellite submodule 10031 are combined with the 8 bits of data in the register pointed to by CH_ADDR in the channel switch and TR enable module to form a new 32-bit parallel data (the low 16 bits are all padded with logic "1"). This data is then written back to the sub-shift serial-to-parallel module at the first rising edge of CLK2 after LD_RW reaches a high level. Simultaneously with the input of the next frame of data, it is input to the main control module 1002 via the RD_DOUT pin and output via the DOUT pin.

[0102] Specifically, to input write command data into the CNC unit to update the control value of the amplitude and phase control signal output pin of the TR channel of its distributed satellite module 1003, taking the first satellite submodule 10031 as an example, its Q_ADDR_SEL pin is connected to the "00" level, and the input data reference... Figure 10 In the 32-bit serial data, MS is logic "0", RW is logic "0", DC is logic "1", Q_ADDR[1:0] is "00", and the value of CH_ADDR[1:0] is consistent with the output pin of the TR channel amplitude and phase control signal (CH_ADDR = "00" corresponds to the A_P_CTRL_CH0<19:0> pin, CH_ADDR = "01" corresponds to the A_P_CTRL_CH1<19:0> pin, CH_ADDR = "10" corresponds to the A_P_CTRL_CH2<19:0> pin, CH_ADDR = "11" corresponds to the A_P_CTRL_CH3<19:0> pin, and so on). Bits D19 to D0 of DATA[19:0] are the data values ​​that control the output pin of the TR channel amplitude and phase control signal to the required state. Furthermore, the 32-bit data input at the rising edge of CS2 is loaded into the sub-buffer module of the first satellite submodule 10031. Furthermore, on the rising edge of LD_RW, bits D19 to D0 of the 32-bit data in the sub-buffer module are loaded into the register pointed to by CH_ADDR in the amplitude and phase control module, and then the corresponding TR channel amplitude and phase control signal output pins are updated to the required level state. Specifically, each time the A_P_CTRL_CHn<19:0> (n=0~3) pin state is updated, the bits from high to low are updated to D19 to D0 respectively.

[0103] Specifically, to input read command data into the CNC unit and thus read the control value of the amplitude and phase control signal output pin of the TR channel of its distributed satellite module 1003, taking the first satellite submodule 10031 as an example, its Q_ADDR_SEL pin is connected to the "00" level, and the input data reference... Figure 11 In the 32-bit serial data, MS is logic "0", RW is logic "1", DC is logic "1", Q_ADDR[1:0] is "00", CH_ADDR[1:0] is consistent with the output pin of the amplitude and phase control signal of the TR channel, and DATA[19:0] is 20 bits of logic "0". Further, at the rising edge of CS2, the 32-bit data is loaded into the sub-buffer module of the first satellite sub-module 10031. Further, at the rising edge of LD_RW, the high 8 bits of the 32-bit data stored in the sub-buffer module of the first satellite sub-module corresponding to Q_ADDR[1:0] are combined with the 20 bits of data in the register pointed to by CH_ADDR in the amplitude and phase control module to form a new 32-bit parallel data (the low 4 bits are all padded with logic "1"). This data is then written back to the sub-shift serial-to-parallel module at the first rising edge of CLK2 after LD_RW reaches a high level. Simultaneously with the input of the next frame of data, it is input to the main control module 1002 via the RD_DOUT pin and output via the DOUT pin. When continuously inputting write command data into the CNC unit, the DOUT output is the 32-bit serial data input via DATA from the previous frame.

[0104] For example, in some possible implementations, the microwave monolith includes a numerical control unit as described above.

[0105] For example, the microwave monolith also includes an amplifier and a power divider; the amplifier is used to amplify the signal input to the microwave monolith to obtain a first signal; the power divider is used to divide the first signal to obtain multiple sets of power-divided signals, and input the multiple sets of power-divided signals into the microwave monolith.

[0106] It should be understood that the sequence number of each step in the above embodiments does not imply the order of execution. The execution order of each process should be determined by its function and internal logic, and should not constitute any limitation on the implementation process of the embodiments of this application.

[0107] The above-described embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be included within the protection scope of this application.

Claims

1. A numerical control unit for a satellite distributed configuration, comprising: Decoupling capacitor module, main control module, and distributed satellite module; The positive terminal of the decoupling capacitor module is connected to the power supply pin of the CNC unit, and the negative terminal of the decoupling capacitor module is connected to the ground pin of the CNC unit. The power supply pin of the main control module is connected to the power supply pin of the numerical control unit, and the ground pin of the main control module is connected to the ground pin of the numerical control unit. The main control module adopts a data input method that samples serial data on the rising edge of the clock and transmits the most significant bit first. The main control module adopts a data output method that outputs serial data on the falling edge of the clock and transmits the most significant bit first. The main control module is connected to the distributed satellite module. The distributed satellite module includes a first satellite submodule, a second satellite submodule, a third satellite submodule, and a fourth satellite submodule. The power supply pin of the first satellite submodule is connected to the power supply pin of the numerical control unit (NC unit), and the ground pin of the first satellite submodule is connected to the ground pin of the NC unit. The power supply pin of the second satellite submodule is connected to the power supply pin of the NC unit, and the ground pin of the second satellite submodule is connected to the ground pin of the NC unit. The power supply pin of the third satellite submodule is connected to the power supply pin of the NC unit, and the ground pin of the third satellite submodule is connected to the ground pin of the NC unit. The power supply pin of the fourth satellite submodule is connected to the power supply pin of the NC unit, and the ground pin of the fourth satellite submodule is connected to the ground pin of the NC unit. Each time the numerical control unit receives a frame of serial data, the main control module, the first satellite submodule, the second satellite submodule, the third satellite submodule, and the fourth satellite submodule simultaneously receive this frame of serial data. Each time the numerical control unit receives a frame of serial data, there is a corresponding read feedback or write feedback; each time the numerical control unit receives a frame of serial data, it performs a read operation or write operation on at least one of the main control module, the first satellite sub-module, the second satellite sub-module, the third satellite sub-module, or the fourth satellite sub-module. The connection methods between the first satellite submodule and the main control module, the second satellite submodule and the main control module, the third satellite submodule and the main control module, and the fourth satellite submodule and the main control module are the same; The decoupling capacitor module is a CMOS circuit, and the decoupling capacitor module includes a first field-effect transistor and a second field-effect transistor. The first field-effect transistor is a P-channel field-effect transistor, and the second field-effect transistor is an N-channel field-effect transistor. The source and substrate of the first field-effect transistor are the positive terminal of the decoupling capacitor module, and the gate of the first field-effect transistor is connected to the drain of the second field-effect transistor; the source and substrate of the second field-effect transistor are the negative terminal of the decoupling capacitor module, and the gate of the second field-effect transistor is connected to the drain of the first field-effect transistor. The equivalent capacitance value of the decoupling capacitor module is calculated using the following formula: in, i The current applied across the decoupling capacitor module is a small signal. v The voltage of the small signal applied across the decoupling capacitor module. f The frequency of the small signal applied across the decoupling capacitor module; In the decoupling capacitor module, the gate width and length of the P-channel field-effect transistor are 1.5um and 4um, respectively, while the gate width and length of the N-channel field-effect transistor are 1.5um and 2.5um, respectively.

2. The numerical control unit for a satellite distributed configuration as described in claim 1, characterized in that, The main control module includes: a main shift serial-to-parallel conversion module, a main buffer module, a main common control signal register module, and a main logic control module; When the main control module is working, serial data is input to the main shift serial-to-parallel module through the main control serial data input pin when the main control chip select enable and the first-level latch signal input pin are at a low level. When the main control chip select enable and the first-level latch signal input pin are on the rising edge, the main shift serial-to-parallel module will convert the parallel data and transmit it to the main cache module. At the same time, the main logic control module will extract the key function bit data to determine whether the input data is a common control write instruction, a common control signal readback instruction, or an irrelevant instruction. If the input data is determined to be a common control write instruction, when the main control secondary latch and readback control signal input pin is at a rising edge, the corresponding data registered in the main cache module is written to the main common control signal register module. The main logic control module extracts the address information from this write instruction data and updates the data information therein to the corresponding common control signal output pin or reserved control signal output pin. When updating the state value of the reserved control signal output pin, the main logic control module extracts the soft reset function bit data therein and generates a low-level pulse signal lasting for 2 CLK cycles after a delay of 1.5 CLK cycles, which is output by the main control soft reset signal output pin. If the input data is determined to be a common control signal readback instruction, when the main control secondary latch and readback control signal input pin is at the rising edge, the instruction information retained in the main cache module and the corresponding control data information in the main common control signal register module are combined to form new parallel data. When the main control secondary latch and readback control signal input pin reaches the high level, the data is filled into the main shift serial-to-parallel module at the rising edge of the first CLK signal, and is serially output through the main control serial output pin at the same time as the next frame of serial data input. If the input data is determined to be an irrelevant instruction, the main control module will not perform any read or write operations on the main common control signal register module; the main logic control module detects the rising edge of the main control secondary latch and readback control signal input pin and extracts the signal of the main control secondary latch and readback control signal input pin after the rising edge for one CLK pulse cycle, which is then output by the main control LD detection signal output pin.

3. The numerical control unit for a satellite distributed configuration as described in claim 1, characterized in that, The numerical control unit also includes a reset module; The power supply pin of the reset module is connected to the power supply pin of the CNC unit, the ground pin of the reset module is connected to the ground pin of the CNC unit, and the reset signal output pin of the reset module is connected to the main control module, the first satellite sub-module, the second satellite sub-module, the third satellite sub-module and the fourth satellite sub-module respectively, providing a reset signal during the power-on and power-off processes of the CNC unit.

4. The numerical control unit for a satellite distributed configuration as described in claim 1, characterized in that, The internal structure and pinout of the first satellite submodule, the second satellite submodule, the third satellite submodule, and the fourth satellite submodule are all identical.

5. The numerical control unit for a satellite distributed configuration as described in claim 4, characterized in that, The first satellite submodule includes: a sub-shift serial-to-parallel module, a sub-buffer module, a TR channel enable and amplitude / phase control module, and a sub-logic control module; The first satellite submodule adopts a data input method that samples serial data on the rising edge of the clock and transmits the most significant bit first, and the first satellite submodule adopts a data output method that outputs serial data on the falling edge of the clock and transmits the most significant bit first. When the first satellite submodule is working, serial data is input to the sub-shift serial-to-parallel module through the submodule serial data input pin when the submodule chip select enable and first-level latch signal input pins are at a low level; When the submodule chip select enable and the first-level latch signal input pin are at the rising edge, the sub-shift serial-to-parallel module will convert the parallel data and transmit it to the sub-buffer module. At the same time, the sub-logic control module extracts the key function bit data to determine whether the parallel data is a TR channel enable or amplitude-phase control write instruction, a TR channel enable or amplitude-phase control status readback instruction, or an irrelevant instruction. If it is a TR channel enable or amplitude-phase control write instruction, when the input pin of the submodule secondary latch and readback control signal is at the rising edge, the data registered in the sub-buffer module is written to the TR channel enable and amplitude-phase control module. Then, the corresponding channel switch and TR enable or amplitude-phase control data control the multi-functional circuit unit of the corresponding channel in the microwave single chip according to the channel addressing information extracted by the sub-logic control module. If the input data is determined to be a TR channel enable or amplitude-phase control status readback instruction, when the submodule secondary latch and readback control signal input pin is at the rising edge, the instruction information retained in the sub-buffer module and the corresponding control data information in the TR channel enable and amplitude-phase control module are combined to form new parallel data. When the first CLK signal after the submodule secondary latch and readback control signal input pin reaches the high level is at the rising edge, it is filled into the sub-shift serial-to-parallel module, and at the same time as the next frame of serial data input, it is read back to the main control module by the readback data output pin and output through the main control serial output pin. If the input data is determined to be an irrelevant instruction, the first satellite submodule will not perform any read or write operations on the TR channel enable and amplitude / phase control module.

6. A microwave monolithic chip, characterized in that, Includes a numerical control unit for a satellite distributed configuration as described in any one of claims 1 to 5.

7. The microwave monolithic chip as described in claim 6, characterized in that, The microwave monolithic chip also includes: an amplifier and a power divider; The amplifier is used to amplify the signal input to the microwave chip to obtain a first signal; The power divider is used to divide the first signal into multiple sets of power divided signals, and input the multiple sets of power divided signals into the numerical control unit.

8. An antenna element, characterized in that, Includes a numerical control unit for a satellite distributed configuration as described in any one of claims 1 to 5.

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