A frequency deviation correction method for PLC system based on FPGA

Abstract

The present invention relates to a frequency deviation correction method for a PLC system based on FPGA, and belongs to the field of mobile communications. The method includes a frequency domain signal processing module process, a frequency deviation estimation module process, and a frequency deviation compensation module process. The present invention uses the cyclic prefix in the OFDM symbol to perform channel compensation; performs frequency deviation adjustment in the frequency domain; adds multi-symbol averaging and multi-frame averaging in the frequency deviation estimation module; optimizes the frequency deviation compensation module; improves the utilization rate of transmission resources, the accuracy of frequency deviation estimation, uses fewer resources, is easier to implement, and solves the problem that the low-voltage power line broadband carrier communication system only sends the real part of the base signal on the power line, which makes it inconvenient to perform clock deviation compensation at the receiving and transmitting end in the time domain part of the frame structure.

Description

Technical Field

[0001] The invention belongs to the field of mobile communications, and in particular relates to a frequency deviation correction method of a PLC system based on FPGA. Background Art

[0002] Power Line Communication (PLC) has been widely used in smart grid, automatic smart meter reading and other fields. Since the system works in the 2-30MHz frequency band, the characteristics of the power line channel determine that it has strong multipath fading, a large amount of narrowband interference and pulse interference.

[0003] Orthogonal Frequency Division Multiplexing (OFDM) can not only realize parallel transmission of signals but also has strong anti-interference ability. Therefore, many foreign PLC standard organizations have begun to customize PLC protocols based on OFDM technology.

[0004] In the PLC system, due to the use of orthogonal frequency division multiplexing (OFDM) modulation technology, frequency offset has a great impact on the performance of the system. Frequency offset is divided into carrier frequency offset and sampling frequency offset. Since the PLC system uses baseband transmission, we only consider the sampling frequency offset. The sampling frequency offset is due to the fact that the frequencies of the digital-to-analog converter (ADC) at the transmitter and the analog-to-digital converter (DAC) at the receiver are not exactly the same, causing the sampling frequency to slowly shift. In the time domain, it manifests as an offset of the sampling point, and in the frequency domain, it manifests as a phase rotation of the received signal. The frequency domain algorithm mainly uses pilot signals or training sequences to estimate the phase rotation caused by the sampling frequency offset. Summary of the invention

[0005] In view of this, the purpose of the present invention is to provide a frequency offset correction method for a PLC system based on FPGA to solve the problem of the influence of spectrum offset on the performance of the PLC system in the prior art. The present invention uses the cyclic prefix in the OFDM symbol to perform channel compensation; adjusts the frequency offset in the frequency domain; adds multi-symbol averaging and multi-frame averaging in the frequency offset estimation module; and optimizes the frequency offset compensation module, thereby solving the problem of the influence of spectrum offset on the performance of the PLC system in the prior art.

[0006] In order to achieve the above object, the present invention provides the following technical solutions:

[0007] A frequency deviation correction method for a PLC system based on FPGA, the method specifically comprises the following steps:

[0008] S1: The receiving end receives the frequency domain signal after the fast Fourier transform FFT, takes out 512 points of data from the frequency domain signal in sequence, and stores them in a random access memory 1;

[0009] S2: The frequency domain signal is conjugate-correlated with the data in the random access memory 1 in the frequency domain to obtain a cross-correlation sequence, where the cross-correlation sequence is the preamble information of each subcarrier in the current orthogonal frequency division multiplexing OFDM symbol;

[0010] S3: adding and averaging the leading information in the obtained cross-correlation sequence within the working frequency band to obtain leading symbols of several OFDM symbols, and before frame synchronization is completed, respectively adding and averaging the several leading symbols to obtain leading symbols after multi-symbol addition and averaging; the leading symbols after multi-symbol addition and averaging obtained are respectively leading symbols after real part multi-symbol addition and averaging and leading symbols after imaginary part multi-symbol addition and averaging;

[0011] S4: Divide the leading symbol obtained by adding and averaging the imaginary multi-symbols by the leading symbol obtained by adding and averaging the real multi-symbols, and round the decimal part of the result to 32 bits; locally generate an average subcarrier number according to the working frequency band of the device, and divide the result by the locally generated average subcarrier number to obtain the frequency deviation value of subcarrier No. 1 in the first OFDM symbol in each frame;

[0012] During burst communication, the frame counter starts counting. When the counter counts less than 8 frames, the frequency deviation value of subcarrier No. 1 in the first OFDM symbol in the frame is directly output; when the counter counts to 8 frames or more, the frequency deviation values ​​of subcarrier No. 1 in the first OFDM symbol in 8 consecutive frames are added and averaged to obtain the average frequency deviation value of multi-frame signals, and the average frequency deviation value is output; when the burst communication ends, the counter is reset; the frequency deviation value is the frequency deviation estimation value;

[0013] S5: Obtain an average frequency deviation value of the multi-frame signal, and input the average frequency deviation value of the multi-frame signal into the Cordic module to obtain cosθ and sinθ of the complex frequency deviation angle, that is, the real part and imaginary part of the complex frequency deviation angle, and the complex frequency deviation angle is the frequency deviation angle of subcarrier No. 1 of the first OFDM symbol in each frame;

[0014] S6: Use the frequency deviation angle of the Sth subcarrier of the first OFDM symbol in each frame to conjugate and multiply it with the frequency deviation angle of the 1st subcarrier of the first OFDM symbol in each frame to obtain the S+1th subcarrier frequency deviation angle of the first OFDM symbol in each frame, S=1,2,3,4...n, when S=n-1, all frequency deviation angles of the first OFDM symbol in each frame in the working frequency band are obtained, stored in the random access memory 2, and enter S7; otherwise, S=S+1 and repeat S6;

[0015] S7: read out the frequency deviation angle in the random access memory 2, conjugate and multiply it with the frequency domain signal after channel estimation, obtain the frequency domain signal after frequency deviation correction, i.e., frequency domain equalization, and store the frequency domain signal after frequency deviation correction in the random access memory 3; the frequency domain equalization calculated by S7 is the frequency domain equalization value of the first OFDM symbol in each frame; the frequency deviation increment of each subsequent OFDM symbol in each frame is equal to the frequency deviation increment of the first OFDM symbol;

[0016] S8: Repeat S8 every 1024 clock cycles, read out the frequency domain signal of the frequency offset correction of the Sth OFDM symbol in each frame from the random access memory three, then read out the frequency offset angle of the first OFDM symbol in each frame from the random access memory two, multiply the frequency offset signal of the frequency offset correction of the Sth OFDM symbol in each frame by the conjugate frequency offset angle of the first OFDM symbol in each frame, obtain the frequency domain equalization value of the S+1th symbol in each frame, store it in the random access memory three, overwrite the original data in the random access memory three; read out the updated data in the random access memory three; until this frame signal ends, pull the enable signal low, shut down the module, and obtain the complete signal after frequency offset correction.

[0017] The beneficial effects of the present invention are:

[0018] First, the present invention adopts the method of channel compensation using the cyclic prefix in the OFDM symbol, which does not need to insert a reference signal into the OFDM symbol data, thereby improving the utilization rate of transmission resources.

[0019] Secondly, the method for adjusting frequency deviation in the frequency domain proposed in the present invention solves the problem that the low-voltage power line broadband carrier communication system only sends the real part of the baseband signal on the power line, which makes it inconvenient to compensate the clock deviation of the transmitting and receiving ends in the time domain part of the frame structure.

[0020] Third, in the frequency offset estimation module of the present invention, by adding multi-symbol averaging and multi-frame averaging, compared with the conventional use of the current frame estimation value for compensation, this method can improve the accuracy of frequency offset estimation when the channel conditions are poor or the frame structure is long.

[0021] Fourthly, the present invention optimizes the frequency offset compensation module, which uses fewer resources and is easier to implement than traditional compensation methods.

[0022] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 The signal processing block diagram of the receiving end of the PLC system of the present invention;

[0025] Figure 2 This is a hardware implementation diagram of the frequency domain signal processing module of the present invention;

[0026] Figure 3 This is a flow chart of the frequency offset estimation module of the present invention;

[0027] Figure 4 This is a flow chart of the frequency offset compensation module of the present invention; DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0029] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0030] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0031] See also Figure 1 to Figure 4 , which is a frequency deviation correction method for PLC system based on FPGA.

[0032] The present invention consists of three parts: a frequency domain signal processing module, a frequency offset estimation module and a frequency offset compensation module.

[0033] The signal processing block diagram of the PLC system receiving end is as follows Figure 1 As shown, Figure 1 The frequency offset estimation, frequency offset compensation and frequency domain equalization in the system are designed by the present invention.

[0034] 1. Frequency domain signal processing module process.

[0035] The hardware implementation structure diagram of this module is as follows Figure 2 The receiving end receives the frequency domain signal after fft, which is recorded as fft_i and fft_q; 512 points of data are taken out from fft_i and fft_q in sequence and stored in ram, which are recorded as fft_data_ram_i and fft_data_ram_q;

[0036] fft_i, fft_q are conjugate correlated with fft_data_ram_i, fft_data_ram_q in the frequency domain to obtain two cross-correlation sequences, denoted as mult_itemp_w and mult_qtemp_w. mult_itemp_w and mult_qtemp_w are the leading information of each subcarrier in the current OFDM symbol;

[0037] The leading information in the working frequency band of mult_itemp_w and mult_qtemp_w is added and averaged respectively to obtain the leading symbol of the current OFDM symbol, which is recorded as sum_i and sum_q; before the frame synchronization is completed, the sum_i and sum_q of multiple leading symbols are added and averaged respectively to obtain the leading symbol of the real part and the imaginary part after the multi-symbol addition and averaging, which is recorded as acc_i and acc_q;

[0038] When processing signals, they are all complex signals. The real part and the imaginary part are processed separately using the same processing method. The real part is recorded as I path and the imaginary part is recorded as Q path.

[0039] 2. Frequency offset estimation module process.

[0040] Divide the pilot signals acc_i and acc_q after adding and averaging multiple symbols, and divide acc_q by acc_i. The result is rounded to 32 bits of the decimal part, recorded as angle_fre. According to the working frequency band of the device, the average subcarrier number is generated locally, recorded as average_subcarrier_number, and angle_fre is divided by average_subcarrier_number to obtain the frequency deviation value of subcarrier No. 1 in the first symbol of the frame, recorded as phi_rad;

[0041] Calculate the frequency deviation values ​​phi_rad_1, phi_rad_2, ..., phi_rad_6 of subcarrier No. 1 in eight consecutive frames, add them up and average them to obtain the average frequency deviation value of the multi-frame signal, recorded as output_phase; when there are less than eight frames, directly output the calculated frequency deviation value.

[0042] 3. Frequency deviation compensation module process:

[0043] like Figure 4 As shown, the output_phase calculated above is input into the cordic module to obtain the sinθ and cosθ of the complex frequency deviation angle, which are the real and imaginary parts of the complex frequency deviation angle. The complex frequency deviation angle is the frequency deviation angle of subcarrier No. 1 of the first OFDM symbol in the current frame. The frequency deviation angle is expressed as (cosθ, isinθ). Since we use the average frequency deviation calculation strategy for all subcarriers in the current symbol, we believe that the frequency deviation increment of each subsequent subcarrier is equivalent to the frequency deviation value of subcarrier No. 1.

[0044] Based on the above strategy, we use the frequency deviation angle of subcarrier 1 of the current symbol to multiply it by its own conjugate to get the frequency deviation angle of subcarrier 2. Use the frequency deviation angle of subcarrier S to do conjugate multiplication with the frequency deviation angle of subcarrier 1 to get the frequency deviation angle of subcarrier S+1. Through this method, all frequency deviation angles of the first OFDM symbol of the current frame in the working frequency band can be obtained, recorded as cos_k and sin_k, and stored in ram_1.

[0045] Read the data in ram_1 and perform conjugate multiplication with the frequency domain signals chest_i and chest_q after channel estimation to obtain the frequency domain signal after frequency offset correction, that is, frequency domain equalization. Store the signal after frequency domain equalization in ram_2, recorded as chest_compensate_I_r and chest_compensate_Q_r. The frequency domain equalization value calculated in the above steps is the frequency domain equalization value of the first OFDM symbol in the current frame. Similarly, we use the calculation method of adding and averaging the frequency offsets of multiple symbols, so we believe that the frequency offset increment of each subsequent symbol in the frame is equivalent to the frequency offset value of the first symbol.

[0046] Repeat once every 1024 clock cycles, read chest_compensate_I_r, chest_compensate_Q_r of the Sth symbol from ram_2, and then read cos_k_r, sin_k_r of the first symbol from ram_1, and perform conjugate multiplication of chest_compensate_I_r, chest_compensate_Q_r with cos_k_r, sin_k_r to get the frequency domain equalization value of the S+1th symbol, and store it in ram_2 again, overwriting the original data in ram_2, and read the updated data in ram_2, recorded as fre_compensate_i and fre_compensate_q, until this frame signal ends, pull the enable signal low, shut down the module, and get the complete signal after frequency deviation correction.

[0047] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A frequency deviation correction method for a PLC system based on FPGA, characterized in that: The method specifically comprises the following steps: S1: The receiving end receives the frequency domain signal after the fast Fourier transform FFT, takes out 512 points of data from the frequency domain signal in sequence, and stores them in a random access memory 1; S2: The frequency domain signal is conjugate-correlated with the data in the random access memory 1 in the frequency domain to obtain a cross-correlation sequence, where the cross-correlation sequence is the preamble information of each subcarrier in the current orthogonal frequency division multiplexing OFDM symbol; S3: adding and averaging the leading information in the obtained cross-correlation sequence within the working frequency band to obtain leading symbols of several OFDM symbols, and before frame synchronization is completed, adding and averaging the several leading symbols to obtain a leading symbol after multi-symbol addition and averaging; The obtained leading symbols after adding and averaging multiple symbols are respectively the leading symbols after adding and averaging multiple symbols of the real part and the leading symbols after adding and averaging multiple symbols of the imaginary part; S4: Divide the leading symbol obtained by adding and averaging the imaginary multi-symbols by the leading symbol obtained by adding and averaging the real multi-symbols, and round the decimal part of the result to 32 bits; locally generate an average subcarrier number according to the working frequency band of the device, and divide the result by the locally generated average subcarrier number to obtain the frequency deviation value of subcarrier No. 1 in the first OFDM symbol in each frame; During burst communication, the frame counter starts counting. When the counter counts less than 8 frames, the frequency deviation value of subcarrier No. 1 in the first OFDM symbol in the frame is directly output; when the counter counts to 8 frames or more, the frequency deviation values ​​of subcarrier No. 1 in the first OFDM symbol in 8 consecutive frames are added and averaged to obtain the average frequency deviation value of multi-frame signals, and the average frequency deviation value is output; when the burst communication ends, the counter is reset; the frequency deviation value is the frequency deviation estimation value; S5: Obtain an average frequency deviation value of the multi-frame signal, and input the average frequency deviation value of the multi-frame signal into the Cordic module to obtain cosθ and sinθ of the complex frequency deviation angle, that is, the real part and imaginary part of the complex frequency deviation angle, and the complex frequency deviation angle is the frequency deviation angle of subcarrier No. 1 of the first OFDM symbol in each frame; S6: Use the frequency deviation angle of the Sth subcarrier of the first OFDM symbol in each frame to conjugate and multiply it with the frequency deviation angle of the 1st subcarrier of the first OFDM symbol in each frame to obtain the frequency deviation angle of the S+1th subcarrier of the first OFDM symbol in each frame, S=1,2,3,4...n, when S=n-1, all frequency deviation angles of the first OFDM symbol in each frame in the working frequency band are obtained, stored in the random access memory 2, and enter S7; Otherwise, S=S+1 and repeat S6; S7: read out the frequency deviation angle in the random access memory 2, conjugate and multiply it with the frequency domain signal after channel estimation, obtain the frequency domain signal after frequency deviation correction, i.e., frequency domain equalization, and store the frequency domain signal after frequency deviation correction in the random access memory 3; the frequency domain equalization calculated by S7 is the frequency domain equalization value of the first OFDM symbol in each frame; The frequency offset increment of each subsequent OFDM symbol in each frame is equal to the frequency offset increment of the first OFDM symbol; S8: Repeat S8 every 1024 clock cycles, read out the frequency domain signal of the frequency offset correction of the Sth OFDM symbol in each frame from the random access memory three, then read out the frequency offset angle of the first OFDM symbol in each frame from the random access memory two, multiply the frequency offset signal of the frequency offset correction of the Sth OFDM symbol in each frame by the conjugate frequency offset angle of the first OFDM symbol in each frame, obtain the frequency domain equalization value of the S+1th symbol in each frame, store it in the random access memory three, overwrite the original data in the random access memory three; read out the updated data in the random access memory three; until this frame signal ends, pull the enable signal low, shut down the module, and obtain the complete signal after frequency offset correction.

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