A dual common-mode rejection receiving circuit

Abstract

The present invention discloses a dual common-mode rejection receiver circuit, comprising a first-stage common-mode rejection circuit, a second-stage non-inverting proportional amplifier composed of a fully differential operational amplifier, a third-stage mismatched hysteresis comparator, and a fourth-stage output buffer. Direct coupling is employed between the stages. After the input bus level passes through the first-stage common-mode rejection circuit, it is attenuated to a common-mode level range determined by the common-mode swing and maximum common-mode voltage of the fully differential operational amplifier. After the signal passes through the non-inverting proportional amplifier composed of the fully differential operational amplifier, the common-mode level is stabilized. Simultaneously, the differential signal of the non-inverting proportional amplifier composed of the second-stage fully differential operational amplifier is transmitted to the hysteresis comparator, which then outputs a digital logic level. The output port of the hysteresis comparator is connected to an output buffer composed of an inverter chain. This invention simplifies the circuit structure and reduces the overall power consumption of the circuit while ensuring accurate reception of both dominant and recessive levels.

Description

Technical Field

[0001] The invention belongs to the technical field of CAN bus, and in particular relates to a dual common-mode suppression receiving circuit. Background Art

[0002] CAN bus technology, with its high speed and high reliability, is widely used in aerospace, marine, sensor detection, medical, and other fields. One of the primary functions of a CAN transceiver chip is to receive both explicit and implicit signals on the physical CAN bus. With the increasing adoption of CAN bus transceivers, the demand for higher communication rates and the increasing complexity and diversity of application environments have led to an increased difficulty in designing receiver circuits. In particular, in a CAN bus communication network, the two communication buses are typically very long, making them susceptible to high-frequency electromagnetic interference. This interference affects both communication buses equally, manifesting as a common-mode signal within the differential signal.

[0003] The circuit structure of the existing scheme is as follows Figure 1 As shown in the figure, the receiving circuit consists of a voltage divider circuit formed by a resistor array, an open-loop comparator, and a hysteresis comparator. CANH and CANL are the bus voltages on the physical twisted pair, VREF is the external reference voltage, and RXD is a communication port of the CAN transceiver with a load capacitance of 15pF. The resistor divider circuit creates an attenuation factor. When the common-mode voltage of the bus fluctuates between -30V and 60V, the bus signals CANH and CANL pass through the resistor divider circuit, and the differential signal enters the differential amplifier. After amplification, it enters the hysteresis comparator and finally outputs a logic signal.

[0004] Disadvantages of the existing technology: The resistor divider circuit consumes significant power to stabilize the common-mode level at a fixed 2.5V level. The second-stage circuit uses an open-loop operational amplifier, which cannot effectively identify invisible levels. According to existing standards, when the differential signal on the bus is less than 500mV, the RXD port will output a logic "1." However, in this circuit, a differential level less than 500mV may still be amplified by the differential amplifier after passing through the resistor divider circuit. After passing through the comparator, RXD will output an incorrect logic signal. Due to the characteristics of the open-loop amplifier, the response speed of the dominant signal and the recessive signal are different, which deteriorates the symmetry of the loop delay of the entire CAN transceiver, resulting in a shortened bit width of each signal bit. In severe cases, this can cause errors in the information received by the receiver. Summary of the Invention

[0005] In order to overcome the problems existing in the above-mentioned prior art, the purpose of the present invention is to provide a dual common-mode suppression receiving circuit, which is divided into four stages, namely: a first-stage common-mode suppression circuit, a second-stage common-mode suppression circuit, a third-stage hysteresis comparator circuit and a fourth-stage output driver stage circuit. The dual common-mode suppression technology enables the circuit to have a good common-mode rejection ratio, which can filter out the common-mode interference signal of the bus. The two-stage common-mode suppression circuit also has low latency and good symmetry, which improves the speed of the circuit and the accuracy of the received signal. The present invention introduces a mismatch to move the transfer characteristic curve of the hysteresis comparator in the positive direction, thereby simplifying the circuit structure while ensuring accurate reception of the explicit and implicit levels, and reducing the overall power consumption of the circuit.

[0006] In order to achieve the above object, the technical solution adopted by the present invention is:

[0007] A dual common-mode rejection receiving circuit includes a four-stage structure consisting of a common-mode rejection circuit, a fully differential in-phase proportional amplifier, a mismatched hysteresis comparator, and an output buffer, with direct coupling between stages.

[0008] After the input bus level is attenuated by the common-mode suppression circuit, the common-mode level fluctuation range of the input differential signal will be controlled within the input common-mode range of the fully differential operational amplifier. After the signal passes through the in-phase proportional amplifier composed of the fully differential operational amplifier, the common-mode level will be stabilized. At the same time, the differential signal of the in-phase proportional amplifier composed of the fully differential operational amplifier is transmitted to the hysteresis comparator, and the digital logic level is output after passing through the hysteresis comparator; the output of the hysteresis comparator is connected to the output buffer composed of the inverter chain.

[0009] The first-stage common-mode suppression circuit includes a resistor string consisting of R1 to R8 connected in cascade to generate a fixed attenuation ratio, and eight feedback loops consisting of transistors M1 to M8 and resistors R9 to R14. The resistor string is used to generate a fixed attenuation ratio, and the feedback loop is used to stabilize the voltage at point C, which is located between R4 and R5 and is the common mode point of the differential signal.

[0010] The transistors M1 to M4 all operate in a common-source amplifier mode. The common-source amplifier has a negative gain. When the level on the bus increases, the voltages of nodes A, B, E, and F also increase. Node A is located at the gates of transistors M1 and M3, node B is located at the gates of transistors M2 and M4, node E is located at the gates of transistors M5 and M7, and node F is located at the gates of transistors M6 and M8.

[0011] The four feedback loops formed by M5, M6, M7, M8, R11, R12, R13 and R14 detect the voltage fluctuations at the E and F nodes, and reduce the voltage fluctuations at the A and B nodes;

[0012] The transistor M7, resistor R13, and R2 form a feedback loop; the transistor M5, resistor R14, and R2 form a feedback loop; the transistor M8, resistor R11, and R7 form a feedback loop; the transistor M6, resistor R12, and R7 form a feedback loop;

[0013] M1 to M4, R9, and R10 also form four feedback loops, all with output nodes at point C. They jointly control the voltage fluctuation at node C by detecting the voltage fluctuation at nodes A and B.

[0014] Nodes A, B, and C are all on the same voltage path. By detecting the voltages of nodes A and B, the voltage of node C is controlled through negative feedback. Transistor M1 and transistor M2 share resistor R10 to form two feedback loops, and transistor M3 and transistor M4 share resistor R9 to form two feedback loops. The output nodes of the four feedback loops are all at node C, and the voltage fluctuations of node C are jointly controlled by detecting the voltage fluctuations of nodes A and B.

[0015] The transistor M3, resistors R9, R3, and R4 form a feedback loop; the transistor M4, resistors R9, R5, and R6 form a feedback loop; the transistor M1, resistors R10, R3, and R4 form a feedback loop; and the transistor M2, resistors R10, R5, and R6 form a feedback loop.

[0016] The first-stage common-mode suppression circuit has eight feedback loops to stabilize the voltage of node C, of ​​which four feedback loops indirectly stabilize the voltage of node C by stabilizing the voltage fluctuations of nodes A and B, and the other four feedback loops directly control the voltage of node C.

[0017] The second-stage common-mode suppression circuit is a proportional amplifier composed of a fully differential operational amplifier. It is used to suppress the common-mode signal a second time and protect the integrity of the differential signal. The resistance values ​​of RF1, RF2, RF3, and RF4 are appropriately designed based on the voltage divider factor of the first-stage circuit.

[0018] The fully differential operational amplifier includes transistors M1-M5 forming the first stage of the operational amplifier, transistors M6-M9 forming the second stage of the operational amplifier, transistors M9-M14 and R3, R4 forming a common-mode negative feedback circuit, and capacitors C1, C2 and R1, R2 ensuring loop stability;

[0019] The outputs OUTP and OUTN of the first-stage circuit are respectively connected to the feedback resistors REF1 and REF2 of the second-stage circuit; the common-mode negative feedback circuit includes transistors M11, M12, M13, M14, M9, R3 and R4, and the common-mode negative feedback circuit is part of the circuit of the second-stage fully differential operational amplifier.

[0020] The second-stage circuit re-amplifies the attenuated differential signal at a certain ratio, which is used to improve the detection accuracy and speed of the differential signal; after passing through the first-stage common-mode suppression circuit, the common-mode level of the differential signal still fluctuates within a small range, and the differential amplifier has a higher common-mode rejection ratio. There is a common-mode negative feedback circuit in the fully differential amplifier. Due to the effect of common-mode negative feedback, the differential signal is finally accurately stabilized.

[0021] The third-stage hysteresis comparator adds a mismatched transistor M14 to the second-stage positive feedback comparison stage, so that the transfer characteristic curve of the hysteresis comparator moves in the positive direction; the second-stage positive feedback comparison stage also adds a mismatched transistor M14, which is used to make the currents passing through transistors M12 and M11 no longer equal in the steady state, thereby causing the transfer characteristic curve of the hysteresis comparator to move toward the positive half-axis direction; by adjusting the amplifier coefficient of the fully differential operational amplifier and the sizes of M9-M14 in the hysteresis comparator, RXD outputs a low level or RXD outputs a high level.

[0022] The gate terminal of M14, the drain terminal of M14, the gate terminal of M11 and the drain terminal of M11 are connected together, and the source terminal of M12 and M11 are connected together.

[0023] To address the common-mode suppression issue, this invention employs dual common-mode suppression technology, employing two circuits to suppress common-mode fluctuations on the bus. Eight feedback loops are incorporated into the first-stage circuit. Under a wide range of common-mode fluctuations, the common-mode level of the differential signal output by the first-stage common-mode suppression circuit is stabilized within the operating range of the second-stage common-mode suppression circuit. Common-mode negative feedback in the second-stage circuit ultimately stabilizes the common-mode level at a precise 2.5V.

[0024] To ensure efficient transmission of differential signals, the receiving circuit employs a fully symmetrical structure, ensuring the final loop delay symmetry meets the speed requirements of the CAN transceiver. Furthermore, the attenuated differential signal is amplified in the second-stage circuit to reduce overall reception delay. A mismatched hysteresis comparator is used in the third-stage circuit to address the issue of recessive level recognition and reception. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] Figure 1 This is a schematic diagram of the traditional CAN bus transceiver receiving circuit structure.

[0026] Figure 2 This is a schematic diagram of the receiving circuit structure of the CAN bus transceiver of the present invention.

[0027] Figure 3 This is a schematic diagram of a traditional resistor voltage divider circuit.

[0028] Figure 4 This is a schematic diagram of the first-stage common-mode suppression circuit of the present invention.

[0029] Figure 5 This is a circuit topology diagram of a fully differential op amp.

[0030] Figure 6 Schematic diagram of the dynamic performance indicators of the CAN bus transceiver.

[0031] Figure 7 Schematic diagram of the circuit topology of the hysteresis comparator in the present invention.

[0032] Figure 8 Schematic diagram of the transfer curve of the hysteresis comparator. DETAILED DESCRIPTION

[0033] The present invention will be described in further detail below with reference to the accompanying drawings.

[0034] The present invention provides a dual common-mode suppression circuit applied to a CAN bus transceiver.

[0035] The basic receiving circuit is as follows Figure 2 As shown in the figure, the first stage is a common-mode rejection circuit, the second stage is a non-inverting proportional amplifier composed of fully differential op amps, the third stage is a mismatched hysteresis comparator, and the fourth stage is an output buffer. Direct coupling is used between the stages. After the input bus voltage passes through the first-stage common-mode rejection circuit, it is attenuated to a common-mode voltage range determined by the common-mode swing and maximum common-mode voltage of the fully differential op amps. After passing through the non-inverting proportional amplifier composed of the fully differential op amps, the common-mode voltage is precisely stabilized at 2.5V. Simultaneously, the differential signal is passed to the hysteresis comparator, which then outputs a digital logic level. Because the RXD port is loaded with a large 15pF capacitor, an output buffer consisting of a chain of inverters is added to the output of the hysteresis comparator.

[0036] Traditional voltage divider circuits such as Figure 3As shown, the voltage at the center point C of the voltage divider circuit is set to a fixed voltage using two current-conducting elements, R7 and R8. The attenuation network is formed by a resistor string. However, the disadvantage of this circuit structure is that when the common-mode voltage fluctuates significantly, the attenuation ratio of the resistor string also increases. As a result, the useful differential signal is also attenuated, and detection of the useful differential signal becomes less accurate as the attenuation factor increases. Increasing the attenuation factor also increases the area of ​​the resistors, making it difficult to suppress large common-mode fluctuations using resistors alone.

[0037] The first stage common mode suppression circuit of the present invention is as follows Figure 4 As shown, R1-R8 form a resistor string that produces a fixed attenuation ratio. M1-M8 and R9-R14 form eight feedback loops, which stabilize the voltage at point C, the common-mode point of the differential signal. Transistors M1-M4 operate in common-source amplifier mode. Common-source amplifiers have negative gain. When the bus voltage increases, the voltages at nodes A, B, E, and F also increase. The four feedback loops formed by M5, M6, M7, M8, R11, R12, R13, and R14 detect voltage fluctuations at nodes E and F, thereby reducing voltage fluctuations at nodes A and B. M1-M4, R9, and R10 also form four feedback loops, all with output nodes at point C. By detecting voltage fluctuations at nodes A and B, they collectively control voltage fluctuations at node C. Resistors R9, R10, R11, R12, R13, and R14 limit the transistor's source-drain voltage to reduce power consumption. They also increase the impedance at the source of the common-source amplifier, improving its gain and achieving better feedback control, thus achieving a trade-off between power consumption and gain. In this solution, the first-stage common-mode suppression circuit has eight feedback loops to stabilize the voltage at node C. Four of these feedback loops indirectly stabilize the voltage at node C by stabilizing voltage fluctuations at nodes A and B, while the remaining four feedback loops directly control the voltage at node C. Therefore, when the common-mode level of the bus fluctuates between -30V and 60V, the voltage at node C is stably controlled within a small range.

[0038] Although R1, R2, R3, R4, R5 and R6 in the designed first-stage common-mode suppression circuit can produce an attenuation factor to attenuate the common-mode level on the bus to a certain range, thereby playing the role of common-mode suppression, as a result of attenuation, the useful differential signal is also attenuated, which will affect the detection accuracy and speed of the differential signal. This problem will be solved by the proportional amplifier composed of the fully differential operational amplifier in the second-stage circuit proposed in this solution. Figure 2As shown in the figure, the second-stage common-mode suppression circuit is a proportional amplifier composed of a fully differential operational amplifier. Its main purpose is to suppress the common-mode signal for the second time. Another function is to protect the integrity of the differential signal. Reasonable design of the resistance values ​​of RF1, RF2, RF3 and RF4 can ultimately make the second-stage common-mode suppression circuit have a fixed gain for the differential signal. The circuit structure of the fully differential operational amplifier is shown in the figure. Figure 5 As shown in the figure, transistors M1-M5 form the first stage of the operational amplifier, M6-M9 the second stage, M9-M14 and R3, R4 form the common-mode negative feedback circuit, and capacitors C1, C2 and R1, R2 ensure loop stability. The second stage circuit re-amplifies the attenuated differential signal at a specific ratio, improving the accuracy and speed of differential signal detection. After passing through the first stage common-mode rejection circuit, the common-mode level of the differential signal still fluctuates within a small range, resulting in a higher common-mode rejection ratio for the differential amplifier. The presence of common-mode negative feedback in a fully differential amplifier ultimately stabilizes the differential signal at a precise 2.5V.

[0039] The total common mode rejection ratio of the circuit can be expressed as A CMRR =A CMRR1 *A CMRR2 , where A CMRR1 is the common mode rejection ratio of the first stage circuit, A CMRR2 is the common-mode rejection ratio of the second-stage circuit. Based on the dual common-mode rejection technology proposed in this invention, the receiving circuit can operate normally under abnormal bus voltages ranging from -30°C to 60°C. By designing a high GBW (gain-bandwidth product), signal latency is minimized. This solution utilizes symmetry between the first-stage and second-stage common-mode rejection circuits, ensuring that the differential signal maintains a high degree of symmetry after passing through the two circuit stages.

[0040] CAN transceivers have three different propagation delays: transmit delay, receive delay, and loop delay. Figure 6 The definition of three delays of CAN bus transceiver is explained, TXD is the transmit signal, Vdiff is the differential signal on the bus, and RXD is the receive signal. TX is the sending delay, t RX is the receiving delay, t Loop is the loop delay, which is equal to the sum of the sending delay and the receiving delay. Figure 6 As shown, t Loop1 is the loop delay for receiving the recessive differential signal, t Loop2 is the loop delay of receiving the dominant signal, if t Loop1 ≠t Loop2 , it will cause loop delay asymmetry, which will cause t Bit (TXD)≠tBit (RXD), where t Bit (TXD) is the transmit bit width, t Bit (RXD) is the receive bit width, which can cause errors in the information received by the receiver. In the circuit of the present invention, the symmetry of the circuit structure and the second-stage amplification and recovery of the differential signal significantly improve the problem of loop delay asymmetry, maintaining good loop delay symmetry even under a wide range of common-mode fluctuations and various process corners.

[0041] The third stage circuit is a hysteresis comparator, the circuit topology is as follows Figure 7 As shown in the figure. This comparator improves the circuit structure based on the traditional hysteresis comparator, and adds a mismatch transistor M14 in the second positive feedback comparison stage, so that the transfer characteristic curve of the hysteresis comparator moves in the positive direction. Figure 6 It can be seen that in the CAN receiver's receiving specification, when the differential level is greater than 900mV, RXD outputs a low level, and when the differential signal is less than 500mV, RXD outputs a high level. The transmission curve of the traditional comparator is as follows Figure 8 As shown in (a), the traditional hysteresis comparator cannot meet the application requirements of the present invention. The hysteresis comparator in the present invention is composed of a pre-amplifier stage, a positive feedback comparison stage and a Class AB output driver stage.

[0042] The main function of the first stage pre-amplifier is to speed up the comparison and reduce the transmission delay. In the second stage positive feedback comparison stage, a mismatched transistor M14 is added, so that the currents passing through M12 and M11 are no longer equal in the steady state, which causes the transfer characteristic curve of the hysteresis comparator to move toward the positive half axis direction, as shown in Figure 2. Figure 8 By adjusting the amplifier coefficient of the fully differential op amp and the size of M9-M14 in the hysteresis comparator, RXD can output a low level when the differential level is greater than 900mV, and a high level when the differential signal is less than 500mV.

[0043] The structure of the present invention utilizes dual common-mode suppression technology, employing a two-stage circuit with common-mode suppression capabilities to suppress voltage fluctuations from the bus. The first-stage common-mode suppression circuit features an innovative circuit structure, employing two stages of eight feedback loops to stabilize the common-mode voltage of the differential output signal. M5-M8 and R11-R14 form the first-stage feedback loop, stabilizing the common-mode voltage at nodes A and B, and thus at the central node C. M1-M4 and R9 and R10 form the second-stage feedback loop, directly stabilizing the common-mode voltage at the central node. The resistor at the transistor drain terminal acts as a current limiter, increasing the output impedance of the common-source amplifier and the loop gain, further stabilizing the common-mode voltage and achieving a compromise between power consumption and gain. The second-stage common-mode suppression circuit also exhibits resistance to common-mode interference, ultimately stabilizing the common-mode voltage at a fixed 2.5V. The second-stage common-mode suppression circuit recovers the differential signal after attenuation by the first-stage common-mode suppression circuit, ensuring low latency and high accuracy in differential signal reception. By utilizing a two-stage common-mode suppression circuit, the entire circuit system can receive differential signals on the bus despite common-mode voltage fluctuations ranging from -30V to 60V caused by electromagnetic interference. In the first-stage common-mode suppression circuit, the resistance and size of the left-half resistor and transistor are identical to those of the right-half, resulting in a completely symmetrical first-stage and second-stage common-mode suppression circuits. This symmetrical circuit structure ensures the symmetry of the differential signal, improves the symmetry of the signal loop delay, and guarantees the reception quality of the differential signal. Furthermore, the present invention introduces mismatched transistors into the hysteresis comparator, so the currents flowing through M9 and M10 in the steady state become unequal, shifting the transfer characteristic curve of the hysteresis comparator to the positive half axis to meet the reception specifications of the CAN receiver circuit.

[0044] The above content is only for explaining the technical idea of ​​the present invention and cannot be used to limit the protection scope of the present invention. Any changes made on the basis of the technical solution in accordance with the technical idea proposed by the present invention shall fall within the protection scope of the claims of the present invention.

Claims

1. A dual common-mode rejection receiving circuit, characterized in that: It includes a first-stage common-mode suppression circuit, a second-stage common-mode suppression circuit, a third-stage hysteresis comparator, and a fourth-stage output buffer, with direct coupling between stages. The second-stage common-mode suppression circuit is a proportional amplifier composed of a fully differential operational amplifier, which is used to perform a second suppression on the common-mode signal and protect the integrity of the differential signal. After the input bus level is attenuated by the common-mode suppression circuit, the common-mode level fluctuation range of the input differential signal will be controlled within the input common-mode range of the fully differential operational amplifier. After the signal passes through the in-phase proportional amplifier formed by the fully differential operational amplifier, the common-mode level will be stabilized. At the same time, the differential signal of the in-phase proportional amplifier formed by the fully differential operational amplifier is transmitted to the hysteresis comparator, and after passing through the hysteresis comparator, a digital logic level is output; the output of the hysteresis comparator is connected to the output buffer formed by the inverter chain; The first-stage common-mode suppression circuit includes a resistor string consisting of R1 to R8 connected in cascade, and eight feedback loops consisting of transistors M1 to M8 and resistors R9 to R14. The resistor string is used to generate a fixed attenuation ratio, and the feedback loop is used to stabilize the voltage at point C, which is located between R4 and R5 and is the common-mode point of the differential signal. The transistors M1 to M4 all operate in a common-source amplifier mode. The common-source amplifier has a negative gain. When the level on the bus increases, the voltages of nodes A, B, E, and F also increase. Node A is located at the gates of transistors M1 and M3, node B is located at the gates of transistors M2 and M4, node E is located at the gates of transistors M5 and M7, and node F is located at the gates of transistors M6 and M8. The four feedback loops formed by M5, M6, M7, M8, R11, R12, R13 and R14 detect the voltage fluctuations at the E and F nodes, and reduce the voltage fluctuations at the A and B nodes; The first-stage common-mode suppression circuit has eight feedback loops to stabilize the voltage at node C. Four of these feedback loops indirectly stabilize the voltage at node C by stabilizing the voltage fluctuations at nodes A and B, while the remaining four feedback loops directly control the voltage at node C. The fully differential operational amplifier includes transistors M1-M5 forming the first stage of the operational amplifier, and transistors M6-M9 forming the second stage of the operational amplifier.

2. The dual common-mode rejection receiving circuit according to claim 1, characterized in that: The transistor M7, resistor R13, and R2 form a feedback loop; the transistor M5, resistor R14, and R2 form a feedback loop; the transistor M8, resistor R11, and R7 form a feedback loop; the transistor M6, resistor R12, and R7 form a feedback loop; M1-M4, R9, and R10 also form four feedback loops, all with output nodes at point C. They jointly control the voltage fluctuation at node C by detecting the voltage fluctuation at nodes A and B. Nodes A, B, and C are all on the same voltage path. By detecting the voltages at nodes A and B, the voltage at node C is controlled through negative feedback. Transistors M1 and M2 share resistor R10, forming two feedback loops. Transistors M3 and M4 share resistor R9, forming two feedback loops. The output nodes of all four feedback loops are at node C. By detecting voltage fluctuations at nodes A and B, the voltage fluctuations at node C are collectively controlled. The transistor M3, resistors R9, R3, and R4 form a feedback loop; the transistor M4, resistors R9, R5, and R6 form a feedback loop; the transistor M1, resistors R10, R3, and R4 form a feedback loop; and the transistor M2, resistors R10, R5, and R6 form a feedback loop.

3. The dual common-mode rejection receiving circuit according to claim 1, characterized in that: Capacitors C1, C2 and resistors R1, R2 to ensure loop stability; The outputs OUTP and OUTN of the first-stage common-mode suppression circuit are respectively connected to the feedback resistors REF1 and REF2 of the second-stage common-mode suppression circuit; the common-mode negative feedback circuit includes transistors M11, M12, M13, M14, M9, R3, and R4; the third-stage hysteresis comparator includes a mismatched transistor M14 in the second-stage positive feedback comparison stage, and the mismatched transistor M14 is used to make the currents passing through transistors M12 and M11 no longer equal in the steady state, thereby causing the transfer characteristic curve of the hysteresis comparator to move toward the positive half-axis direction; by adjusting the amplifier coefficient of the fully differential operational amplifier and the sizes of M9-M14 in the hysteresis comparator, RXD outputs a low level or RXD outputs a high level.

4. The dual common-mode rejection receiving circuit according to claim 2, wherein: The gate terminal of M14, the drain terminal of M14, the gate terminal of M11 and the drain terminal of M11 are connected together, and M12 and the source terminal of M11 are connected together.

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