Sot-mram memory cell and method of manufacturing the same, memory

Abstract

This invention provides a SOT-MRAM memory cell and its manufacturing method, relating to the field of magnetic memory technology. The SOT-MRAM memory cell of this invention includes a stacked bottom gate, a dielectric layer, a semiconductor SOT layer, a magnetic tunnel junction layer, and a T-top electrode. Conductive metals serving as S-bottom and D-bottom electrodes are disposed on both sides of the semiconductor SOT layer. The material of the semiconductor SOT layer is a transition metal chalcogenide. The T-top electrode is used to apply a read voltage. Applying a positive or negative voltage to the bottom gate enables the semiconductor SOT layer to switch between P-type and N-type semiconductors. Applying a voltage between the S-bottom and D-bottom electrodes causes the semiconductor SOT layer to acquire a spin current due to the spin Hall effect, driving the magnetic moments of the free layers in the magnetic tunnel junction layer to flip. This invention reduces the complexity of the control circuit while simplifying the manufacturing process by changing the structure of the SOT-MRAM memory cell.

Description

Technical Field

[0001] This invention relates to the field of magnetic memory technology, specifically to a SOT-MRAM memory cell and its manufacturing method, and a memory. Background Technology

[0002] SOT-MRAM, also known as spin-orbit torque magnetic random access memory, is the latest generation of MRAM. SOT's unique properties combine the performance and reliability requirements of both RAM and NVM applications, achieving both high operating speeds and virtually unlimited read / write endurance, thus expanding the application scope of magnetic storage devices. However, compared to the two-terminal STT-MRAM, SOT-MRAM is a three-terminal device, which has a larger area, more complex control circuitry, and presents challenges in integration.

[0003] like Figure 1 As shown, during the read and write process of SOT-MRAM, each MTJ memory cell requires two transistors for coordinated control. To simplify the SOT-MRAM memory cell control circuit and achieve high-density integration, there are currently three main methods: 1. Through methods such as... Figure 2 The connection method reduces the number of transistor terminals on the MTJ read / write end, but transistors still need to be connected to the top of the device. 2. Front-end CMOS on-chip integration, but this method requires deeper vias at the bottom. In terms of process, ion implantation or etching requires 3D effects to avoid over-etching, short circuits, and poor connections, making the process more complex. 3. Through methods such as... Figure 3 The connection method in this design eliminates the need to connect read transistors from the top of the MTJ, but it requires very high vias at the very end of the device or array, making the fabrication process more complex and affecting the magnetic and electrical performance of the MTJ device. Furthermore, using this connection method requires a wider metal element laterally to increase the aspect ratio of the two vias, ensuring sufficient spacing between the two side-by-side CMOS sensors at the bottom for fabrication and placement. Moreover, this design still requires two transistors to work together to perform the device gating action.

[0004] As can be seen from the above description, the existing methods for simplifying the control circuit of SOT-MRAM memory cells lead to complex manufacturing processes. Summary of the Invention

[0005] (a) Technical problems to be solved

[0006] To address the shortcomings of existing technologies, this invention provides a SOT-MRAM memory cell and its manufacturing method, as well as a memory, which solves the technical problem that existing simplified SOT-MRAM memory cell control circuits lead to complex manufacturing processes.

[0007] (II) Technical Solution

[0008] To achieve the above objectives, the present invention provides the following technical solution:

[0009] In a first aspect, the present invention provides a SOT-MRAM memory cell, comprising a stacked bottom gate, a dielectric layer, a semiconductor SOT layer, a magnetic tunnel junction layer, and a T-top electrode;

[0010] The semiconductor SOT layer has conductive metals on both sides serving as S-bottom electrodes and D-bottom electrodes.

[0011] The material of the semiconductor SOT layer is a transition metal chalcogenide;

[0012] The T-top electrode is used to apply the reading voltage;

[0013] When a positive or negative voltage is applied to the bottom gate, the semiconductor SOT layer achieves the interconversion between P-type and N-type semiconductors. When a voltage is applied between the S-bottom electrode and the D-bottom electrode, the semiconductor SOT layer obtains a spin current due to the spin Hall effect, which drives the magnetic moment of the free layer in the magnetic tunnel junction to reverse.

[0014] Preferably, it also includes a T-top electrode, which is stacked on the magnetic tunnel junction layer for reading voltage when a DC current is applied.

[0015] Preferably, transition metal chalcogenides include tungsten disulfide and graphene.

[0016] Preferably, the magnetic tunneling layer comprises a stacked free layer, a barrier layer, and a reference layer.

[0017] Preferably, during the forward write operation of the SOT-MRAM memory cell, a positive voltage is applied to the bottom gate. Due to the capacitance effect, a negative electric field is generated in the semiconductor SOT layer. When electrons arrive, an electron-forming N-channel is formed. The positive voltage of the bottom gate attracts electrons from the D bottom electrode and the S bottom electrode into the channel. A voltage is applied between the D bottom electrode and the S bottom electrode, and the current flows freely between the D bottom electrode and the S bottom electrode. The bottom gate voltage controls the electrons in the channel, and the current flows from the D bottom electrode to the S bottom electrode. Due to the spin Hall effect, a spin current is generated in the semiconductor SOT layer, driving the free layer to flip forward.

[0018] During the reverse state write operation of the SOT-MRAM memory cell, a negative voltage is applied to the bottom gate. Due to the capacitance effect, a positive electric field is generated in the semiconductor SOT layer. When a hole arrives, a hole-forming P-channel is formed. The negative voltage of the bottom gate attracts electrons from the S-bottom electrode and the D-bottom electrode into the channel. A voltage is applied between the S-bottom electrode and the D-bottom electrode, and the current flows freely between the S and D-bottom electrodes. The bottom gate voltage controls the holes in the channel, and the current flows from the S-bottom electrode to the D-bottom electrode. Due to the spin Hall effect, a spin current is generated in the semiconductor SOT layer, driving the free layer to flip in the reverse direction.

[0019] In a second aspect, the present invention provides a memory comprising a plurality of SOT-MRAM memory cells as described above.

[0020] Thirdly, the present invention provides a method for manufacturing a SOT-MRAM memory cell, comprising:

[0021] Thin film layers are deposited at the bottom, top, and left and right sides of a semiconductor SOT layer made of metal chalcogenide to form thin film layers.

[0022] The bottom S electrode and bottom D electrode are photolithographically etched on the metal thin films on both sides of the semiconductor SOT layer, and the bottom G electrode is photolithographically etched on the metal layer in the bottom double thin film.

[0023] Etch a magnetic tunnel junction and a top electrode on a thin film layer on top of a semiconductor SOT layer;

[0024] Through holes are made on the top electrode, S bottom electrode, D bottom electrode and G electrode, and metallic material is deposited and filled into the through holes.

[0025] Preferably, the transition metal chalcogenide comprises tungsten disulfide and graphene.

[0026] Preferably, the thin film layers on both sides of the semiconductor SOT layer are metal thin films, the bottom thin film layer is a double-layer thin film composed of a heavily doped silicon layer and a metal layer, and the top thin film layer is a multilayer thin film composed of a magnetic material layer, a metal oxide layer, a magnetic material layer, and a metal layer.

[0027] Preferably, the manufacturing method further includes:

[0028] After photolithography and etching, a protective layer is deposited.

[0029] (III) Beneficial Effects

[0030] This invention provides a SOT-MRAM memory cell, its manufacturing method, and a memory. Compared with the prior art, it has the following advantages:

[0031] This invention discloses a SOT-MRAM memory cell, comprising a stacked bottom gate, a dielectric layer, a semiconductor SOT layer, a magnetic tunnel junction layer, and a T-top electrode. Conductive metals serving as S-bottom and D-bottom electrodes are disposed on both sides of the semiconductor SOT layer. The semiconductor SOT layer is made of a transition metal chalcogenide. The T-top electrode is used to apply a read voltage. Applying a positive or negative voltage to the bottom gate enables the semiconductor SOT layer to switch between P-type and N-type semiconductors. Applying a voltage between the S-bottom and D-bottom electrodes causes the semiconductor SOT layer to acquire a spin current due to the spin Hall effect, driving the magnetic moments of the free layers in the magnetic tunnel junction layer to flip. This invention reduces the complexity of the control circuit while simplifying the manufacturing process by modifying the structure of the SOT-MRAM memory cell. Attached Figure Description

[0032] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0033] Figures 1-3 Schematic diagrams of SOT-CMOS read / write circuit structures under different designs;

[0034] Figure 4 This is a schematic diagram of the structure of a SOT-MRAM memory cell according to an embodiment of the present invention;

[0035] Figure 5 This is a flowchart illustrating the forward write operation of a SOT-MRAM memory cell according to an embodiment of the present invention.

[0036] Figure 6 This is a flowchart illustrating the reverse write operation of a SOT-MRAM memory cell according to an embodiment of the present invention.

[0037] Figure 7 When writing in the forward direction, the device write operation process can be understood using a partial diagram of the unit device, where + represents a hole and - represents an electron;

[0038] Figure 8 This is a flowchart illustrating the read operation process of a SOT-MRAM memory cell according to an embodiment of the present invention.

[0039] Figure 9 The present invention also provides a flowchart of a method for manufacturing a SOT-MRAM memory cell. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention are described clearly and completely. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0041] This application provides a SOT-MRAM memory cell and its manufacturing method, as well as a memory, which solves the technical problem that existing methods for simplifying the control circuit of SOT-MRAM memory cells lead to complex processes, thereby reducing the complexity of the control circuit while simplifying the process.

[0042] The technical solution in this application is to solve the above-mentioned technical problems, and the general idea is as follows:

[0043] SOT-MRAM, with its superior performance such as fast write speed and high stability, shows great promise in the field of magnetic storage devices. However, ordinary SOT-MRAM three-terminal memory devices have a large area and complex control circuits, resulting in difficulties and complexity in integration. To solve the above-mentioned problems of ordinary SOT-MRAM three-terminal memory devices, existing methods generally sacrifice process simplification and use complex processes to achieve the above objectives. This invention, by changing the structure of the SOT-MRAM memory cell, reduces the complexity of the control circuit while simplifying the process.

[0044] To better understand the above technical solutions, the following will provide a detailed explanation of the technical solutions in conjunction with the accompanying drawings and specific implementation methods.

[0045] This invention provides a SOT-MRAM memory cell, comprising a stacked bottom gate, a dielectric layer, a semiconductor SOT layer, a magnetic tunnel junction layer, and a T-top electrode;

[0046] The semiconductor SOT layer has conductive metals on both sides serving as S-bottom electrodes and D-bottom electrodes.

[0047] The material of the semiconductor SOT layer is a transition metal chalcogenide;

[0048] The T-top electrode is used to apply the reading voltage;

[0049] When a positive or negative voltage is applied to the bottom gate, the semiconductor SOT layer achieves the interconversion between P-type and N-type semiconductors. When a voltage is applied between the S-bottom electrode and the D-bottom electrode, the semiconductor SOT layer obtains a spin current due to the spin Hall effect, which drives the magnetic moment of the free layer in the magnetic tunnel junction to reverse.

[0050] This invention reduces the complexity of the control circuit by changing the structure of the SOT-MRAM memory cell, while simplifying the manufacturing process.

[0051] The following is a detailed description of each level in the SOT-MRAM memory cell:

[0052] The bottom gate (G) is made of heavily doped silicon.

[0053] The dielectric layer is used to maintain the insulation between the heavily doped silicon layer and the semiconductor SOT layer, and it is generally made of silicon oxide.

[0054] The material of the semiconductor SOT layer is a transition metal chalcogenide, such as tungsten disulfide and graphene.

[0055] The magnetic tunneling layer consists of a free layer, a barrier layer, and a reference layer.

[0056] The T-top electrode, S-bottom electrode, and D-bottom electrode are all conductive metals, such as gold, silver, and copper.

[0057] The SOT-MRAM memory cell writing methods in this embodiment of the invention include forward writing and reverse writing.

[0058] Among them, the forward write operation is as follows Figure 5 As shown, when a positive voltage is applied to the bottom gate (G), the gate is essentially subjected to a positive electric field. Due to the capacitance effect (such as...), Figure 7 As shown, a negative electric field is generated in the semiconductor SOT layer, forming an electron-forming N-channel when electrons arrive. The positive voltage at the gate (G) attracts electrons from the bottom electrodes (D and S) into the channel. If a voltage is applied between the D and S bottom electrodes, current will flow freely between them. The gate voltage then controls the electrons in the channel, causing current to flow from the D bottom electrode to the S bottom electrode. The spin Hall effect in the semiconductor SOT layer generates a spin current that drives the adjacent free layer to flip in the positive direction.

[0059] Reverse write operation as follows Figure 6 As shown, when a negative voltage is applied to the bottom gate (G), the gate is essentially subjected to a negative electric field. Due to the capacitance effect (and...), Figure 7 (The + and - signs are reversed, as shown). A positive electric field is generated in the semiconductor SOT layer, forming a hole-forming P-channel when holes arrive. The negative voltage at the gate (G) attracts electrons from the bottom electrodes (S and D) into the channel. If a voltage is applied between the S and D bottom electrodes, current will flow freely between them. At this time, the gate voltage will control the holes in the channel, and the current will flow from the bottom electrode (S) to the bottom electrode (D). The spin Hall effect in the semiconductor SOT layer generates a spin current that drives the adjacent free layers to flip in the opposite direction.

[0060] Its read operation is as follows Figure 8As shown, a positive voltage is applied to the G terminal, and a DC read voltage is applied through the T top electrode. Current enters from the T top electrode and flows out from the D bottom electrode. By measuring the magnitude of the current flowing out of the D bottom electrode, the magnetic tunnel junction resistance is obtained, which reflects the magnetization state of the SOT-MRAM memory cell.

[0061] In this embodiment of the invention, the main principle is as follows: Spin stacking generated in the van der Waals heterojunction composed of graphene and tungsten disulfide, when a write voltage is applied across the S / D bottom electrode, allows pure current to be transmitted through the graphene (induced Lashpa and spin-orbit coupling SOC in graphene leads to spin accumulation and spin current without the use of ferromagnetic electrodes), creating a spin current. Simultaneously, a relatively stable semiconductor heterojunction is formed between tungsten disulfide and graphene, enabling gate control of the lower-level transistor.

[0062] like Figure 9 As shown, this embodiment of the invention also provides a method for manufacturing a SOT-MRAM memory cell, comprising:

[0063] Thin film layers are deposited at the bottom, top, and left and right sides of a semiconductor SOT layer made of metal chalcogenide. Among them, metal thin films are formed on both sides of the semiconductor SOT layer, and a double-layer thin film consisting of a heavily doped silicon layer and a metal layer is formed sequentially at the bottom. A multilayer thin film consisting of a magnetic material layer, a metal oxide layer, a magnetic material layer, and a metal layer is formed sequentially at the top.

[0064] The bottom S electrode and bottom D electrode are photolithographically patterned on the metal thin films on both sides of the semiconductor SOT layer, and the bottom G electrode is photolithographically patterned on the metal layer in the bottom double thin film, and then a protective layer is deposited.

[0065] The magnetic tunnel junction and top electrode are etched on top of the semiconductor SOT layer, and then a protective layer is deposited.

[0066] Through holes are made on the top electrode, S bottom electrode, D bottom electrode and G electrode, and metallic material is deposited and filled into the through holes.

[0067] It is understood that the method for preparing the SOT-MRAM memory cell provided in the embodiments of the present invention corresponds to the SOT-MRAM memory cell in the above embodiments. The explanation, examples, specific materials, hierarchical structure and other related contents can be referred to the corresponding contents in the SOT-MRAM memory cell, and will not be repeated here.

[0068] This invention also provides a memory comprising a plurality of SOT-MRAM memory cells as described above.

[0069] In summary, compared with existing technologies, it has the following beneficial effects:

[0070] 1. The embodiments of the present invention reduce the complexity of the control circuit by changing the structure of the SOT-MRAM memory cell, while simplifying the manufacturing process.

[0071] 2. The SOT-MRAM memory cell in this embodiment of the invention uses only a single transistor, which reduces the area of ​​the entire memory cell.

[0072] 3. In the manufacturing process of the SOT-MRAM memory cell of this embodiment, the electrodes that need to be made into through holes are not connected to the magnetic tunnel junction layer, thus ensuring the magnetic and electrical performance of the MTJ device.

[0073] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0074] The above embodiments are only used to illustrate the technical solutions of the present invention, and are not intended to limit it. Although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some of the technical features. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A SOT-MRAM memory cell, characterized in that, It includes a stacked bottom gate, dielectric layer, semiconductor SOT layer, magnetic tunnel junction layer, and T-top electrode; The semiconductor SOT layer has conductive metals on both sides serving as S-bottom electrodes and D-bottom electrodes. The material of the semiconductor SOT layer is a transition metal chalcogenide; The T-top electrode is used to apply the reading voltage; When a positive or negative voltage is applied to the bottom gate, the semiconductor SOT layer achieves the interconversion between P-type and N-type semiconductors. When a voltage is applied between the S-bottom electrode and the D-bottom electrode, the semiconductor SOT layer obtains a spin current due to the spin Hall effect, which drives the magnetic moment of the free layer in the magnetic tunnel junction layer to reverse. During the forward write operation of the SOT-MRAM memory cell, a positive voltage is applied to the bottom gate. Due to the capacitance effect, a negative electric field is generated in the semiconductor SOT layer. When electrons arrive, an electron-forming N-channel is formed. During the reverse state write operation of the SOT-MRAM memory cell, a negative voltage is applied to the bottom gate. Due to the capacitance effect, a positive electric field is generated in the semiconductor SOT layer. When a hole arrives, a hole P-channel is formed.

2. The SOT-MRAM memory cell as described in claim 1, characterized in that, The materials used in the semiconductor SOT layer include tungsten disulfide and graphene.

3. The SOT-MRAM memory cell as described in claim 1, characterized in that, The magnetic tunneling layer comprises a stacked free layer, a barrier layer, and a reference layer.

4. The SOT-MRAM memory cell as described in any one of claims 1-3, characterized in that, A positive gate voltage attracts electrons from the D and S bottom electrodes into the channel; when a voltage is applied between the D and S bottom electrodes, current flows freely between them; the gate voltage controls the electrons in the channel, and current flows from the D bottom electrode to the S bottom electrode. Due to the spin Hall effect, a spin current is generated in the semiconductor SOT layer, driving the free layer to flip in the forward direction. The negative gate voltage attracts electrons from the S and D bottom electrodes into the channel; when a voltage is applied between the S and D bottom electrodes, current flows freely between the S and D bottom electrodes; the gate voltage controls the holes in the channel, and current flows from the S bottom electrode to the D bottom electrode. Due to the spin Hall effect, a spin current is generated in the semiconductor SOT layer, driving the free layer to flip in the opposite direction.

5. The SOT-MRAM memory cell as described in any one of claims 1-3, characterized in that, During the read operation of the SOT-MRAM memory cell, a positive voltage is applied to the bottom gate, and a DC read voltage is applied through the top electrode T. Current enters from the top electrode T and flows out from the bottom electrode D. The magnetic tunnel junction resistance is obtained by measuring the magnitude of the current flowing out of the bottom electrode D, which reflects the magnetization state of the SOT-MRAM memory cell.

6. A memory, characterized in that, It includes multiple SOT-MRAM memory cells as described in any one of claims 1 to 5.

7. A method for manufacturing a SOT-MRAM memory cell according to any one of claims 1-5, characterized in that, include: Thin film layers are deposited at the bottom, top, and left and right sides of a semiconductor SOT layer made of transition metal chalcogenides to form thin film layers. The S-bottom electrode and D-bottom electrode are photolithographically patterned on the metal thin films on both sides of the semiconductor SOT layer, and the bottom gate is formed in the metal layer of the bottom double thin film. A magnetic tunnel junction and a T-top electrode are etched on a thin film layer on top of the semiconductor SOT layer.

8. The method for manufacturing a SOT-MRAM memory cell as described in claim 7, characterized in that, The materials of the semiconductor SOT layer include tungsten disulfide and graphene.

9. The method for manufacturing a SOT-MRAM memory cell as described in claim 7, characterized in that, The thin film layers on both sides of the semiconductor SOT layer are metal thin films. The bottom thin film layer is a double-layer thin film composed of a heavily doped silicon layer and a metal layer. The top thin film layer is a multilayer thin film composed of a magnetic material layer, a metal oxide layer, a magnetic material layer, and a metal layer.

Images