Systems and methods for offset calibration in successive approximation analog-to-digital converters

Abstract

The disclosure herein relates to systems and methods for offset calibration in a successive approximation analog-to-digital converter (SAR ADC). In one aspect, the SAR ADC includes a calibration circuit configured to receive some or all of a plurality of bits corresponding to an input voltage, and to accumulate or average at least some of the bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with a first comparator, to provide a second offset signal to control a second offset associated with a second comparator, or to reduce an offset difference associated with the first offset and the second offset.

Description

Technical Field

[0001] This disclosure generally relates to a communication system, including but not limited to a successive approximation analog-to-digital converter (SAR ADC). Background Technology

[0002] Recent advancements in communication and computing devices demand high data rates. For example, network switches, routers, hubs, or any communication device can exchange data at high speeds (e.g., 1 Mbps to 100 Gbps) to stream data in real time or process large volumes of data seamlessly. To efficiently process data in the digital domain, the amplitude or voltage of a signal can represent multiple bits, and the signal can be exchanged between two or more communication devices via cable or wireless media. For example, a 1.2V signal can be represented as [00010110], and a 1.3V signal can be represented as [00011001]. To convert the voltage of an input signal into corresponding bits, some communication devices implement SAR ADCs. For example, a SAR ADC can determine multiple bits corresponding to an input signal through successive approximations. Dynamic and static offset errors in the comparator of a SAR ADC can affect the accuracy and / or precision of the conversion. ADC offset error can be defined as the deviation between the actual transfer function and the ideal transfer function. Summary of the Invention

[0003] In one aspect, this disclosure relates to an apparatus comprising: a sampling and digital-to-analog converter (DAC) circuit for sampling an input voltage to obtain a first sampled voltage; a first comparator coupled to the sampling and DAC circuit; a first set of storage circuitry coupled to the first comparator and the sampling and DAC circuitry, the first set of storage circuitry configured to store a first subset of a plurality of bits corresponding to the input voltage; a second comparator coupled to the sampling and DAC circuitry; a second set of storage circuitry coupled to the second comparator and the sampling and DAC circuitry, the second set of storage circuitry configured to store a second subset of the plurality of bits corresponding to the input voltage; and a calibration circuitry configured to receive a first bit from a first storage cell of the first set of storage circuitry and to receive a plurality of bits from the first set of storage circuitry and the second set of storage circuitry, wherein the calibration circuitry is configured to provide a first offset signal to control a first offset associated with the first comparator and to provide a second offset signal to control a second offset associated with the second comparator.

[0004] On the other hand, this disclosure relates to an apparatus comprising: a sampling and digital-to-analog converter (DAC) circuit for sampling an input voltage to obtain a first sampled voltage; a first comparator coupled to the sampling and DAC circuit; a first set of storage circuitry coupled to the first comparator and the sampling and DAC circuitry, the first set of storage circuitry configured to store a first subset of a plurality of bits corresponding to the input voltage; a second comparator coupled to the sampling and DAC circuitry; a second set of storage circuitry coupled to the second comparator and the sampling and DAC circuitry, the second set of storage circuitry configured to store a second subset of the plurality of bits corresponding to the input voltage; and a calibration circuitry configured to receive the second subset of the plurality of bits corresponding to the input voltage and to accumulate or average the second subset of the plurality of bits corresponding to the input voltage, wherein the calibration circuitry is configured to provide a first offset signal to control a first offset associated with the first comparator or to provide a second offset signal to control a second offset associated with the second comparator, wherein the calibration circuitry is configured to update the first offset signal or the second offset signal when the average value of the second subset of the plurality of bits is higher than a threshold.

[0005] In another aspect, this disclosure relates to a method comprising: sampling an input voltage by a sampling and digital-to-analog converter (DAC) circuit to obtain a first sampled voltage; determining, based on the first sampled voltage, a state of a first bit among a plurality of bits corresponding to the input voltage by a first comparator coupled to a first set of memory circuits; sampling the input voltage by the sampling and DAC circuit to obtain a second sampled voltage; determining, based on the second sampled voltage, a state of a second bit among the plurality of bits by a second comparator coupled to a second set of memory circuits other than the first set of memory circuits; averaging a first number of the plurality of bits from the first set of memory circuits and a second number of bits from the first set of memory circuits and the second set of memory circuits; and providing a first offset signal in response to the average value of the first number of the bits to control a first offset associated with the first comparator and providing a second offset signal in response to the second number of the bits to control a second offset associated with the second comparator to reduce the offset difference. Attached Figure Description

[0006] The various objects, aspects, features, and advantages of this disclosure will become more apparent and better understood by referring to the detailed description taken in conjunction with the accompanying drawings, in which the same reference numerals consistently identify corresponding elements. In the drawings, the same reference numerals generally indicate identical, functionally similar, and / or structurally similar elements.

[0007] Figure 1AIt is a block diagram depicting a network environment comprising one or more access points communicating with one or more devices or stations, according to one or more embodiments.

[0008] Figure 1B and 1C It is a block diagram depicting a computing device used in conjunction with the methods and systems described herein, according to one or more embodiments.

[0009] Figure 2 It is a block diagram depicting a communication device according to one or more embodiments.

[0010] Figure 3 This is a schematic diagram of a SAR ADC according to one or more embodiments.

[0011] Figure 4 According to one or more embodiments Figure 3 The timing diagram of the SAR ADC operation is shown.

[0012] Figure 5 According to one or more embodiments Figure 3 The diagram shows a block diagram of the calibration engine for the SAR ADC.

[0013] Figure 6 According to one or more embodiments Figure 5 The diagram shows a portion of the calibration engine.

[0014] Figure 7 According to one or more embodiments Figure 5 The diagram shows a portion of the calibration engine.

[0015] Figure 8 According to one or more embodiments Figure 5 The diagram shows a portion of the calibration engine.

[0016] Details of various embodiments of the method and system are set forth in the accompanying drawings and the following description. Detailed Implementation

[0017] The following description of the various embodiments, along with their respective sections, may be helpful in reading the description of the various embodiments below:

[0018] Section A describes the network and computing environments that can be used to practice the embodiments described herein; and

[0019] Section B describes embodiments of systems and methods for implementing a SAR ADC (e.g., a power-efficient SAR ADC) according to one or more embodiments.

[0020] The various embodiments disclosed herein relate to apparatuses for data communication. In some embodiments, the apparatus includes or is used in physical layer products with a SAR ADC. In some embodiments, the SAR ADC is high-speed (e.g., operating at frequencies above 5 Mbps, resolutions from 8 to 18 bits, or above 500 MHz (e.g., above 1 GHz)). In some embodiments, the SAR ADC is used in data communication and processing systems, including but not limited to network switches, serializer / deserializer (SERDES) physical layer devices (PHYs), optical receivers, wireless receivers (including 5G cellular receivers), data acquisition systems, sensors, etc. The SAR ADC uses offset calibration for two or more comparators, where compensation is provided for static and dynamic DC offset errors that reduce the performance of the SAR ADC, particularly in time-interleaved ADCs according to some embodiments. Advantageously, the systems and methods described herein can provide large SAR ADC arrays with SAR ADCs that have reduced latency, reduced area, reduced mismatch, increased resolution, and increased bandwidth.

[0021] The various embodiments disclosed herein relate to apparatus for data communication. In some embodiments, the apparatus includes sampling and digital-to-analog converter (DAC) circuitry for sampling an input voltage to obtain a first sampled voltage. In some embodiments, the apparatus includes a first comparator coupled to the sampling and DAC circuitry. In some embodiments, the apparatus includes a first set of storage circuitry coupled to the first comparator and the sampling and DAC circuitry. In some embodiments, the first set of storage circuitry is configured to store the state of a first subset of a plurality of bits corresponding to the input voltage. In some embodiments, the apparatus includes a second comparator coupled to the sampling and DAC circuitry. In some embodiments, the apparatus includes a second set of storage circuitry coupled to the second comparator and the sampling and DAC circuitry. In some embodiments, the second set of storage circuitry is configured to store the state of a second subset of a plurality of bits corresponding to the input voltage. In some embodiments, the apparatus includes control circuitry coupled to the first comparator and the second comparator. The control circuitry may be configured to select the first comparator to determine the state of the target bit during a first time period corresponding to a target bit of the plurality of bits of the input voltage. The first comparator may determine the state of the target bit based on the first sampled voltage.

[0022] The system and method employ a DC offset calibration approach to reduce the offsets of the first and second comparators and minimize residual offsets. In some embodiments, a smaller residual offset improves the effective number of bits (ENOB) of the SAR ADC and the SAR ADC overrange protection margin. In some embodiments, the system and method provide greater design freedom for optimizing the performance, power, and speed of the first and second comparators. In some embodiments, the DC offset calibration method provides a universal solution for different non-binary SAR DAC weighting schemes (e.g., any type of non-binary SAR DAC weighting scheme). In some embodiments, the system and method provide a receiver based on a time-interleaved SAR ADC, which can be manufactured with higher yields and is more robust, exhibiting more consistent ENOB performance across process, voltage, and temperature (PVT) angles.

[0023] The various embodiments disclosed herein relate to an apparatus. The apparatus includes a sampling and digital-to-analog converter (DAC) circuit for sampling an input voltage to obtain a first sampled voltage, a first comparator coupled to the sampling and DAC circuit, a first set of storage circuits, a second set of storage circuits, a second comparator, and a calibration circuit. The first set of storage circuits is coupled to the first comparator and the sampling and DAC circuit. The first set of storage circuits is configured to store a first subset of bits corresponding to the input voltage. The second comparator is coupled to the sampling and DAC circuit. The second set of storage circuits is coupled to the second comparator and the sampling and DAC circuit and is configured to store a second subset of bits corresponding to the input voltage. The calibration circuit is configured to receive a first bit from a first storage cell of the first set of storage circuits and to receive a plurality of bits from the first and second sets of storage circuits. The calibration circuit is configured to provide a first offset signal to control a first offset associated with the first comparator and to provide a second offset signal to control a second offset associated with the second comparator.

[0024] In some embodiments, the first comparator has a faster detection speed than the second comparator, and the second comparator has higher sensitivity than the first comparator. In some embodiments, the first bit is the most significant bit. In some embodiments, several bits include all bits of the first group of memory circuits and the second group of memory circuits.

[0025] In some embodiments, the calibration circuit includes a first averaging circuit configured to receive a first bit and a second averaging circuit configured to receive several bits. In some embodiments, a first offset code calculation circuit is coupled to the first averaging circuit, and a second offset code calculation circuit is coupled to the second averaging circuit. In some embodiments, the first averaging circuit is an accumulator. The accumulator may be a digital logic device including registers for storing arithmetic results such as addition, averaging, etc.

[0026] In some embodiments, the device is housed within an integrated circuit package. In some embodiments, the output of the first comparator is directly coupled to the input port of a first set of memory circuits, and the output of the second comparator is directly coupled to the input port of a second set of memory circuits.

[0027] The various embodiments disclosed herein relate to an apparatus. The apparatus includes a sampling and digital-to-analog converter (DAC) circuit for sampling an input voltage to obtain a first sampled voltage, a first comparator coupled to the sampling and DAC circuit, a first set of storage circuitry coupled to the first comparator and the sampling and DAC circuit, a second comparator coupled to the sampling and DAC circuit, a second set of storage circuitry coupled to the second comparator and the sampling and DAC circuit, and a calibration circuit. The first set of storage circuitry is configured to store a first subset of bits corresponding to the input voltage, and the second set of storage circuitry is configured to store a second subset of bits corresponding to the input voltage. The calibration circuit is configured to receive the second subset of bits corresponding to the input voltage and to accumulate or average the second subset of bits corresponding to the input voltage. The calibration circuit is configured to provide a first offset signal to control a first offset associated with the first comparator or to provide a second offset signal to control a second offset associated with the second comparator. When the average value of the second subset of bits is higher than a threshold, the calibration circuit updates the first offset signal or the second offset signal.

[0028] In some embodiments, the first comparator has a faster detection speed than the second comparator, and the second comparator has higher sensitivity than the first comparator.

[0029] In some embodiments, the calibration circuitry includes a third comparator that receives an average value and a threshold. In some embodiments, a second subset of bits includes all bits of a second set of storage circuitry. In some embodiments, the calibration circuitry includes an adder. In some embodiments, the device is housed in an integrated circuit package.

[0030] The various embodiments disclosed herein relate to a method. The method includes sampling an input voltage by a sampling and digital-to-analog converter (DAC) circuit to obtain a first sampled voltage, and determining, based on the first sampled voltage, the state of a first bit among a plurality of bits corresponding to the input voltage by a first comparator coupled to a first set of memory circuitry. The method further includes sampling the input voltage by the sampling and DAC circuitry to obtain a second sampled voltage, and determining, based on the second sampled voltage, the state of a second bit among a plurality of bits by a second comparator coupled to a second set of memory circuitry different from the first set of memory circuitry. The method further includes averaging a first plurality of bits from the first set of memory circuitry and a second plurality of bits from both the first and second sets of memory circuitry. The method further includes providing a first offset signal in response to the average of the first plurality of bits to control a first offset associated with a first comparator, and providing a second offset signal in response to the second plurality of bits to control a second offset associated with a second comparator.

[0031] In some embodiments, the first number of bits are the most significant bits. In some embodiments, the second number of bits includes all bits of the first group of storage circuits and the second group of storage circuits. In some embodiments, the method further includes storing a determined state of the first bit in a corresponding element of the first group of storage circuits, and storing a determined state of the second bit in a corresponding element of the second group of storage circuits. In some embodiments, the operation of sampling the input voltage by the sampling and DAC circuits to obtain the second sampled voltage is at least partially based on the determined state of the first bit stored in a corresponding element of the first group of storage circuits.

[0032] A. Computing and Network Environment

[0033] Before discussing specific embodiments of this solution, it may be helpful to describe aspects of the operating environment and associated system components (e.g., hardware elements) in conjunction with the methods and systems described herein. References Figure 1A This describes an embodiment of a network environment. In short, the network environment includes a wireless communication system comprising one or more network devices or access points (APs) 106, one or more wireless communication devices 102, and node or network hardware components 192. The wireless communication device 102 may, for example, include a computer 102 (e.g., a desktop computer, laptop computer, notebook computer, or tablet computer), a personal computer 102, and / or a cellular phone device 102. Details of embodiments of each wireless communication device 102 and / or network device 106 are available for reference. Figure 1B and 1CMore detailed description. In one embodiment, the network environment may be an ad hoc network environment, an infrastructure wireless network environment, a subnet environment, etc. Network device 106 may be operatively coupled to network hardware or node 192 via a local area network (LAN) connection. Network hardware or node 192, which may include routers, gateways, switches, bridges, modems, system controllers, facilities, etc., may provide LAN connectivity for the communication system. Each of network devices 106 may have an associated antenna or antenna array to communicate with wireless communication devices in its area. Wireless communication device 102 may register with a specific AP or network device 106 to receive services from the communication system (e.g., via SU-MIMO or MU-MIMO configuration). For direct connections (e.g., point-to-point communication), some wireless communication devices may communicate directly via an allocation channel and communication protocol. Some wireless communication devices 102 may be mobile or relatively stationary relative to the AP or network device 106.

[0034] In some embodiments, the AP or network device 106 includes means or modules (comprising a combination of hardware and software) that allow the wireless communication device 102 to connect to a wired network using Wi-Fi or other standards. The network device 106 may sometimes be referred to as a Wireless Access Point (WAP). The network device 106 may be implemented (e.g., configured, designed, and / or built) for operation in a Wireless Local Area Network (WLAN). In some embodiments, the AP or network device 106 may be connected as a standalone device to a router (e.g., via a wired network). In other embodiments, the AP or network device 106 may be a component of a router. The AP or network device 106 may provide network access to multiple devices. The AP or network device 106 may, for example, connect to a wired Ethernet connection and use a radio frequency link to provide wireless connectivity to other devices 102 to utilize the wired connection. The AP or network device 106 may be implemented to support standards for transmitting and receiving data using one or more radio frequencies. These standards and the frequencies used may be defined by IEEE (e.g., the IEEE 802.11 standard). Ap or network device 106 may be configured and / or used to support public Internet hotspots and / or extend the Wi-Fi signal range of a network over a network.

[0035] In some embodiments, access point 106 may be used (e.g., in a home or building) for a wireless network (e.g., IEEE 802.11, Bluetooth, ZigBee, any other type of radio frequency-based network protocol and / or variations thereof). Each of the wireless communication devices 102 may include a built-in radio and / or be coupled to a radio. Such wireless communication devices 102 and / or access points 106 may operate according to various aspects of this disclosure as presented herein to enhance performance, reduce cost and / or size, and / or enhance broadband applications. Each wireless communication device 102 may have the capability to act as a client node seeking access to resources (e.g., data and connections to networked nodes such as servers) via one or more access points 106.

[0036] The network connection may include any type and / or form of network and may include any of the following: point-to-point network, broadcast network, telecommunications network, data communication network, computer network. The network topology may be a bus, star, or ring network topology. The network may be any such network topology known to those of ordinary skill in the art capable of supporting the operations described herein. In some embodiments, different types of data may be transmitted via different protocols. In other embodiments, the same type of data may be transmitted via different protocols.

[0037] The communication device 102 and access point 106 can be deployed as and / or executed on any type and form of computing device, such as a computer, network device or facility capable of communicating and performing the operations described herein on any type and form of network. Figure 1B and 1C A block diagram depicting a computing device 100 that can be used to implement embodiments of wireless communication device 102 or network device 106. (See diagram for reference.) Figure 1B and 1C As shown, each computing device 100 includes a main processor 121 and a main memory unit 122. For example... Figure 1B As shown, computing device 100 may include storage device 128, mounting device 116, network interface 118, I / O controller 123, display devices 124a to 124n, keyboard 126, and pointing device 127 such as a mouse. Storage device 128 may include operating system and / or software. Figure 1C As shown, each computing device 100 may also include additional optional components, such as memory port 103, bridge 170, one or more input / output devices 130a to 130n, and cache memory 140 communicating with the main processor 121.

[0038] The main processor 121 is any logic circuit system that responds to and processes instructions fetched from the main memory unit 122. In many embodiments, the central processing unit or main processor 121 is provided by a microprocessor unit, such as those manufactured by Intel Corporation of Santa Clara, California; those manufactured by International Business Machines Corporation of White Plains, New York; or those manufactured by Advanced Micro Devices, Inc. of Sunnyvale, California. The computing device 100 may be based on any of these processors, or any other processor capable of operating as described herein.

[0039] Main memory unit 122 may be one or more memory chips capable of storing data and allowing direct access to any storage location by microprocessor 121, such as any type or variant of static random access memory (SRAM), dynamic random access memory (DRAM), ferroelectric RAM (FRAM), NAND flash memory, NOR flash memory, and solid-state drive (SSD). Main memory 122 may be based on any of the above-described memory chips, or any other available memory chips capable of operating as described herein. Figure 1B In the embodiment shown, the processor 121 communicates with the main memory 122 via the system bus 150 (described in more detail below). Figure 1C An embodiment of computing device 100 is depicted, wherein the processor communicates directly with main memory 122 via memory port 103. For example, in Figure 1C In this context, the main memory 122 can be DRDRAM.

[0040] Figure 1C An embodiment is depicted in which the main processor 121 communicates directly with the cache memory 140 via a secondary bus (sometimes called a back-end bus). In other embodiments, the main processor 121 communicates with the cache memory 140 using a system bus 150. The cache memory 140 typically has a faster response time than the main memory 122 and is provided by, for example, SRAM, BSRAM, or EDRAM. Figure 1C In the embodiment shown, processor 121 communicates with various I / O devices 130 via a local system bus 150. Various buses can be used to connect the main processor 121 to any of the I / O devices 130, such as the VESAVL bus, ISA bus, EISA bus, Micro Channel Architecture (MCA) bus, PCI bus, PCI-X bus, PCI-Express bus, or NuBus. In an embodiment where the I / O device is a video display 124, processor 121 may use an Advanced Graphics Port (AGP) to communicate with the display 124. Figure 1CAn embodiment of computer 100 is depicted, wherein the main processor 121 can communicate directly with I / O device 130b, for example via HYPERTRANSPORT, RAPIDIO, or INFINIBAND communication technologies. Figure 1C An embodiment in which a combination of local bus and direct communication is also depicted: the processor 121 communicates with I / O device 130a using a local interconnect bus, while simultaneously communicating directly with I / O device 130b.

[0041] Various I / O devices 130a to 130n may exist in the computing device 100. Input devices include a keyboard, mouse, trackpad, trackball, microphone, dial pad, touchpad, touch screen, and drawing tablet. Output devices include a video display, speakers, inkjet printer, laser printer, projector, and dye-to-sublimation printer. The I / O devices can be controlled by the I / O controller 123, such as... Figure 1B The I / O controller can control one or more I / O devices, such as a keyboard 126 and a pointing device 127, such as a mouse or light pen. Additionally, the I / O devices can provide storage and / or mounting media 116 for the computing device 100. In other embodiments, the computing device 100 can provide a USB connection (not shown) to receive a handheld USB storage device, such as the USB flash drive series manufactured by Twintech Industry, Inc. in Los Aramis, California.

[0042] Refer again Figure 1B The computing device 100 may support any suitable installation device 116, such as a disk drive, CD-ROM drive, CD-R / RW drive, DVD-ROM drive, flash memory drive, tape drive of various formats, USB device, hard disk drive, network interface, or any other device suitable for installing software and programs. The computing device 100 may further include a storage device, such as one or more hard disk drives or a redundant array of independent disks, for storing the operating system and other related software, and for storing application software programs, such as any program or software 120 used to implement (e.g., configured and / or designed for) the systems and methods described herein. Optionally, any of the installation devices 116 may also be used as a storage device. Additionally, the operating system and software may be run from a bootable media.

[0043] Furthermore, the computing device 100 may include a network interface 118 to interface with the network 104 via various connections, including but not limited to standard telephone lines, LAN or WAN links (e.g., 802.11, T1, T3, 56kb, X.25, SNA, DECNET), broadband connections (e.g., ISDN, Frame Relay, ATM, Gigabit Ethernet, Ethernet over SONET), wireless connections, or combinations of any or all of the above connections. Connections can be established using various communication protocols (e.g., TCP / IP, IPX, SPX, NetBIOS, Ethernet, ARCNET, SONET, SDH, Fiber Distributed Data Interface (FDDI), RS232, IEEE 802.11, IEEE 802.11a, IEEE 802.11b, IEEE 802.11g, IEEE 802.11n, IEEE 802.11ac, IEEE 802.11ad, CDMA, GSM, WiMax, and direct asynchronous connections). In one embodiment, computing device 100 communicates with other computing devices 100' via any type and / or form of gateway or tunneling protocol (e.g., Secure Sockets Layer (SSL) or Transport Layer Security (TLS)). Network interface 118 may include a built-in network adapter, network interface card, PCMCIA network card, card bus network adapter, wireless network adapter, USB network adapter, modem, or any other means suitable for interfacing computing device 100 with any type of network capable of communicating and performing the operations described herein.

[0044] In some embodiments, computing device 100 may include or be connected to one or more display devices 124a to 124n. Therefore, any of the I / O devices 130a to 130n and / or the I / O controller 123 may include any type and / or form of suitable hardware, software, or a combination of hardware and software to support, enable, or provide connectivity and use of the display devices 124a to 124n by computing device 100. For example, computing device 100 may include any type and / or form of video adapter, video card, driver, and / or library to interface with, communicate with, connect to, or otherwise use the display devices 124a to 124n. In one embodiment, a video adapter may include multiple connectors to interface with the display devices 124a to 124n. In other embodiments, computing device 100 may include multiple video adapters, each connected to the display devices 124a to 124n. In some embodiments, any portion of the operating system of computing device 100 may be configured to use multiple displays 124a to 124n. In a further embodiment, I / O device 130 may serve as a bridge between system bus 150 and an external communication bus, such as a USB bus, Apple Desktop bus, RS-232 serial connection, SCSI bus, FireWire bus, FireWire800 bus, Ethernet bus, AppleTalk bus, Gigabit Ethernet bus, Asynchronous Transfer Mode bus, Fibre Channel bus, Serial Attached Small Computer System Interface bus, USB connection, or HDMI bus.

[0045] Figure 1B and 1CThe computing device 100 of the type described herein can operate under the control of an operating system that controls task scheduling and access to system resources. The computing device 100 can run any operating system, such as versions of Microsoft Windows, different versions of Unix and Linux operating systems, any version of MAC OS for Macintosh computers, any embedded operating system, any real-time operating system, any open-source operating system, any proprietary operating system, any operating system for mobile computing devices, or any other operating system capable of running on a computing device and performing the operations described herein. Typical operating systems include, but are not limited to: Android produced by Google; Windows 7, 8, and 10 produced by Microsoft Corporation of Redmond, Washington; MAC OS produced by Apple Computer Inc. of Cupertino, California; WebOS produced by Research In Motion (RIM); OS / 2 produced by International Business Machines Corporation of Armonk, New York; and Linux, a free and available operating system distributed by Caldera Inc. of Salt Lake City, Utah, or any type and / or form of Unix operating system.

[0046] Computer system 100 may be any workstation, telephone, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone or other portable telecommunications device, media playback device, gaming system, mobile computing device, or any other type and / or form of computing, telecommunications or media device capable of communication. In some embodiments, computing device 100 may have a different processor, operating system and input device consistent with the device. For example, in one embodiment, computing device 100 is a smartphone, mobile device, tablet computer or personal digital assistant. Furthermore, computing device 100 may be any workstation, desktop computer, laptop or notebook computer, server, handheld computer, mobile phone, any other computer, or other form of computing or telecommunications device capable of communication and having sufficient processor power and memory capacity to perform the operations described herein.

[0047] The aforementioned aspects of the operating environment and components will become apparent in the context of the systems and methods disclosed herein.

[0048] B.SAR ADC

[0049] The various embodiments disclosed herein relate to SAR ADCs, such as high-speed SAR ADCs or ultra-high-speed SAR ADCs. In some embodiments, the SAR ADC is relatively unaffected by PVT variations and is configured for 200G / 100G network applications. In some embodiments, the systems and methods described herein are used for SAR ADCs used in network integrated circuits (ICs), such as 225Gbps PAM4 optical transceivers or other transceivers. In some embodiments, the systems and methods described herein provide speed advantages without significant power / area loss. SAR ADCs can be used with reference to the above. Figure 1A The SAR ADC can be connected to or communicate with the various components discussed in C. The SAR ADC operates according to the principles described herein and uses the conversion structure and operation described in U.S. Patent No. 10,903,846, which is assigned to the assignee of this application and whose entire contents are incorporated herein by reference. The SAR ADC 300 is an integrated circuit (IC) device integrated on a single substrate, disposed in a multi-chip package, or in some embodiments, part of another IC device.

[0050] In some embodiments, the SAR ADC includes a digital-to-analog converter (DAC) circuit for sampling the input voltage. In some embodiments, the SAR ADC includes a first comparator coupled to the DAC circuit and a first set of memory circuitry coupled between the first comparator and the DAC circuitry. In some embodiments, the SAR ADC includes a second comparator coupled to the DAC circuitry and a second set of memory circuitry coupled between the second comparator and the DAC circuitry. In one aspect, the SAR ADC includes control circuitry configured to select a corresponding comparator from the first and second comparators for each of a plurality of bits (e.g., N bits, where N is any integer) corresponding to the input voltage to determine the state of each of the plurality of bits during a corresponding time period.

[0051] In some embodiments, the DC offset calibration engine uses different methods to calibrate the first and second comparators. In some embodiments, the system and method utilize the DC offset correction circuit of each comparator to correct the DC offset of each comparator. The SAR ADC output Dout[N-1:0] is sent to the calibration engine to obtain the DC offset of each comparator. Based on the offset information, the offset calibration codes of the two comparators are sent to their respective offset correction circuits to correct the individual comparator offsets.

[0052] In some embodiments, the DC offset calibration of the first comparator uses only the most significant bit (MSB) of the SAR ADC output (e.g., Dout[N-1]). In some embodiments, after averaging the MSB bits of the output (e.g., Dout[N-1]), the DC offset information of the first comparator is extracted, and the offset code of the first comparator is updated accordingly. In some embodiments, the DC offset calibration of the second comparator uses all bits of the SAR ADC output (e.g., Dout[N-1:0]). In some embodiments, after averaging all bits of the output (e.g., Dout[N-1:0]), the DC offset information of the second comparator is extracted, and the offset code of the second comparator is updated accordingly.

[0053] In some embodiments, the DC offset information associated with the offset difference between the first and second comparators can be determined after offset calibration of one or both of the first and second comparators. The offset difference is extracted by averaging all bits of the output from the second comparator (e.g., the least significant bits of Dout[N-1:0] or (Dout[M-1:0])). The offset difference is compared to a threshold, and if it is higher than the threshold, the offset codes of the first and / or second comparators are updated accordingly.

[0054] Advantageously, the disclosed SAR ADC achieves both speed and power efficiency. In one aspect, the first comparator has a faster detection speed than the second comparator, wherein the second comparator has higher sensitivity than the first comparator. Therefore, selectively configuring the first and second comparators allows the states of different bits of the input voltage to be determined in an effective manner. For example, the state of the most significant bit (MSB) can be determined rapidly by the first comparator, while the state of the least significant bit (LSB) can be determined with high sensitivity by the second comparator. In one configuration, the output ports of the first and second comparators are coupled to a memory circuit, such that the determined states of the bits can be stored by the memory circuit. However, a large number of memory circuits (e.g., more than seven) coupled to the first and second comparators can result in a large capacitive load, which can reduce the power efficiency and / or operating speed of the first and second comparators. By implementing a first comparator coupled to a first set of memory circuits and a second comparator coupled to a second set of memory circuits, the capacitive load at the output ports of the first and second comparators can be reduced. By reducing capacitive load, the first and second comparators can operate in a fast and power-efficient manner.

[0055] Figure 2This is a block diagram depicting a communication device 200 according to one or more embodiments. In some embodiments, the communication device 200 is a system, apparatus, or device for network communication (e.g., an optical transceiver sampling at 180 gigabits per second). For example, the communication device 200 is part of a network device 106, node 192, device 102, or other part of a network communicating with device 102. In some embodiments, the device 200 includes a transmitter 210, a receiver 220, and a processor 280. These components may operate together to communicate with another communication device via a network cable (e.g., Ethernet, USB, FireWire, etc.) and / or via wireless media (e.g., Wi-Fi, Bluetooth, 60 GHz link, cellular network, etc.). In some embodiments, the communication device 200 includes a... Figure 2 It can display more, fewer, or different components.

[0056] Transmitter 210 is a circuit or component that receives transmission data TX Data from processor 280 and generates output signals Out+ and Out-. Transmitter 210 can receive N bits of digital data TX Data from processor 280 and generate output signals Out+ and Out- having a voltage or current corresponding to the digital data TX Data. Output signals Out+ and Out- can be differential signals. In some embodiments, transmitter 210 can generate single-ended signals or signals with different representations for output signals Out+ and Out-. In some embodiments, transmitter 210 transmits output signals Out+ and Out- via a network cable. In some embodiments, transmitter 210 provides output signals Out+ and Out- to a wireless transmitter (not shown) that can up-convert output signals Out+ and Out- to generate radio frequency wireless transmission signals and transmit the wireless transmission signals via a wireless medium.

[0057] Receiver 220 is a circuit or component that receives input signals In+ and In- and generates received data RX Data. In some embodiments, receiver 220 receives input signals In+ and In- via a network cable. Input signals In+ and In- may be differential signals. In some embodiments, receiver 220 may receive single-ended signals or signals representing different aspects of input signals In+ and In-. In some embodiments, receiver 220 receives input signals In+ and In- from a wireless receiver (not shown), which may receive wireless signals via a wireless medium and down-convert the wireless signals to generate input signals In+ and In- at baseband frequencies. In some embodiments, receiver 220 receives input signals In+ and In- and generates N-bit digital data RX Data corresponding to the voltage or current of input signals In+ and In-. Receiver 220 may provide the digital data RX Data to processor 280. In some embodiments, receiver 220 includes a SAR ADC 225, which converts input signals In+ and In- into N-bit digital data RX Data in a power-efficient manner. A detailed description of the implementation and operation of SAR ADC 225 is provided below. Figures 3 to 8 supply.

[0058] Processor 280 is a circuit or component capable of performing logical calculations. In some embodiments, processor 280 is implemented as a field-programmable gate array, an application-specific integrated circuit (ASIC), or a state machine. Processor 280 is electrically coupled to transmitter 210 and receiver 220 via conductive traces or a bus connection. In this configuration, processor 280 can receive data RX Data from receiver 220 and perform logical calculations or execute various application programs based on the state of the received data RX Data. Processor 280 can also generate data TX Data and provide data TX Data to transmitter 210.

[0059] Figure 3 This is a block diagram of a SAR ADC 300 according to one or more embodiments. The SAR ADC 300 may be implemented as... Figure 2 The SAR ADC 225. In some embodiments, the SAR ADC 300 includes sampling and DAC circuitry 310, comparators 330A and 330B, a finite state machine 366, offset correction circuitry 380A and 380B, and a calibration engine 390. The finite state machine 366 includes a first set of storage circuitry 360A, a second set of storage circuitry 360B, and control circuitry 370. The components of the SAR ADC 300 can operate together to receive input signals In+ and In- and perform successive approximation analog-to-digital conversion to generate N-bit data RXData corresponding to the voltages of the input signals In+ and In-. In some embodiments, the SAR ADC 300 includes a ratio Figure 3 The document shows more, fewer, or different components. Despite... Figure 3 In the diagram, the sampling and DAC circuit 310, comparators 330A and 330B, and storage circuits 360A and 360B are shown to generate and process differential signals, but some or all of these components can generate and process single-ended signals.

[0060] In some embodiments, the sampling and DAC circuit 310 is a circuit or component that samples input signals In+ and In- and generates DAC output signals DAC Out+ and DAC Out-. In one embodiment, the sampling and DAC circuit 310 is embodied as a capacitive DAC circuit. In some embodiments, the sampling and DAC circuit 310 includes an input port 312 for receiving input signals In+ and In-, a feedback port 314 for receiving N-bit data RX Data, and an output port 316 for outputting DAC output signals DAC Out+ and DAC Out-. In one configuration, NM feedback ports 314 of the sampling and DAC circuit 310 are coupled to NM output ports 322 of a first set of storage circuits 360A, and M feedback ports 314 of the sampling and DAC circuit 310 are coupled to M output ports 322 of a second set of storage circuits 360B. In one example, N may be 9 and M may be 4. In some embodiments, N and M may be other integers. In one configuration, the first output port of the sampling and DAC circuit 310 is coupled to the first input ports of comparators 330A and 330B. In another configuration, the second output port of the sampling and DAC circuit 310 is coupled to the second input ports of comparators 330A and 330B. In this configuration, the sampling and DAC circuit 310 receives input signals In+ and In- at input port 312 and receives N-bit data RX Data at feedback port 314, and samples the input signals In+ and In-. The sampling and DAC circuit 310 can perform DAC based on the N-bit data RX Data to generate DAC output signals DACOut+ and DACOut- at output port 316. The sampling and DAC circuit 310 can provide the DAC output signals DACOut+ and DACOut- to comparators 330A and 330B. In one method, for the Xth bit of N-bit data RXData, the DAC output signals DACOut+ and DACOut- indicate the voltages (e.g., Vin+ and Vin-) of the input signals In+ and In-, where the voltages correspond to an N number of MSBs of Data RX. In another method, the sampling and DAC circuit 310 generates the DAC output signals DACOut+ and DACOut- according to the following equation:

[0061]

[0062] In some embodiments, comparator 330A is a circuit or component that receives DAC output signals DACOut+ and DACOut-, and determines the state of the corresponding bit of data RXData based on the DAC output signals DACOut+ and DACOut-. In one configuration, comparator 330A includes a first input port coupled to a first output port of sampling and DAC circuit 310 to receive the DAC output signal DACOut+, a second input port coupled to a second output port of sampling and DAC circuit 310 to receive the DAC output signal DACOut-, a first output port coupled to a first input port of first group of storage circuit 360A, a second output port coupled to a second input port of first group of storage circuit 360A, and a clock input port coupled to a first clock output port of control circuit 370. The first output port of comparator 330A can be directly coupled to the first input port of storage circuit 360A, and the second output port of comparator 330A can be directly coupled to the second input port of storage circuit 360A. Similarly, the first output port of comparator 330B can be directly coupled to the first input port of storage circuit 360B, and the second output port of comparator 330B can be directly coupled to the second input port of storage circuit 360B. In this configuration, comparator 330A can be enabled or disabled according to the clock signal CLK1 from control circuit 370. For example, comparator 330A is enabled in response to the rising edge of clock signal CLK1 or logic state '1'. For example, comparator 330A is disabled in response to the falling edge of clock signal CLK1 or logic state '0'. When comparator 330A is enabled, comparator 330A can determine the state of the bit according to the DAC output signals DAC Out+ and DAC Out-, and generate comparator outputs CompOut1+ and CompOut1- at output port 322 indicating the determined state of the bit. For example, when comparator 330A is enabled, in response to the voltage difference between the DAC output signals DACOut+ and DACOut- which are above 0V or the reference voltage, comparator 330A can generate a comparator output CompOut1+ with logic state '1' and a comparator output CompOut1- with logic state '0'. For example, when comparator 330A is enabled, in response to the voltage difference between the DAC output signals DACOut+ and DACOut- which are below 0V or the reference voltage, comparator 330A can generate a comparator output CompOut1+ with logic state '0' and a comparator output CompOut1- with logic state '1'. When comparator 330A is disabled, comparator 330A can reset comparator outputs CompOut1+ and CompOut1- to logic state '0'. Comparator 330A can provide comparator outputs CompOut1+ and CompOut1- to the first set of memory circuits 360A.The comparator outputs CompOut1+ and CompOut1- can be differential signals.

[0063] In some embodiments, comparator 330B is a circuit or component that receives DAC output signals DACOut+ and DACOut- and determines the corresponding bit of data RXData based on the DAC output signals DACOut+ and DACOut-. In some embodiments, comparator 330A has a higher detection speed and / or higher power efficiency than comparator 330B, wherein comparator 330B has higher sensitivity than comparator 330A. In one configuration, comparator 330B includes a first input port coupled to a first output port of sampling and DAC circuit 310 to receive the DAC output signal DACOut+, a second input port coupled to a second output port of sampling and DAC circuit 310 to receive the DAC output signal DACOut-, a first output port coupled to a first input port of second set of storage circuit 360B, a second output port coupled to a second input port of second set of storage circuit 360B, and a clock input port coupled to a second clock output port of control circuit 370. The operation of comparator 330B is similar to that of comparator 330A, except that comparator 330B is enabled or disabled in response to clock signal CLK2 instead of clock signal CLK1, and comparator 330B provides comparator outputs CompOut2+ and CompOut2- to the second set of storage circuits 360B instead of the first set of storage circuits 360A. Therefore, for the sake of brevity, detailed descriptions of repeated parts are omitted in this document.

[0064] In some embodiments, the first set of storage circuits 360A is a group of components storing NM bits (e.g., MSB) of data. In one embodiment, the first set of storage circuits 360A is embodied as NM flip-flops or latches (e.g., ratio SR latches). In some embodiments, a first input port of each storage circuit 360A is coupled to a first output port of comparator 330A, and a second input port of each storage circuit 360A is coupled to a second output port of comparator 330A. In some embodiments, an enable port of each storage circuit 360A is coupled to a corresponding enable output port of control circuit 370, and an output port of each storage circuit 360A is coupled to a corresponding feedback port of sampling and DAC circuit 310. In this configuration, each storage circuit 360A can be enabled or disabled according to the corresponding bit of the NM bit enable signal En1. For example, the first storage circuit 360A is enabled in response to an enable signal EN1 with

[00001] ; the second storage circuit 360A is enabled in response to an enable signal EN1 with

[00010] ; the third storage circuit 360A is enabled in response to an enable signal EN1 with

[00100] ; the fourth storage circuit 360A is enabled in response to an enable signal EN1 with

[01000] ; and the fifth storage circuit 360A is enabled in response to an enable signal EN1 with

[10000] . For example, all of the first group of storage circuits 360A are disabled in response to an enable signal EN1 with

[00000] . When a storage circuit 360A is enabled, it can update the corresponding bits of the data RX Data according to the comparator outputs CompOut1+ and CompOut1-. For example, if storage circuit 360A is enabled, then in response to comparator output CompOut1+ with logic state '1' and comparator output CompOut1- with logic state '0', storage circuit 360A can update the corresponding bit of data RX Data to '1'. For example, if storage circuit 360A is enabled, then in response to comparator output CompOut1- with logic state '1' and comparator output CompOut1+ with logic state '0', storage circuit 360A can update the corresponding bit of data RX Data to '0'. If storage circuit 360A is disabled, then storage circuit 360A can maintain or preserve the corresponding bit of data RX Data (Dout[N-1, 0]), regardless of the comparator outputs CompOut1+ and CompOut1- at the input port.

[0065] In some embodiments, the second set of storage circuits 360B is a group of components storing M bits (e.g., LSB) of data. In one embodiment, the second set of storage circuits 360B is embodied as M flip-flops or latches. In some embodiments, a first input port of each storage circuit 360B is coupled to a first output port of comparator 330B, and a second input port of each storage circuit 360B is coupled to a second output port of comparator 330B. In some embodiments, an enable port of each storage circuit 360B is coupled to a corresponding enable output port of control circuit 370, and an output port of each storage circuit 360B is coupled to a corresponding feedback port of sampling and DAC circuit 310. The operation of storage circuit 360B is similar to that of the first set of storage circuits 360A, except that each of the storage circuits 360B is enabled or disabled in response to the corresponding state of the M-bit enable signal En2 instead of the NM-bit enable signal En1, and each of the storage circuits 360B stores and outputs the corresponding bit (e.g., instead of the NM-bit bits of the data RXData, such as the MSB) of the M bits (e.g., LSB or Dout[M-1, 0]) of the data RXData. Therefore, for the sake of brevity, detailed descriptions of repeated parts are omitted here.

[0066] In some embodiments, control circuitry 370 is a component that configures comparators 330A, 330B and storage circuits 360A, 360B to perform successive approximation analog-to-digital conversion. In one embodiment, control circuitry 370 is implemented as a state machine or as one or more digital logic circuits. In some embodiments, control circuitry 370 includes, for example, an input port that receives a clock signal CLK from a clock generator (not shown), a first clock output port coupled to the clock input port of comparator 330A, a second clock output port coupled to the clock input port of comparator 330B, NM number of enable output ports coupled to enable ports of the first set of storage circuits 360A, and M number of enable output ports coupled to enable ports of the second set of storage circuits 360B. In this configuration, control circuitry 370 may generate a clock signal CLK1 at the first clock output port based on the clock signal CLK and provide the clock signal CLK1 to the first comparator 330A. Additionally, the control circuit 370 can generate a clock signal CLK2 at the second clock output port based on the clock signal CLK, and provide the clock signal CLK2 to the second comparator 330B. Furthermore, the control circuit 370 can generate an NM-bit enable signal En1 at NM enable output ports based on the clock signal CLK, and provide the NM-bit enable signal En1 to the first group of storage circuits 360A. Furthermore, the control circuit 370 can generate an M-bit enable signal En2 at M enable output ports based on the clock signal CLK, and provide the M-bit enable signal En2 to the second group of storage circuits 360B. In some embodiments, one or more of the signals CLK1, CLK2, En1, and En2 are generated independently of the clock signal CLK, but can be generated based on the comparator outputs CompOut1+, CompOut1- and / or the comparator outputs CompOut1+, CompOut1-. For example, signals CLK1, CLK2, En1, and En2 can be generated in response to the rising edge of the comparator outputs CompOut1+, CompOut1-, CompOut2+, and CompOut2-.

[0067] In one aspect, control circuit 370 generates clock signals CLK1, CLK2 and enable signals En1, En2 to configure sampling and DAC circuit 310, comparators 330A, 330B, and storage circuits 360A, 360B to perform successive approximation analog-to-digital conversion. In one method, control circuit 370 may generate clock signal CLK1 with a series of pulses to select or enable comparator 330A during corresponding time periods to determine the state of NM bits (e.g., MSB) of data RX Data, while simultaneously generating clock signal CLK2 with a logic state '0' to disable comparator 330B. When comparator 330A is enabled, control circuit 370 may generate an NM bit enable signal En1 to configure storage circuit 360A to store the determined state of NM bits (e.g., MSB) of data RX Data. For example, for the MSB of data RX Data, sampling and DAC circuit 310 may sample input signals In+, In- to generate DAC output signals DACOut+, DACOut-. In response to the rising edge of clock signal CLK1 or logic state '1', comparator 330A generates comparator outputs CompOut1+ and CompOut1- indicating the MSB state based on DAC output signals DACOut+ and DACOut-. Then, in response to the pulse of the corresponding bit of enable signal En1 or logic state '1', corresponding storage circuit 360A stores the MSB state of data RX Data based on comparator outputs CompOut1+ and CompOut1-. For subsequent bits of data RX Data, sampling and DAC circuit 310 samples input signals In+ and In- based on the state of previous bits of data RX Data to generate DAC output signals DACOut+ and DACOut-. In response to the rising edge of clock signal CLK1 or logic state '1', comparator 330A generates comparator outputs CompOut1+ and CompOut1- indicating the state of subsequent bits based on DAC output signals DACOut+ and DACOut. Next, in response to the pulse or logic state '1' of the corresponding bit of the enable signal En1, the corresponding storage circuit 360A can store the state of the subsequent bits of the data RX Data according to the comparator outputs CompOut1+ and CompOut1-. The process can be repeated for the remaining bits of the NM bits of the data RX Data.

[0068] After determining the state of the NM bits of data RX Data, control circuit 370 can generate a clock signal CLK2 with a series of pulses to select or enable comparator 330B within a corresponding time period to determine the state of the M bits (e.g., LSBs) of data RX Data, and simultaneously generate a clock signal CLK1 with a logic state '0' to disable comparator 330A. When comparator 330B is enabled, control circuit 370 can generate an M-bit enable signal En2 to configure storage circuit 360B to store the determined state of the M bits (e.g., LSBs) of data RX Data. For example, for the Mth bit of data RX Data, sampling and DAC circuit 310 can sample input signals In+ and In- according to the states of the previous NM bits of data RX Data to generate DAC output signals DACOut+ and DACOut-, and comparator 330B can generate comparator outputs CompOut2+ and CompOut2- indicating the state of the Mth bit according to the DAC output signals DACOut+ and DACOut-. Then, corresponding storage circuit 360B can store the state of the Mth bit of data RX Data. For subsequent bits of the data RX Data, the sampling and DAC circuit 310 samples the input signals In+ and In- based on the state of the previous bits of the data RX Data to generate DAC output signals DAC Out+ and DAC Out-. In response to the rising edge of the clock signal CLK2 or logic state '1', the comparator 330B generates comparator outputs Comp Out2+ and Comp Out2- indicating the state of subsequent bits based on the DAC output signals DAC Out+ and DAC Out-. Then, in response to the pulse of the corresponding bit of the enable signal En2 or logic state '1', the corresponding storage circuit 360B stores the state of subsequent bits of the data RX Data based on the comparator outputs Comp Out2+ and Comp Out2-. This process can be repeated for the remaining M bits of the data RX Data.

[0069] Advantageously, the SAR ADC 300 achieves both speed and power efficiency. In one aspect, comparator 330A has a higher detection speed and / or higher power efficiency than comparator 330B, wherein comparator 330B has higher sensitivity than comparator 330A. Therefore, comparator 330A can determine the state of a first subset of the bits of data RX Data (e.g., MSB), while comparator 330B can determine the state of a second subset of the bits of data RX Data (e.g., LSB). In one embodiment, a multiplexer can be added between the output ports of comparators 330A and 330B and the input ports of memory circuits 360A and 360B, and comparator 330A or comparator 330B can be electrically coupled to memory circuits 360A and 360B. However, electrically coupling comparator 330A or comparator 330B to memory circuits 360A and 360B increases the capacitive load at the output ports of comparators 330A and 330B. Such an increase in capacitive load reduces speed and power efficiency. By implementing comparator 330A, which has an output port directly coupled to the input port of storage circuit 360A, and comparator 330B, which has an output port directly coupled to the input port of storage circuit 360B, the capacitive load at the output ports of comparators 330A and 330B can be reduced, thereby achieving speed and power efficiency. A driver can be positioned between the input ports of comparator 330A and storage circuit 360A, and between comparator 330B and storage circuit 360B.

[0070] Offset correction circuits 380A and 380B are configured to provide offset correction (e.g., reduce offset error) for comparators 330A and 330B, respectively. In some embodiments, offset correction circuit 380A corrects the DC offset of comparator 330A, and offset correction circuit 380B corrects the DC offset of comparator 330A. Offset correction circuit 380A receives the offset correction code of comparator 330A from calibration engine 390 at input 392A, and offset correction circuit 380B receives the offset correction code of comparator 330B from calibration engine 390 at input 392B. The offset correction code can correct the offset caused by the input circuitry of SAR ADC 300 and / or comparators 330A and 330B. The use of offset correction circuits 380A and 380B allows for adaptation to different static and dynamic DC offsets of comparators 330A and 330B, thereby reducing the degradation of SAR ADC performance, especially in time-interleaved ADCs. In some embodiments, each of the offset correction circuits 380A and 380B includes one or more analog correction circuits. The analog correction circuits are configured to control one or more programmable capacitors (e.g., a set of four binary-scale switchable capacitors) to adjust the offset current, voltage, or power. In some embodiments, the offset correction circuits 380A and 380B receive a digital offset correction code and include a DAC and capacitors driven by the DAC. The DAC, in response to the digital offset correction code, makes small adjustments to the inputs of comparators 330A and 330B via the capacitors. In some embodiments, each of the offset correction circuits 380A and 380B includes an offset register.

[0071] Calibration engine 390 is configured to provide an offset correction code for comparator 330A at input 392A and an offset correction code for comparator 330B at input 392B. Calibration engine 390 determines the offset correction codes for comparators 330A and 330B in response to data Dout[N-1,0]. In some embodiments, all output data bits (Dout[N-1,0]) are not used to calibrate comparator 330A because all output data bits (Dout[N-1,0]) at least partially indicate the offset of comparator 330B, rather than the offset of comparator 330A. In some embodiments, the first NM bits of Dout[N-1:0] are not used to calibrate comparator 330A, wherein non-binary DAC weights for overrange protection are implemented to improve the effective number of bits (ENOB) of SAR and overcome problems such as incomplete DAC instability, reference jumps, comparator offset mismatch, and high noise in the first few bit comparison cycles.

[0072] In the two-comparator SAR ADC of SAR ADC 300, over-range protection is highly effective for optimizing the SAR ADC's power, speed, and noise performance. The design of comparator 330A, with its higher speed and lower power than comparator 330B, results in higher noise in comparator 330A than in comparator 330B. In some embodiments, over-range protection helps reduce the impact of the high noise associated with comparator 330A on the SAR ADC ENOB. Additionally, over-range protection reduces the impact of residual DC offset between comparator 330A and comparator 330B (even after DC offset calibration of comparator 330A and comparator 330B) on the SAR ADC ENOB. For some over-range protection schemes, the MSB bits are the sum of the following bits in the first DAC weight range of comparator 330A. For example, for an 8-bit SAR ADC, an example DAC weight scheme is 120, 64, 32, 16, 8, 8, 4, 2, 1. The first 5 bits, weighted 120, 64, 32, 16, and 8, are used for comparator 330A, and the remaining 4 bits, weighted 8, 4, 2, and 1, are used for comparator 330B. In this case, for comparator 330A, when the DC offset is very small and the noise is relatively small (total error << 8), the first 5 bits are 10000 or 01111. This means that the binary value of the first 5 bits is always 120 and the DC offset of comparator 330A cannot be extracted.

[0073] In some embodiments, the offset correction code for comparator 330B is determined using all output data bits (Dout[N-1,0]) and the offset code for comparator 330A is determined using a single output data bit (e.g., MSB(Dout[N-1])) to allow extraction of the DC offset of comparator 330A. In some embodiments, the offset correction code is determined using polarity-based offset detection. In some embodiments, offset correction circuits 380A and 380B and calibration engine 390 can handle cases where the comparator offset is large without requiring large out-of-range protection. In some embodiments, offset correction circuits 380A and 380B and calibration engine 390 correct the comparator offset such that bit comparison error is reduced when comparator 330B is used immediately after it.

[0074] Figure 4 This is to illustrate according to one or more embodiments Figure 3 Timing diagram 400 for the operation of the SAR ADC 300. In some embodiments, control circuitry 370 generates clock signals CLK1, CLK2 and enable signals En1, En2 to configure sampling and DAC circuitry 310, comparators 330A, 330B and storage circuitry 360A, 360B to perform successive approximation analog-to-digital conversion to determine the state of N-bit data RXData. Figure 4In the example shown, N is 9 and M is 4. In some embodiments, the principles disclosed herein can be applied to perform successive approximation analog-to-digital conversion to determine the state of different numbers of individual bits in the data RX. In one method, control circuitry 370 can generate a clock signal CLK1 with pulses at times T1 to T5, and a clock signal CLK2 with pulses at times T6 to T9. In one aspect, during times T1 to T5, comparator 330A is enabled in response to the pulses of clock signal CLK1, while comparator 330B is disabled. In another aspect, during times T6 to T9, comparator 330B is enabled in response to the pulses of clock signal CLK2, while comparator 330A is disabled.

[0075] In one example, near or before time T1, the sampling and DAC circuit 310 samples the input signals In+ and In- to generate DAC output signals DACOut+ and DACOut-. After the DAC output signals DACOut+ and DACOut- stabilize at time T1, the comparator 330A generates comparator outputs CompOut1+ and CompOut1- indicating the state of the first bit (or MSB) of the data RX Data based on the DAC output signals DACOut+ and DACOut-. Then, the corresponding storage circuit 360A stores the state of the first bit or MSB of the data RX Data in response to the logic state '1' of the enable signal En1 (9).

[0076] In one example, after time T1 and near or before time T2, the sampling and DAC circuit 310 can perform DAC to generate DAC output signals DACOut+ and DACOut- based on the state of the first bit of the data RX Data. After the DAC output signals DACOut+ and DACOut- stabilize at time T2, the comparator 330A can generate comparator outputs CompOut1+ and CompOut1- indicating the state of the subsequent bit (or the second bit) based on the DAC output signals DACOut+ and DACOut-. Then, the corresponding storage circuit 360A can store the state of the subsequent bit (or the second bit) of the data RX Data in response to the logic state '1' of the enable signal En1 (8).

[0077] In one example, after time T2 and near or before time T3, the sampling and DAC circuit 310 can perform DAC to generate DAC output signals DAC+ and DAC- based on the determined states of two bits of the data RX Data. After the DAC output signals DAC+ and DAC- stabilize at time T3, the comparator 330A can generate comparator outputs CompOut1+ and CompOut1- indicating the state of the subsequent bit (or the third bit) based on the DAC output signals DAC+ and DAC-. Then, the corresponding storage circuit 360A can store the state of the subsequent bit (or the third bit) of the data RX Data in response to the logic state '1' of the enable signal En1 (7).

[0078] In one example, after time T3 and near or before time T4, the sampling and DAC circuit 310 can perform DAC to generate DAC output signals DAC+ and DAC- based on the determined states of the three bits of data RX Data. After the DAC output signals DAC+ and DAC- stabilize at time T4, comparator 330A can generate comparator outputs CompOut1+ and CompOut1- indicating the state of the subsequent bit (or the fourth bit) based on the DAC output signals DAC+ and DAC-. Then, the corresponding storage circuit 360A can store the state of the subsequent bit (or the fourth bit) of data RX Data in response to the logic state '1' of the enable signal En1 (6).

[0079] In one example, after time T4 and near or before time T5, the sampling and DAC circuit 310 can perform DAC to generate DAC output signals DAC+ and DAC- based on the determined states of the four bits of data RX Data. After the DAC output signals DAC+ and DAC- stabilize at time T5, comparator 330A can generate comparator outputs CompOut1+ and CompOut1- indicating the state of subsequent bits (or the fifth bit) based on the DAC output signals DAC+ and DAC-. Then, the corresponding storage circuit 360A can store the state of subsequent bits (or the fifth bit) of data RX Data in response to the logic state '1' of the enable signal En1 (5).

[0080] In one example, after time T5 and near or before time T6, the sampling and DAC circuit 310 can perform DAC to generate DAC output signals DAC+ and DAC- based on the determined states of the five bits of data RX Data. After the DAC output signals DAC+ and DAC- stabilize at time T6, the comparator 330B can generate comparator outputs CompOut2+ and CompOut2- indicating the state of the subsequent bit (or the sixth bit) based on the DAC output signals DAC+ and DAC-. Then, the corresponding storage circuit 360B can store the state of the subsequent bit (or the sixth bit) of data RX Data in response to the logic state '1' of the enable signal En2(4).

[0081] In one example, after time T6 and near or before time T7, the sampling and DAC circuit 310 can perform DAC to generate DAC output signals DAC+ and DAC- based on the determined states of the six bits of data RX Data. After the DAC output signals DAC+ and DAC- stabilize at time T7, the comparator 330B can generate comparator outputs CompOut2+ and CompOut2- indicating the state of the subsequent bit (or the seventh bit) based on the DAC output signals DAC+ and DAC-. Then, the corresponding storage circuit 360B can store the state of the subsequent bit (or the seventh bit) of data RX Data in response to the logic state '1' of the enable signal En2(3).

[0082] In one example, after time T7 and near or before time T8, the sampling and DAC circuit 310 performs digital-to-analog conversion based on the determined states of the seven bits of data RX Data to generate DAC output signals DAC+ and DAC-. After the DAC output signals DAC+ and DAC- stabilize at time T8, comparator 330B generates comparator outputs CompOut2+ and CompOut2- indicating the state of subsequent bits (or the eighth bit) based on the DAC output signals DAC+ and DAC-. Then, the corresponding storage circuit 360B stores the state of subsequent bits (or the eighth bit) of data RX Data in response to the logic state '1' of the enable signal En2(2).

[0083] In one example, after time T8 and near or before time T9, the sampling and DAC circuit 310 performs digital-to-analog conversion based on the state of the eight bits of data RX Data to generate DAC output signals DAC+ and DAC-. After the DAC output signals DAC+ and DAC- stabilize at time T9, comparator 330B generates comparator outputs CompOut2+ and CompOut2- indicating the state of subsequent bits (or the ninth bit) based on the DAC output signals DAC+ and DAC-. Then, the corresponding storage circuit 360B stores the state of subsequent bits (or the ninth bit) of data RX Data in response to the logic state '1' of the enable signal En2(1).

[0084] refer to Figure 5 The calibration engine 390 is configured as a DC offset calibration engine, and outputs from the input 502 to the output port 322. Figure 3 ) Receives output data Dout[N-1] and provides offset correction code at output 520A for comparator 330A for input 392A of offset correction circuit 380B. Figure 3 The output data Dout[N-1] is received at input 520B and provides an offset correction code at output 520B for comparator 330B to receive at input 392B of offset correction circuit 380B. The value of output data Dout[N-1] can be provided over a period of time in which the sample at input port 312 varies with the intermediate average value of the input range of the SAR DAC (e.g., 0V in some embodiments). Calibration engine 390 includes averaging circuit 506A, averaging circuit 506B, offset code calculation circuit 516A, and offset code calculation circuit 516B. Calibration engine 390 includes input 504A for output data Dout[N-1] from input 502 and input 504B for output data Dout[N-1:0] from input 502.

[0085] The averaging circuit 506A averages the value of Dout[N-1] over a period of time. In some embodiments, the averaging circuit 506A provides a running average. The offset code calculation circuit 516A receives the average value of the output data Dout[N-1]. If the average value is higher than a threshold (expected average value, e.g., 0.5), the offset code calculation circuit 516A decreases the offset signal (e.g., offset command) of the comparator 330A to decrease the DC offset, and if the average value is lower than the threshold, the offset signal (e.g., offset command) increases to increase the DC offset.

[0086] The averaging circuit 506B averages the values ​​of Dout[N-1:0] over a period of time. In some embodiments, the averaging circuit 506B provides a running average. The offset code calculation circuit 516B receives the average value of the output data Dout[N-1:0]. If the average value is higher than a threshold (expected average value, e.g., 0.5), the offset code calculation circuit 516B decreases the offset command of comparator 330B to decrease the DC offset, and if the average value is lower than the threshold, it increases the offset command to increase the DC offset.

[0087] The averaging circuits 506A and 506B can be any hardware circuitry or software process used to determine the average value. Multipliers, dividers, registers, adders, etc., can be used. Similar to the averaging circuits 506A and 506B, the offset code calculation circuits 516A and 516B can be any hardware circuitry or software process used to determine the offset code. The averaging circuits 506A and 506B and the offset code calculation circuits 516A and 516B can be integrated with the SAR ADC 300 (e.g., provided as part of the control circuitry 370 or another or other part of the SAR ADC 300). In some embodiments, the calibration engine 390 is a processor, microcontroller (e.g., executing firmware), ASIC, field-programmable gate array (FPGA), or logic device, or any other type and form of dedicated semiconductor logic or processing circuitry system capable of processing or supporting the operations described herein. In some embodiments, the operation associated with the calibration engine 390 is partially controlled by the processor 280 ( Figure 2 )implement.

[0088] The calibration operations described herein can be performed periodically during device initialization, power-on, and during device operation. In some embodiments, the calibration operations can be initiated in response to thermal changes, detection errors, etc.

[0089] refer to Figure 6In some embodiments, the averaging circuit 506A includes an input 504A, an adder 604A, and an accumulator 606A. The accumulator 606A is coupled to an offset code calculation circuit 516A. The MSB bit of the data output Dout[N-1] is received as either 0 or 1 at input 504A. The MSB bit of the data output is subtracted in adder 604A from the value 0.5 provided at input 605 of adder 604A. The result is -0.5 or 0.5, and the average is equal to 0. The value Dout[N-1]-0.5 is provided to accumulator 606A (e.g., the averaging circuit). For the averaging circuit implementation, Dout[N-1]-0.5 is accumulated K times (where K is an integer (e.g., 5, 10, 20, 50, 100, etc.)). In some embodiments, the average is calculated at output 620 as OS1_sign = ∑(Dout[N-1]-0.5) / K. For accumulator operations, Dout[N-1]-0.5 is added continuously and the accumulator output OS1_sign value is equal to the average value given by ∑(μ*(Dout[N-1]-0.5)), where in some embodiments μ is a coefficient that defines the accumulator bandwidth.

[0090] The OS1_sign value at output 620 is used to update comparator 330A. Figure 3 The offset command of ) . When the OS1_sign value is greater than 0, comparator 330A ( Figure 3 The comparator 330A has a positive DC offset. Therefore, the offset signal (e.g., offset command) is updated by the offset code calculation circuit 516A to decrease the DC offset of the comparator 330A. When the OS1_sign value is less than 0, the comparator 330A has a negative DC offset. Therefore, the offset signal (e.g., offset command) is updated by the offset code calculation circuit 516A to increase the DC offset of the comparator 330A. In some embodiments, the adder 604A may be positioned between the accumulator 606A and the offset code calculation circuit 516A.

[0091] refer to Figure 7 In some embodiments, the averaging circuit 506B includes an input 504B, an adder 604B, and an accumulator 606B. The accumulator 606B is coupled to the offset code calculation circuit 516B. All bits of the data output Dout[N-1:0] are received at input 504B as a range from 0 to 2. N-1 The value of the data output Dout[N-1:0] is subtracted from the value of 2 provided at input 607 of adder 604B in adder 604B. (N-1) -0.5. The result range is from -(2 (N-1) -0.5) to 2 (N-1) -0.5, the average is 0. The range is from -(2 (N-1) -0.5) to 2 (N-1)The result of -0.5 is provided to the accumulator 606B (e.g., the averaging circuit). For the averaging circuit implementation, Dout[N-1:0]-(2 (N-1) -0.5) is accumulated K times (where K is an integer (e.g., 5, 10, 20, 50, 100, etc.)). In some embodiments, at output 622, the average value is calculated as OS2_sign = ∑(Dout[N-1:0] - (2 (N-1)- 0.5)) / K. For accumulator operations, Dout[N-1]-0.5 are added consecutively and the accumulator output OS2_sign value is equal to the average value given by ∑(μ*(Dout[N-1:0]-(2(N-1)-0.5))), where in some embodiments μ is a coefficient that defines the accumulator bandwidth.

[0092] The OS2_sign value at output 622 is used to update the offset signal (e.g., offset command) of comparator 330B. When the OS2_sign value is greater than 0, comparator 330B ( Figure 3 The comparator 330B has a positive DC offset. Therefore, the offset signal (e.g., offset command) is updated by the offset code calculation circuit 516B to decrease the DC offset of the comparator 330B. When the OS1_sign value is less than 0, the comparator 330B has a negative DC offset. Therefore, the offset signal (e.g., offset command) is updated by the offset code calculation circuit 516B to increase the DC offset of the comparator 330B. In some embodiments, the adder 604B may be positioned between the accumulator 606B and the offset code calculation circuit 516B.

[0093] refer to Figure 8 In some embodiments, the calibration engine 800 is configured as a DC offset calibration engine, and outputs from input 802 to output port 322 ( Figure 3 ) Receives output data Dout[M-1:0]. Calibration engine 800 can be used as calibration engine 390 ( Figure 3 In some embodiments, the calibration engine 800 and the following schemes calibrate the DC offset of comparator 330A, comparator 330B, or both comparators 330A and 330B (e.g., as referenced above). Figure 5 , 6 Used after (as described in 7).

[0094] The calibration engine 800 can employ a method to calibrate the DC offset difference between comparators 330A and 330B in the foreground or background, and provides offset correction codes at output 832 for comparators 330A and / or 330B respectively for input 392A. Figure 3 The comparator 330B receives data at input 392B and input 392B at input 392B. In some embodiments, the comparator 330B ( Figure 3The calibration engine 800 generates the last valid bits ([M-1:0] bits). In some embodiments, the calibration engine 800 includes an adder 804, an averaging circuit or accumulator 806, a comparator 812 and an offset code calculation circuit 816, and uses the last valid bits ([M-1:0] bits) to extract the offset difference between comparators 330A and 330B.

[0095] Accumulator 806 is coupled to the non-inverting input of offset code calculation circuit 816 and comparator 812. The last bit of data output Dout[M-1:0] is received at input 802 as a range from 0 to 2. M-1 The value of the data output Dout[M-1:0] is subtracted from the value of 2 provided at input 807 of adder 804 in adder 804. (M-1) -0.5. The result range is from -(2 (M-1) -0.5) to 2 (M -1) -0.5, the average is 0. The range is from -(2 ^M-1) -0.5 to 2 (M-1) The result of -0.5 is provided to accumulator 806 (e.g., averaging circuit). For the averaging circuit implementation, Dout[M-1:0]-(2 (M-1) -0.5) accumulated K times (where K is an integer (e.g., 5, 10, 20, 50, 100, etc.)). In some embodiments, the average value is calculated at output 822 as OSD12 = ∑(Dout[M-1:0]-(2 (M-1) -0.5)) / K. For accumulator operations, Dout[M-1]-0.5 is added continuously and the accumulator output OSD12 value is equal to ∑(μ*(Dout[M-1:0]-(2 (M-1) -0.5))) gives the average value, where in some embodiments μ is a coefficient that defines the accumulator bandwidth.

[0096] At the inverting input of comparator 652, the amplitude of OSD12 is compared with the preset target threshold D. th Compare them. If the absolute value of OSD12 (|OSD12|) is less than the threshold D th Therefore, the DC offset difference between comparators 330A and 330B is very small (e.g., less than several hundred microvolts) and does not require updating. Threshold D thThis can be a fixed value, representing a small or insignificant difference between the DC offsets of comparators 330A and 330B. If the absolute value of OSD12 is greater than the threshold Dth, then the DC offset difference is too large and an offset code update is required. Comparator 652 provides a control signal to the offset code calculation circuit 816, indicating that an update is needed. If the value of OSD12 is greater than 0, then the offset of comparator 330B is greater than the offset of comparator 330A, and the offset code calculation circuit increases the offset of comparator 330B or decreases the offset of comparator 330A. If the value of OSD12 is less than zero, then the offset of comparator 330B is less than the offset of comparator 330A, and the offset code calculation circuit 816 decreases the offset of comparator 330B or increases the offset of comparator 330A. In some embodiments, adder 804 may be positioned between accumulator 806 and offset code calculation circuit 816.

[0097] It should be noted that certain paragraphs of this disclosure may refer to terms related to subsets of transport spatial streams, probe frames, responses, and means, such as "first" and "second," to identify or distinguish them from each other. These terms are not intended to associate entities (e.g., first means and second means) merely temporally or sequentially, but in some cases, these entities may include this relationship. These terms also do not limit the number of possible entities that can operate in the system or environment. It should be understood that the described system may provide any or one of these components and these components may be provided on a standalone machine, or in some embodiments, on multiple machines in a distributed system. Furthermore, the described system and methods may be provided as one or more computer-readable programs or executable instructions embodied in or on one or more articles of art, such as floppy disks, hard disks, CD-ROMs, flash memory cards, PROMs, RAMs, ROMs, or magnetic tapes. The program may be implemented in any programming language, such as LISP, PERL, C, C++, C#, or any bytecode language, such as JAVA. Software programs or executable instructions may be stored as object code on or in one or more artifacts.

[0098] While the foregoing written description of the methods and systems enables those skilled in the art to make and use embodiments thereof, those skilled in the art will understand and appreciate the existence of variations, combinations, and equivalents of the specific embodiments, methods, and examples described herein. Therefore, the methods and systems should not be limited to the foregoing embodiments, methods, and examples, but rather to all embodiments and methods within the scope and spirit of this disclosure.

Claims

1. An apparatus comprising: The sampling and digital-to-analog converter (DAC) circuit is used to sample the input voltage to obtain a first sample voltage. A first comparator is coupled to the sampling and DAC circuit; A first set of storage circuitry, coupled to the first comparator and the sampling and DAC circuitry, is configured to store a first subset of bits corresponding to the input voltage. A second comparator is coupled to the sampling and DAC circuit. A second set of storage circuitry, coupled to the second comparator and the sampling and DAC circuitry, is configured to store a second subset of the plurality of bits corresponding to the input voltage; and A calibration circuit configured to receive a first bit from a first memory cell of the first set of memory circuits and several bits from the first set of memory circuits and the second set of memory circuits, wherein the calibration circuit is configured to provide a first offset signal to control a first offset associated with the first comparator and to provide a second offset signal to control a second offset associated with the second comparator.

2. The apparatus of claim 1, wherein the first comparator has a faster detection speed than the second comparator, and wherein the second comparator has higher sensitivity than the first comparator.

3. The apparatus according to claim 1, wherein the first bit is the most significant bit.

4. The apparatus of claim 1, wherein the plurality of bits comprises all the bits of the first group of storage circuits and the second group of storage circuits.

5. The apparatus of claim 1, wherein the calibration circuit includes a first averaging circuit configured to receive the first bit and a second averaging circuit configured to receive the plurality of bits.

6. The apparatus of claim 5, wherein the first offset code calculation circuit is coupled to the first averaging circuit and the second offset code calculation circuit is coupled to the second averaging circuit.

7. The apparatus of claim 5, wherein the first averaging circuit is an accumulator.

8. The apparatus of claim 1, wherein the apparatus is disposed in an integrated circuit package.

9. The apparatus of claim 1, wherein the output of the first comparator is directly coupled to the input port of the first set of storage circuits, and wherein the output of the second comparator is directly coupled to the input port of the second set of storage circuits.

10. An apparatus comprising: The sampling and digital-to-analog converter (DAC) circuit is used to sample the input voltage to obtain a first sample voltage. A first comparator is coupled to the sampling and DAC circuit; A first set of storage circuitry, coupled to the first comparator and the sampling and DAC circuitry, is configured to store a first subset of bits corresponding to the input voltage. A second comparator is coupled to the sampling and DAC circuit. A second set of storage circuitry, coupled to the second comparator and the sampling and DAC circuitry, is configured to store a second subset of the plurality of bits corresponding to the input voltage; and A calibration circuit configured to receive a second subset of the plurality of bits corresponding to the input voltage and to accumulate or average the second subset of the plurality of bits corresponding to the input voltage, wherein the calibration circuit is configured to provide a first offset signal to control a first offset associated with the first comparator or to provide a second offset signal to control a second offset associated with the second comparator, wherein the calibration circuit is configured to update the first offset signal or the second offset signal when the average value of the second subset of the plurality of bits is higher than a threshold.

11. The apparatus of claim 10, wherein the first comparator has a faster detection speed than the second comparator, and wherein the second comparator has higher sensitivity than the first comparator.

12. The apparatus of claim 10, wherein the calibration circuit includes a third comparator that receives the average value and the threshold.

13. The apparatus of claim 10, wherein the second subset of the bits comprises all the bits of the second set of storage circuits.

14. The apparatus of claim 10, wherein the calibration circuit includes an adder.

15. The apparatus of claim 10, wherein the apparatus is disposed in an integrated circuit package.

16. A method comprising: The input voltage is sampled by a sampling and digital-to-analog converter (DAC) circuit to obtain the first sampled voltage; A first comparator coupled to the first set of storage circuitry determines the state of the first bit among a plurality of bits corresponding to the input voltage based on the first sampled voltage; The input voltage is sampled by the sampling and DAC circuit to obtain a second sampled voltage; A second comparator coupled to a second set of storage circuits different from the first set of storage circuits determines the state of the second bit among the plurality of bits based on the second sampling voltage; Average the first number of units digits from the first group of storage circuits and the second number of units digits from the first group of storage circuits and the second group of storage circuits; and A first offset signal is provided in response to the average of the first number of said bits to control a first offset associated with the first comparator, and a second offset signal is provided in response to the second number of said bits to control a second offset associated with the second comparator to reduce the offset difference.

17. The method of claim 16, wherein the first number of bits are the most significant bits.

18. The method of claim 17, wherein the second number of bits comprises all the bits of the first group of storage circuits and the second group of storage circuits.

19. The method of claim 17, further comprising: The determined state of the first bit is stored in one of the corresponding circuits in the first group; and The determined state of the second bit is stored in one of the corresponding circuits in the second group.

20. The method of claim 19, wherein sampling the input voltage by the sampling and DAC circuit to obtain the second sampled voltage is at least partially based on the determined state of the first bit stored by one of the corresponding bits in the first set of storage circuits.

Images