PCIe switch testing method, system and FPGA device based on PIPE interface

Abstract

The present invention provides a test method, system and FPGA device for a PCIe switch based on a PIPE interface. The present invention implements a mature solution of CPU plus RC through a PC, and can directly support most EP drivers using a window system; the psb for ep module and the psb for rp module of the FPGA device are used to reduce and increase the speed, thereby realizing a complete path from the PC to the EP and achieving the function of testing the psb for rp module. Compared with the traditional architecture of implementing CPU plus RC in an FPGA, the present invention reduces the number of developers, shortens the development cycle, saves funds for purchasing corresponding IPs, reduces the links in the debugging process, and further improves the test efficiency. The mature drivers on the windows system can be used to reduce the time and manpower required for repeated development of drivers for different EPs.

Description

Technical Field

[0001] The present invention relates to the field of data processing, and in particular to a test method, system and FPGA device for a PCIe switch based on a PIPE interface. Background Art

[0002] PCI-Express (peripheral component interconnect express) is a high-speed serial computer expansion bus standard. It was proposed by Intel in 2001 and has been widely used in various fields. In the PCIe structure, there may be a clock frequency difference between the RC (Root Complex) external interface RP (Root Port) and the peripheral device End Point (EP) according to the needs, so that there is a rate difference between the two and they cannot communicate normally. In this case, it is necessary to add a PCIeSpeed ​​Bridge (PSB) between the two to convert the low-speed signal to the standard rate so that communication can be normal. Its structure is as follows Figure 1 PSB can be implemented as part of the switch function in the PCIe architecture. Figure 2 As shown in the figure, when the CPU and RC work at a low rate caused by the low-speed clock domain, and the PCIe EP works at the standard rate, channels 2 and 3 cannot communicate normally. After the switch in channel 1 implements PSB, they can communicate normally.

[0003] After using FPGA to implement the switch code and completing the corresponding RTL and simulation work, it is necessary to build a corresponding hardware test environment for further verification. Figure 1 The difficulties of CPU, RC, Memory, switch and EP are as follows:

[0004] 1. FPGA hard core is needed to realize CPU function, separate software development is required, different driver software needs to be developed for different EPs, and CPU and RC direct interface code development is required.

[0005] 2.FPGA requires an RC soft core, which can be developed independently or purchased from a mature IP.

[0006] 3. It is necessary to develop interfaces between CPU and RC, and between RC and switch in FPGA, implement RC’s read and write scheduling of memory through CPU, and simulate and debug successfully.

[0007] 4. A complete set of test scripts needs to be formed based on the developed software to realize the CPU initialization and simple configuration functions of RC and EP.

[0008] The test platform implemented by the above traditional method requires a lot of manpower for development and debugging, the funds required to purchase the corresponding IP are very high, and the development time is very long. Summary of the invention

[0009] In view of the above-mentioned shortcomings of the prior art, the purpose of the present invention is to provide a test method, system and FPGA device for a PCIe switch based on a PIPE interface, so as to solve the above-mentioned problems of the prior art.

[0010] To achieve the above-mentioned purpose and other related purposes, the present invention provides a test system for a PCIe switch based on a PIPE interface, the system comprising: a PC device, an FPGA device and an EP device; wherein the FPGA device is connected to the PC device and comprises: a psb for ep module and a psb for rp module; the FPGA device is used to convert a PHY signal from the PC device into a standard-rate PIPE interface signal through a PCIe PHY IP core, and reduce the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module, and then increase the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module, and send it to the EP device.

[0011] In one embodiment of the present invention, the PC device is connected to the FPGA development board of the FPGA device via a PCIe slot using an adapter board.

[0012] In one embodiment of the present invention, the psb for ep module and the psb for rp module are connected via a low-speed PIPE interface.

[0013] In one embodiment of the present invention, a logic analyzer is connected between the PCIe slot of the PC device and the adapter board to capture uplink and downlink data packets during PCIe communication.

[0014] In one embodiment of the present invention, the FPGA device further includes: a PHY interface for PHY signals from a PC device.

[0015] In one embodiment of the present invention, the FPGA device is connected to the EP device via a PCIe expansion board.

[0016] In one embodiment of the present invention, the PC device is installed with Windows 10 system.

[0017] To achieve the above-mentioned purpose and other related purposes, the present invention provides a test method for a PCIe switch based on a PIPE interface, the method comprising: a PC device sends a PHY signal to an FPGA device connected to the PC device via a PCIe slot using an adapter board; the FPGA device converts the PHY signal from the PC device into a standard-rate PIPE interface signal through a PCIe PHY IP core, and reduces the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through a psb for ep module of the FPGA device, and then increases the speed of the low-speed PIPE signal to a standard-rate PIPE signal through a psb for rp module of the FPGA device; and sends the standard-rate PIPE signal to the EP device through the FPGA device.

[0018] In one embodiment of the present invention, the psb for ep module and the psb for rp module are connected via a low-speed PIPE interface.

[0019] To achieve the above-mentioned purpose and other related purposes, the present invention provides an FPGA device, including: a psb for ep module and a psb for rp module; the FPGA device is used to convert the PHY signal from the PC device into a standard-rate PIPE interface signal through the PCIe PHY IP core, and reduce the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module, and then increase the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module, and send it to the EP device.

[0020] As described above, the present invention is a test method, system and FPGA device for PCIe switch based on PIPE interface, which has the following beneficial effects: the present invention implements a mature solution of CPU plus RC through PC, and can directly support most EP drivers using the window system; the psb for ep module and the psb for rp module of the FPGA device are used to reduce and increase the speed, so as to realize a complete path from PC to EP and achieve the function of testing the psb for rp module. Compared with the traditional architecture of implementing CPU plus RC in FPGA, the present invention reduces the number of developers, shortens the development cycle, saves funds for purchasing corresponding IP, reduces the links in the debugging process, and further improves the test efficiency. The mature drivers on the windows system can be used to reduce the time and manpower required for repeated development of drivers for different EPs. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1It shows a schematic diagram of the communication between the existing RC device and the peripheral device.

[0022] Figure 2 Shown is a schematic diagram of implementing PSB communication with an existing PCIe switch.

[0023] Figure 3 Shown is a structural schematic diagram of a test system for a PCIe switch based on a PIPE interface in an embodiment of the present invention.

[0024] Figure 4 Shown is a structural schematic diagram of a test system for a PCIe switch based on a PIPE interface in an embodiment of the present invention.

[0025] Figure 5 Shown is a test environment connection diagram of a PCIe switch based on a PIPE interface in an embodiment of the present invention.

[0026] Figure 6 Shown is a flowchart of a method for testing a PCIe switch based on a PIPE interface in an embodiment of the present invention.

[0027] Figure 7 Shown is a schematic diagram of the structure of an FPGA device in an embodiment of the present invention. DETAILED DESCRIPTION

[0028] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the following embodiments and features in the embodiments can be combined with each other without conflict.

[0029] It should be noted that in the following description, reference is made to the accompanying drawings, which describe several embodiments of the present invention. It should be understood that other embodiments may also be used, and that mechanical composition, structural, electrical and operational changes may be made without departing from the spirit and scope of the present invention. The following detailed description should not be considered restrictive, and the scope of the embodiments of the present invention is limited only by the claims of the published patents. The terms used herein are only for describing specific embodiments and are not intended to limit the present invention. Spatially related terms, such as "upper", "lower", "left", "right", "below", "below", "lower", "above", "upper", etc., may be used in the text to facilitate the description of the relationship between an element or feature shown in the figure and another element or feature.

[0030] Throughout the specification, when a part is said to be "connected" to another part, this includes not only the case of "direct connection" but also the case of "indirect connection" by placing other elements therebetween. In addition, when a part is said to "include" a certain constituent element, unless otherwise stated, it does not exclude other constituent elements, but means that other constituent elements may be included.

[0031] The terms first, second and third mentioned herein are used to describe various parts, components, regions, layers and / or segments, but are not limited thereto. These terms are only used to distinguish a certain part, component, region, layer or segment from other parts, components, regions, layers or segments. Therefore, the first part, component, region, layer or segment described below may refer to the second part, component, region, layer or segment within the scope of the present invention.

[0032] Furthermore, as used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless there is an indication to the contrary in the context. It should be further understood that the terms "comprise", "include" indicate the presence of the described features, operations, elements, components, items, kinds, and / or groups, but do not exclude the presence, occurrence or addition of one or more other features, operations, elements, components, items, kinds, and / or groups. The terms "or" and "and / or" used herein are interpreted as inclusive, or mean any one or any combination. Therefore, "A, B or C" or "A, B and / or C" means "any of the following: A; B; C; A and B; A and C; B and C; A, B and C". Exceptions to this definition will only occur when the combination of elements, functions or operations is inherently mutually exclusive in some way.

[0033] The present invention discloses a test method for a PCIe switch based on a PIPE interface, which realizes a mature solution of CPU plus RC through a PC, and can directly support most EP drivers using a window system; the psb forep module and the psb for rp module of an FPGA device are used to reduce and increase the speed, thereby realizing a complete path from the PC to the EP and achieving the function of testing the psb for rp module. Compared with the traditional architecture of realizing CPU plus RC in an FPGA, the present invention reduces the number of developers, shortens the development cycle, saves funds for purchasing corresponding IPs, reduces the links in the debugging process, and further improves the test efficiency. The mature drivers on the windows system can be used to reduce the time and manpower required for repeated development of drivers for different EPs.

[0034] The following is a detailed description of the embodiments of the present invention with reference to the accompanying drawings so that those skilled in the art can easily implement the present invention. The present invention can be embodied in many different forms and is not limited to the embodiments described herein.

[0035] like Figure 3 A structural schematic diagram of a PCIe switch test system based on a PIPE interface in an embodiment of the present invention is shown.

[0036] The system comprises:

[0037] PC device 1, FPGA device 2 and EP device 3;

[0038] The PC device 1 is a desktop computer or server, which is a standard PCIe device and can provide a PCIe interface; the PC is installed with a Windows system, which can directly support most EP drivers. Preferably, the PC device 1 is installed with a Windows 10 system, which can provide a stable and reliable EP-side driver, and the SSD, graphics card, and USB flash drive used in the test can all have built-in corresponding drivers.

[0039] The FPGA device 2 is connected to the PC device 1 and includes: a psb for ep module 21 and a psb for rp module 22; the psb for rp module is a PSB module to be tested. The psb for ep module 21 is similar in structure to the psb for rp module 22.

[0040] The FPGA device 3 is used to convert the PHY signal from the PC device into a standard-rate PIPE interface signal through the PCIe PHY IP core, and reduce the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module 21, and then increase the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module 22, and send it to the EP device 3.

[0041] It should be noted that since most systems are implemented inside the FPGA device, the debug methods in the FPGA, such as VIO, lia, etc., can be used to observe the interactive data in the PCIe protocol and quickly locate the problems in the psb for rp module. The external protocol analyzer hardware can also be used to analyze the PCIe interactive data packets to locate the problems in the PSB.

[0042] The combination of PC device 1 and psb for ep module 21 realizes low-speed RP. The psb for ep module 21 is similar in structure to the psb forrp module 22, has a shorter development cycle, saves manpower time and capital costs in the realization of the entire test environment, and can further reduce debugging time costs due to the reduced system complexity.

[0043] In a specific embodiment, the psb for ep module 21 includes: a high-speed input port and a low-speed output port; that is, the high-speed input port inputs a PIPE interface signal of a standard rate, and the low-speed output port outputs a reduced-speed low-speed PIPE signal; the psb for rp module 22 includes: a low-speed input port and a high-speed output port; that is, the low-speed input port inputs a low-speed PIPE interface signal, and the high-speed output port outputs a standard-speed PIPE signal of a raised rate;

[0044] In one embodiment, the PC device 1 is connected to the FPGA device 2 via a PCIe slot using an adapter board. That is, the PC device 1 is connected to the FPGA development board of the FPGA device 2 via a PCIe slot on a PC motherboard using an adapter board.

[0045] In one embodiment, the FPGA device 2 further includes: a PHY interface for a PHY signal of a standard rate from the PC device 1, so as to achieve connection to the PC device 1 through the PHY interface using a psb for ep module.

[0046] In one embodiment, the psb for ep module 21 and the psb for rp module 22 are connected via a low-speed PIPE interface.

[0047] In one embodiment, a logic analyzer is connected between the PCIe slot of the PC device 1 and the adapter board to capture uplink and downlink data packets during PCIe communication.

[0048] In one embodiment, if Figure 3 As shown, the FPGA device is connected to the EP device via a PCIe expansion board 4. Specifically, the PCIe expansion board can be connected to different EP devices.

[0049] In order to better illustrate the above-mentioned PCIe switch test system based on the PIPE interface, the present invention provides the following specific embodiments.

[0050] Embodiment 1: A test system for a PCIe switch based on a PIPE interface. Figure 4 This is a test system framework diagram of the PCIe switch in this embodiment based on the PIPE interface.

[0051] The system includes: PC, FPGA, PCIe expansion board and EP. PC is a desktop computer or server, which is a standard PCIe device and can provide a PCIe interface. PC is installed with Windows 10 system, which can provide a stable and reliable EP-side driver. The SSD, graphics card and USB flash drive used in the test can all have built-in corresponding drivers. Through the PCIe slot on the PC motherboard, the FPGA development board connected by the adapter board is used to convert the PHY signal input from the PC into a standard-rate PIPE interface signal through the PCIe PHY IP core in the FPGA, and connect it to the psb for ep module in the FPGA. After the speed reduction processing, the low-speed PIPE signal is connected to the psbfor rp module, and the speed is increased to the standard-rate PIPE signal. The signal can then be connected to different EPs through the PCIe expansion board to realize a complete path from PC to EP. A logic analyzer can be connected between the PCIe and the adapter board of the PC to capture the upstream and downstream data packets during PCIe communication, such as Figure 5 This system can be used to test the psb for rp module.

[0052] Similar to the principle of the above embodiment, the present invention provides a test method for a PCIe switch based on a PIPE interface.

[0053] The following provides specific embodiments in conjunction with the accompanying drawings:

[0054] like Figure 6 A flowchart of a method for testing a PCIe switch based on a PIPE interface in an embodiment of the present invention is shown.

[0055] The method comprises:

[0056] Step S1: A PC device sends a PHY signal to an FPGA device connected to the PC device via a PCIe slot using an adapter board.

[0057] In one embodiment, the PC device is connected to the FPGA development board of the FPGA device via a PCIe slot using an adapter board to connect to the FPGA device.

[0058] Step S2: The FPGA device converts the PHY signal from the PC device into a standard-rate PIPE interface signal through the PCIe PHY IP core, and reduces the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module of the FPGA device, and then increases the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module of the FPGA device.

[0059] Step S3: Sending the PIPE signal of the standard rate to the EP device through the FPGA device.

[0060] In one embodiment, the psb for ep module and the psb for rp module are connected via a low-speed PIPE interface.

[0061] In one embodiment, a logic analyzer is connected between the PCIe slot of the PC device and the adapter board to capture uplink and downlink data packets during PCIe communication.

[0062] In one embodiment, the FPGA device further includes: a PHY interface for PHY signals from a PC device.

[0063] In one embodiment, the FPGA device is connected to the EP device via a PCIe expansion board.

[0064] In one embodiment, the PC device is installed with Windows 10 system.

[0065] like Figure 7 A schematic diagram showing the structure of an FPGA device in an embodiment of the present invention is shown.

[0066] The structure and function of the FPGA device in this embodiment are similar to those of the FPGA device mentioned in the above embodiments, so they will not be described in detail here.

[0067] The FPGA device includes: a psb for ep module 21 and a psb for rp module 22;

[0068] The FPGA device is used to convert the PHY signal from the PC device into a standard-rate PIPE interface signal through the PCIe PHY IP core, and reduce the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module 21, and then increase the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module 22, and send it to the EP device.

[0069] In summary, the test method, system and FPGA device of the PCIe switch based on the PIPE interface of the present invention realize the mature solution of CPU plus RC through PC, and can directly support most EP drivers by using the window system; the psb for ep module and the psb for rp module of the FPGA device are used to reduce and increase the speed, so as to realize the complete path from PC to EP and achieve the function of testing the psb for rp module. Compared with the traditional architecture of realizing CPU plus RC in FPGA, the present invention reduces the number of developers, shortens the development cycle, saves the funds for purchasing the corresponding IP, reduces the links in the debugging process, and further improves the test efficiency. The mature drivers on the windows system can be used to reduce the time and manpower required for repeated development of drivers for different EPs. Therefore, the present invention effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0070] The above embodiments are merely illustrative of the principles and effects of the present invention, and are not intended to limit the present invention. Anyone familiar with the technology may modify or change the above embodiments without violating the spirit and scope of the present invention. Therefore, all equivalent modifications or changes made by a person of ordinary skill in the art without departing from the spirit and technical ideas disclosed by the present invention shall still be covered by the claims of the present invention.

Claims

1. A PCIe switch test system based on a PIPE interface, characterized in that: The system comprises: PC equipment, FPGA devices and EP equipment; Wherein, the FPGA device is connected to the PC device and includes: a psb for ep module and a psb for rp module; The PC device is connected to the FPGA development board of the FPGA device via a PCIe slot using an adapter board; The FPGA device is used to convert the PHY signal from the PC device into a standard-rate PIPE interface signal through the PCIe PHYIP core, and reduce the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module, and then increase the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module, and send it to the EP device.

2. According to the PCIe switch test system based on PIPE interface described in claim 1, it is characterized in that: The psb for ep module is connected to the psb for rp module via a low-speed PIPE interface.

3. The PCIe switch test system based on the PIPE interface according to claim 1, characterized in that: A logic analyzer is connected between the PCIe slot of the PC device and the adapter board to capture uplink and downlink data packets during PCIe communication.

4. The PCIe switch test system based on the PIPE interface according to claim 1, characterized in that: The FPGA device also includes: a PHY interface for PHY signals from a PC device.

5. The PCIe switch test system based on the PIPE interface according to claim 1, characterized in that: The FPGA device is connected to the EP device via a PCIe expansion board.

6. The PCIe switch test system based on PIPE interface according to claim 1, characterized in that: The PC device is installed with Windows 10 system.

7. A PCIe switch testing method based on a PIPE interface, characterized in that: The method comprises: The PC device sends a PHY signal to an FPGA device connected to the PC device via a PCIe slot using an adapter board; the PC device is connected to an FPGA development board of the FPGA device via a PCIe slot using an adapter board; The FPGA device converts the PHY signal from the PC device into a standard-rate PIPE interface signal through the PCIe PHY IP core, and reduces the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module of the FPGA device, and then increases the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module of the FPGA device; The PIPE signal of the standard rate is sent to the EP device through the FPGA device.

8. The method for testing a PCIe switch based on a PIPE interface according to claim 7, characterized in that: The psb for ep module is connected to the psb for rp module via a low-speed PIPE interface.

9. An FPGA device, characterized in that: include: psb for ep module and psb for rp module; The FPGA device is used to convert the PHY signal from the PC device into a standard-rate PIPE interface signal through the PCIe PHY IP core, and reduce the speed of the standard-rate PIPE interface signal to a low-speed PIPE signal through the psb for ep module, and then increase the speed of the low-speed PIPE signal to a standard-rate PIPE signal through the psb for rp module, and send it to the EP device; the PC device is connected to the FPGA development board of the FPGA device using an adapter board through the PCIe slot.

Images