A test fixture, device, method and storage medium for eMMC

Abstract

The present invention discloses a test fixture, device, method and storage medium of an eMMC, wherein the method comprises searching for a test probe connected to a test pin of an eMMC to be tested; when the test probe connected to the test pin of the eMMC is found, determining the coordinate position of the test probe; acquiring and detecting a test instruction carrying a lead-out mark; when it is detected that the test instruction carries a lead-out mark, according to the lead-out mark and the coordinate position of the test probe, controlling one or more controlled switches corresponding to the test probe, so that the NAND signal inside the eMMC is led out to the first pad corresponding to the lead-out mark on the PCB. The embodiment of the present invention can realize the test of the eMMC under the condition of exempting the welding process, so that the test fixture is no longer restricted by the set position of the test pin of the eMMC, improves the versatility and reusability of the test fixture, reduces the cost of chip testing, and can be widely used in the field of chip testing technology.

Description

Technical Field

[0001] The present invention relates to the field of eMMC testing technology, and in particular to an eMMC testing fixture, device, method and storage medium. Background Art

[0002] eMMC (Embedded Multi Media Card) is a standard for flash memory cards, which are mainly composed of flash memory, flash memory controller, and eMMC protocol interface, etc., and are packaged together in the form of BGA. The eMMC is provided with signal pins for transmitting eMMC signals. The eMMC signal refers to the control signal and data signal output by the flash memory controller to the outside. In order to facilitate the testing of the internal and output signals of the eMMC, when designing the eMMC, manufacturers usually reserve test pins on the eMMC for testing the eMMC and leading out its internal signals. The internal signal refers to the signal transmitted between the flash memory and the flash memory controller. Among them, the reserved positions of the test pins will be different depending on the manufacturer and the specifications of the eMMC. Currently, the common eMMC testing methods are generally divided into the following two methods:

[0003] The first method is to make a PCB (Printed Circuit Board) for testing, place pads on the PCB at the corresponding positions of the test pins and signal pins of the eMMC, and solder the test pins and signal pins of the eMMC to the pads of the PCB to lead out the signals of the eMMC, thereby testing the eMMC. This method requires operations such as ball planting and welding on the eMMC. The eMMC will be affected by high temperatures during ball planting and welding. The high temperature environment will cause the data stored in the eMMC to be lost or invalid, and in severe cases, its internal components will be damaged.

[0004] The second method is to make a PCB and a test fixture for testing, wherein the test fixture is provided with a plurality of probes corresponding to the signal pins and reserved test pins of the eMMC. Pads are placed on the corresponding positions of the PCB and the test pins and signal pins of the eMMC, and the signal pins and test pins of the eMMC are connected to the pads of the PCB through probes to lead out the signals of the eMMC, thereby realizing the test of the eMMC. However, the probes corresponding to the reserved test pins on the test fixture usually need to be set according to the positions of the test pins of the eMMC, and the settings of the test pins of the eMMC vary depending on the manufacturer and the specifications of the eMMC. If the eMMC test is completed in this way, it is necessary to customize the test fixture corresponding to the test pins of the eMMC. The production of the test fixture is time-consuming and costly, resulting in increased testing costs.

[0005] The above technical problems need to be solved urgently. Summary of the invention

[0006] The purpose of the present invention is to solve one of the technical problems existing in the prior art to at least a certain extent.

[0007] To this end, an object of the present invention is to provide a test fixture, device, method and storage medium for eMMC.

[0008] In order to achieve the above technical objectives, the technical solutions adopted by the embodiments of the present invention include:

[0009] On the one hand, an embodiment of the present invention provides a test fixture for eMMC, including:

[0010] A base, comprising a bottom plate and a selection circuit arranged in the bottom plate, wherein the selection circuit comprises a plurality of controlled switches and a controller, and control ends of the plurality of controlled switches are all connected to the controller;

[0011] A top plate, which is arranged opposite to the base and fixed to each other, and a side of the top plate away from the base is used for placing the eMMC to be tested;

[0012] A plurality of selection probes are arranged on a side of the bottom plate away from the top plate and vertically extend into the bottom plate, each of the selection probes corresponds to one or more of the controlled switches, and the plurality of selection probes also correspond one-to-one to a plurality of first pads of an external test circuit board, one end of each of the selection probes is connected to a first switch end of the corresponding one or more controlled switches, and the other end of each of the selection probes is used to contact the corresponding first pad;

[0013] A plurality of signal probes are arranged in the center of the bottom plate, the plurality of signal probes are arranged in a rectangular shape, and the plurality of signal probes correspond one by one to the plurality of second pads of the test circuit board; wherein one end of each of the signal probes passes through the bottom plate and extends out of a side of the bottom plate away from the top plate, one end of each of the signal probes is used to contact the corresponding second pad, the other end of each of the signal probes passes through the top plate and extends out of a surface of a side of the top plate away from the bottom plate, and the other end of each of the signal probes is used to connect to the signal pin of the eMMC to be tested;

[0014] A plurality of test probes are arranged on a side of the bottom plate close to the top plate and vertically extend into the bottom plate, the plurality of test probes are arranged around the plurality of signal probes, and the plurality of test probes are arranged in a rectangular shape, the spacing between two adjacent test probes is equal, and each of the test probes corresponds to one or more controlled switches; wherein one end of each of the test probes is connected to the second switch end of the corresponding one or more controlled switches, the other end of each of the test probes passes through the top plate and extends out of the surface of the top plate away from the bottom plate, and the other end of each of the test probes is used to connect to the test pin of the eMMC to be tested.

[0015] In addition, the eMMC test fixture according to the above embodiment of the present invention may also have the following additional technical features:

[0016] Furthermore, in one embodiment of the present invention, the eMMC to be tested adopts BGA153 packaging.

[0017] Further, in one embodiment of the present invention, the controlled switch includes any one of a triode, a field effect transistor, a relay or an IGBT.

[0018] Furthermore, in one embodiment of the present invention, the position of the signal probe satisfies the pin position specified by the eMMC protocol.

[0019] Further, in one embodiment of the present invention, the number of the test probes is greater than the number of the selection probes.

[0020] On the other hand, an embodiment of the present invention proposes a test device for an eMMC, comprising a test fixture for an eMMC and a test circuit board, wherein a plurality of first solder pads and second solder pads are arranged on the test circuit board, wherein the first solder pads are connected to an analog integrated circuit, wherein the first solder pads are used to lead out signals between a flash memory and a flash memory controller inside the eMMC to be tested to the analog integrated circuit, and wherein the analog integrated circuit is used to test the eMMC to be tested according to the signals between the flash memory and the flash memory controller; and the second solder pads are used to lead out control signals and / or data signals of the flash memory controller inside the eMMC to be tested.

[0021] In addition, the eMMC test device according to the above embodiment of the present invention may also have the following additional technical features:

[0022] Furthermore, in one embodiment of the present invention, the test circuit board adopts BGA153 packaging.

[0023] On the other hand, an embodiment of the present invention provides a method for testing an eMMC, comprising the following steps:

[0024] Find the test probe connected to the test pin of the eMMC to be tested;

[0025] When a test probe connected to a test pin of the eMMC to be tested is found, a coordinate position of the test probe is determined;

[0026] Acquire and detect a test instruction, wherein the test instruction carries a lead-out identifier, and the lead-out identifier is defined as a coordinate position of a first pad on a test circuit board for leading out a signal between a flash memory and a flash memory controller inside an eMMC to be tested;

[0027] When it is detected that the test instruction carries a lead-out identifier, one or more controlled switches corresponding to the test probe are controlled according to the lead-out identifier and the coordinate position of the test probe, so that the signal between the flash memory inside the eMMC to be tested and the flash memory controller is led out from its test pin to the first pad on the test circuit board corresponding to the lead-out identifier.

[0028] In addition, the eMMC testing method according to the above embodiment of the present invention may also have the following additional technical features:

[0029] Further, in one embodiment of the present invention, controlling one or more controlled switches corresponding to the test probe according to the lead-out mark and the coordinate position of the test probe includes:

[0030] Determining one or more selection probes mapped by the test probe according to the coordinate position of the test probe, and determining the coordinate positions of the mapped one or more selection probes;

[0031] Matching the mapped coordinate positions of one or more selection probes with the extraction identifier to obtain the selection probe matching the extraction identifier;

[0032] Determine a controlled switch group according to the coordinate position of the selection probe matched with the lead-out identifier and the coordinate position of the test probe, wherein the controlled switch group includes a controlled switch connecting the selection probe matched with the lead-out identifier and the test probe, and the controlled switch group also includes a controlled switch connecting the test probe with other selection probes mapped thereto;

[0033] The controlled switch connecting the selection probe and the test probe matching the lead-out identifier is controlled to be turned on, while the controlled switch connecting the test probe and other selection probes mapped thereto remains closed, so that the test circuit board leads out the signal between the flash memory inside the eMMC and the flash memory controller.

[0034] On the other hand, an embodiment of the present invention provides a storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to implement the above-mentioned eMMC test method.

[0035] The embodiments of the present invention provide a test fixture, device, method and storage medium for eMMC, so that the test fixture is no longer restricted by the set position of the test pin of the eMMC, the versatility and reusability of the test fixture are improved, and the degree of adaptability to the eMMC is enhanced, the application scenarios of the test fixture are broadened, and the test of the eMMC can be completed at low cost and high efficiency without welding, thus avoiding the loss of internal data of the eMMC due to welding. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the embodiments of the present invention or the drawings of related technical solutions in the prior art are introduced below. It should be understood that the drawings introduced below are only for the convenience of clearly describing some embodiments of the technical solutions of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0037] Figure 1 A schematic diagram of the structure of an eMMC testing device provided in one embodiment of the present application;

[0038] Figure 2 A signal definition diagram of an eMMC packaged in BGA153 provided for one embodiment of the present application;

[0039] Figure 3 A schematic diagram of the structure of a test fixture provided for one embodiment of the present application;

[0040] Figure 4 A schematic diagram of a side of a bottom plate away from a top plate provided for one embodiment of the present application;

[0041] Figure 5 A schematic diagram of a side of a bottom plate close to a top plate provided for one embodiment of the present application;

[0042] Figure 6 A schematic diagram of a selection circuit provided for one embodiment of the present application;

[0043] Figure 7 A flowchart of a method for testing an eMMC is provided for one embodiment of the present application. DETAILED DESCRIPTION

[0044] The embodiments of the present invention are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present invention, and are not to be construed as limitations of the present invention. For the step numbers in the following embodiments, they are only provided for the convenience of explanation, and the order between the steps is not limited in any way, and the execution order of each step in the embodiment can be adaptively adjusted according to the understanding of those skilled in the art.

[0045] eMMC (Embedded Multi Media Card) is a standard for flash memory cards, which defines the physical architecture, access interface and protocol of storage systems based on embedded multimedia cards. The interior of eMMC is mainly composed of flash memory, flash memory controller and eMMC protocol interface, which are packaged together in the form of BGA. The eMMC is provided with signal pins for transmitting eMMC signals, which are also called particle pins. The eMMC signal refers to the control signal and data signal output by the flash memory controller to the outside.

[0046] The signal transmitted between the flash memory and the flash memory controller inside the eMMC is an internal signal, namely a NAND signal, and the communication between the flash memory and the flash memory controller follows the NAND protocol. After the manufacturer has completed the packaging of the eMMC particle pins, it is necessary to measure and evaluate the quality of its internal NAND signals according to the NAND protocol. In order to facilitate the testing of the internal and output signals of the eMMC, when designing the eMMC, the manufacturer usually reserves a test pin on the eMMC for testing the eMMC and leading out its internal signals, namely a testpin. The test pin can obtain and lead out the internal NAND signal of the eMMC during eMMC verification. Among them, the reserved position of the test pin will be different depending on the manufacturer and the specifications of the eMMC.

[0047] Currently, the common eMMC testing methods are usually divided into the following two methods:

[0048] The first method is to make a PCB (Printed Circuit Board) for testing, place pads on the PCB at the corresponding positions of the test pins and signal pins of the eMMC, and solder the test pins and signal pins of the eMMC to the pads of the PCB to lead out the signals of the eMMC. However, this method requires the eMMC to be balled and soldered, and the eMMC will be affected by high temperatures during balling and soldering. The high temperature environment will cause the data stored in the eMMC to be lost or invalid, and in severe cases, its internal components will be damaged.

[0049] The second method is to make a PCB and a test fixture for testing, place pads on the PCB at positions corresponding to the test pins and signal pins of the eMMC, and set multiple probes corresponding to the signal pins and reserved test pins of the eMMC on the test fixture. The signal pins and test pins of the eMMC are connected to the pads of the PCB through the probes to lead out the NAND signal and eMMC signal of the eMMC. This method eliminates the welding process and can lead out its NAND signal and eMMC signal without damaging the eMMC or causing it to lose internal data. However, the probes corresponding to the reserved test pins on the test fixture usually need to be set according to the position of the test pins of the eMMC, and the setting of the test pins of the eMMC varies depending on the manufacturer and the specifications of the eMMC. If the eMMC test is completed in this way, it is necessary to customize the test fixture corresponding to the test pins of the eMMC. The production of the test fixture is time-consuming and costly, resulting in increased testing costs.

[0050] In order to simplify the types of test fixtures on the market, reduce the test time and cost of eMMC, and overcome the defects of the prior art, the present application provides a test fixture, device, method and storage medium for eMMC, which improves the versatility and reusability of the test fixture, can complete the test of eMMC without welding, and avoids the loss of internal data of eMMC due to welding.

[0051] The following describes in detail a test fixture and a device for eMMC according to an embodiment of the present invention with reference to the accompanying drawings. First, a test device for eMMC according to an embodiment of the present invention and a test fixture included therein will be described with reference to the accompanying drawings.

[0052] Reference Figure 1 , the eMMC test device includes a test fixture 100 and a test circuit board 200 of the eMMC, and the test circuit board 200 is a PCB. The test fixture 100 is used to connect the eMMC to be tested and the test circuit board 200. A plurality of first pads and a plurality of second pads are arranged on the surface of the test circuit board 200. Among them, the first pad is connected to an external analog integrated circuit, and the first pad is used to lead the signal between the flash memory and the flash memory controller inside the eMMC, that is, the internal signal, to the analog integrated circuit, and the analog integrated circuit is used to obtain the internal signal of the eMMC and test the performance of the eMMC according to the internal signal of the eMMC. The second pad is used to lead the control signal and / or data signal of the eMMC to the test circuit board 200.

[0053] Reference Figure 2Optionally, the package of the test circuit board 200 uses a BGA153 package, which is a standard eMMC package. The layout of the first pad and the second pad both meet the pin layout of the BGA153 package. Specifically, the first pad is an NC pin pad of the test circuit board 200, and the NC pin pad is used to connect an analog integrated circuit. The second pad is a pin pad other than the NC pin pad, for example, a pin VSF pad, a pin RFU pad, a pin CLK pad, etc.

[0054] Optionally, the number of the first pads and the second pads is 153.

[0055] Reference Figures 3 to 5 The test fixture 100 is used to connect the eMMC to be tested and the test circuit board 200, and the test fixture 100 includes:

[0056] The base includes a bottom plate 110 and a selection circuit, and the selection circuit is arranged in the bottom plate 110. The selection circuit includes a plurality of controlled switches and a controller, and the control ends of the plurality of controlled switches are connected to the controller.

[0057] Optionally, the controlled switch includes any one of a triode, a field effect transistor, a relay or an IGBT. Among them, IGBT refers to an insulated gate bipolar transistor, which is a composite fully controlled voltage-driven power semiconductor device composed of a bipolar triode (Bipolar Junction Transistor, BJT) and an insulated gate field effect transistor (Metal-Oxide-Semiconductor, MOS), and has the advantages of both the high input impedance of the metal-oxide-semiconductor field effect transistor and the low on-state voltage drop of the power transistor.

[0058] It should be noted that the size of the base plate 110 is larger than the size of the patch frame of the BGA package. Optionally, the model of the BGA package is BGA153, and the size of the patch frame of the BGA153 package, that is, the package range, is 13 mm×11.5 mm.

[0059] The top plate 120 is arranged opposite to the base, and the top plate 120 and the base are fixed to each other. The side of the top plate 120 away from the base is used to place the eMMC to be tested. The size of the top plate 120 is the same as that of the base.

[0060] A plurality of selection probes 130 are provided on a side of the bottom plate 110 away from the top plate 120 and extend into the bottom plate 110, and the plurality of selection probes 130 are perpendicular to the bottom plate 110. Each selection probe 130 corresponds to one or more controlled switches, that is, the relationship between the selection probe 130 and the controlled switches is one-to-many. The plurality of selection probes 130 also correspond one-to-one to a plurality of first pads of the external test circuit board 200, that is, the relationship between the selection probe 130 and the first pads of the test circuit board 200 is one-to-one, and the test circuit board 200 is a PCB.

[0061] It should be noted that the first end of each selection probe 130 is connected to the first switch end of the corresponding controlled switch. The second end of each selection probe 130 is in contact with the corresponding first pad.

[0062] A plurality of signal probes 140 are arranged in a rectangular shape in the center of the base plate 110 and penetrate the base plate 110. The plurality of signal probes 140 correspond to the plurality of second pads of the test circuit board 200 one by one, that is, the relationship between the signal probes 140 and the second pads of the test circuit board 200 is one-to-one.

[0063] It should be noted that the first end of each signal probe 140 passes through the bottom plate 110 and extends out of the side of the bottom plate 110 away from the top plate 120, and the first end of each signal probe 140 is used to contact the second pad corresponding to it. The second end of each signal probe 140 passes through the top plate 120 and extends out of the surface of the top plate 120 away from the bottom plate 110, and the second end of each signal probe 140 is used to connect to the signal pin of the eMMC to be tested. It should be noted that the position of the signal probe 140 meets the pin position specified by the eMMC protocol, and multiple signal probes 140 are arranged in a rectangular shape.

[0064] Optionally, the number of the selection probes 130 and the signal probes 140 is 153, and the spacing between two adjacent selection probes 130 is the same as the spacing between two adjacent signal probes 140. At the same time, the spacing between one adjacent selection probe 130 and one signal probe 140 is also the same as the spacing between two adjacent signal probes 140. Optionally, the spacing between two adjacent signal probes 140 is 0.5 mm.

[0065] A plurality of test probes 150 are provided on a side of the bottom plate 110 close to the top plate 120, and the plurality of test probes 150 are vertically extended into the bottom plate 110. The plurality of test probes 150 are arranged in a rectangular shape on the bottom plate 110 and are arranged around the plurality of signal probes 140. Each test probe 150 corresponds to one or more controlled switches, that is, the corresponding relationship between the test probe 150 and the controlled switch is one-to-one or one-to-many.

[0066] Specifically, the first end of each test probe 150 is connected to the second switch end of the corresponding one or more controlled switches. The second end of each test probe 150 penetrates the top plate 120 and extends out of the surface of the top plate 120 away from the bottom plate 110. The second end of each test probe 150 is used to connect to the test pin of the eMMC to be tested.

[0067] Optionally, one test probe 150 corresponds to one or more selection probes 130 , one selection probe 130 corresponds to one or more test probes 150 , and one controlled switch connects one selection probe 130 and one test probe 150 , respectively.

[0068] Optionally, each test probe 150 may correspond to a plurality of identical selection probes 130 , and different selection probes 130 may correspond to the same test probe 150 .

[0069] It should be noted that the spacing between two adjacent test probes 150 is equal. Optionally, the spacing between two adjacent test probes 150 is 0.5 mm. When the spacing between two adjacent test probes 150 is 0.5 mm, the number of test probes 150 is 332. In other embodiments of the present invention, the spacing between two adjacent test probes 150 can be determined according to actual conditions, and the present application does not make specific limitations on this. In addition, when the spacing between two adjacent test probes 150 changes, the number of test probes 150 will also change, and the arrangement of multiple test probes 150 on the base plate 110 will also change accordingly. Therefore, the effect of changing the arrangement of multiple test probes 150 on the base plate 110 can be achieved by changing the spacing between two adjacent test probes 150.

[0070] In this specific embodiment, the outermost part of the plurality of signal probes 140 is used as a reference, and a test probe 150 is arranged at a certain distance until the package range of the BGA 153 is fully covered with the test probes 150. That is, the plurality of test probes 150 can surround the plurality of signal probes 140 and be arranged at equal distances within the package range of the BGA 153. It should be emphasized that the number of the test probes 150 must be greater than the number of the selection probes 130, that is, the number of the test probes 150 is several times the number of the selection probes 130.

[0071] The specific implementation principle of the present invention is as follows:

[0072] For the lead-out of the eMMC signal, a plurality of signal probes 140 are arranged on the base plate 110. The signal probe 140 is arranged in the center of the base plate 110 and passes through the base plate 110. The signal pin of the eMMC is connected to the second pad of the test circuit board 200 through the signal probe 140. The second pad leads out the eMMC signal of the eMMC.

[0073] For the extraction of NAND signals, a selection circuit including a plurality of controlled switches is arranged in the bottom plate 110, and a plurality of test probes 150 and selection probes 130 are arranged on both sides of the bottom plate 110. Specifically, the selection probe 130 is arranged on the side of the bottom plate 110 away from the top plate 120, and one end of the selection probe 130 is connected to the first pad of the test circuit board 200; the test probe 150 is arranged on the side of the bottom plate 110 close to the top plate 120, and one end thereof penetrates the top plate 120 and is connected to the test pin of the eMMC. The other end of the selection probe 130 is connected to the first switch end of a controlled switch corresponding to it, and the other end of the test probe 150 is connected to the second switch end of one or more controlled switches corresponding to it. In the present application, each controlled switch represents a controlled branch. The selection circuit controls the conduction or cutoff of one or more controlled branches by controlling the opening or disconnection of one or more controlled switches. It should be noted that there is one and only one selection probe 130, one test probe 150 and one controlled switch on a controlled branch. When any controlled switch is turned on, the controlled branch where it is located is turned on, and the selection probe 130 and the test probe 150 located on this controlled branch are connected.

[0074] In the related art, the NAND signal is brought out through the NC pin selected on the PCB. In the present application, according to the NC pin selected on the PCB, the first pad corresponding to it is determined, and then the selection probe 130 connected to the first pad is determined. Each selection probe 130 corresponds to one or more controlled switches, and each test probe 150 also corresponds to one or more controlled switches. When the test probe 150 connected to the test pin of the eMMC and the selection probe 130 connected to the selected first pad are determined, the controlled switch that needs to be controlled to be connected can be determined. Among them, the controlled switch that needs to be controlled to be connected is respectively connected to the test probe 150 connected to the test pin of the eMMC and the selection probe 130 connected to the selected first pad.

[0075] Each test probe 150 is connected to one or more selection probes 130 through a corresponding controlled switch, that is, each test probe 150 is connected to one or more selection probes 130 through different controlled branches. For the test probe 150, there is only one controlled branch that is turned on during the test, and the turned-on controlled branch is the branch connecting the test probe 150 connected to the test pin of the eMMC and the selection probe 130 connected to the selected first pad, that is, the branch where the controlled switch that controls the connection is located; and all branches except the turned-on controlled branch need to be kept off. Therefore, when determining the controlled switch that needs to be controlled to be connected, it is also necessary to determine the controlled switch that needs to be controlled to be cut off. Among them, the controlled switch that needs to be controlled to be cut off is the other controlled switches except the controlled switch that needs to be controlled to be connected among the multiple controlled switches connected to the test probe 150, which are respectively connected to the test probe 150 connected to the test pin of the eMMC and other selection probes except the selected selection probe 130.

[0076] When the controller of the selection circuit controls the controlled switch that needs to be controlled to be connected to be turned on, the controlled branch where the controlled switch is located is turned on, and then the selection probe 130 and the test probe 150 located in the same controlled branch are connected. Among them, the selection probe 130 is a probe connected to the first pad selected on the PCB, and the test probe 150 is a probe connected to the test pin of the eMMC. At the same time, the controller of the selection circuit controls the controlled switch that needs to be controlled to be cut off to remain cut off or closed, so that the other controlled branches of the test probe 150 remain cut off. At this time, the test pin of the eMMC outputs a NAND signal to the first pad by connecting the controlled branch of the test probe 150 and the selection probe 130, and the analog integrated circuit connected to the first pad obtains this NAND signal. Finally, after the analog integrated circuit connected to the first pad obtains the NAND signal, the NAND signal is subsequently processed to realize the test of the eMMC. The eMMC signal is led out to the electronic device that needs to be controlled or data transmitted through the second pad to realize signal control or data transmission.

[0077] The technical solution of the present invention is further described and elaborated by taking an embodiment as follows.

[0078] Reference Figure 6 In this embodiment, the eMMC to be tested is provided with two test pins, wherein the two test pins of the eMMC to be tested are respectively connected to the first test probe on the test fixture 100 and the second test probe The test circuit board 200 is provided with four NC pins, which are defined as Pins, Among them, the first selection probe on the test fixture 100 With the test circuit board 200 Pin contact, second selection probe on test fixture 100 With the test circuit board 200 Pin contact, third selection probe on test fixture 100 With the test circuit board 200 Pin contact, the fourth selection probe on the test fixture 100 With the test circuit board 200 Pin contact.

[0079] In the test fixture 100, the controlled switch is an insulated gate bipolar transistor. Through four insulated gate bipolar transistors, four selection probes are connected , , , The four insulated gate bipolar transistors are respectively a first insulated gate bipolar transistor IGBT1, a second insulated gate bipolar transistor IGBT2, a third insulated gate bipolar transistor IGBT3 and a fourth insulated gate bipolar transistor IGBT4. The second test probe Through four insulated gate bipolar transistors, four selection probes are connected , , , The four insulated gate bipolar transistors are connected to each other, and are respectively a fifth insulated gate bipolar transistor IGBT5, a sixth insulated gate bipolar transistor IGBT6, a seventh insulated gate bipolar transistor IGBT7 and an eighth insulated gate bipolar transistor IGBT8.

[0080] Furthermore, the controller K of the selection circuit is provided with eight IO ports, which are the first IO port I / O1 to the eighth IO port I / O8. For the insulated gate bipolar transistor, its gate is the control terminal, its emitter is the first switch terminal, and its collector is the second switch terminal. Among them:

[0081] The gate of the first insulated gate bipolar transistor IGBT1 is connected to the first IO port I / O1, and the emitter thereof is connected to the corresponding first selection probe Connect its collector to the first test probe connect;

[0082] The gate of the second insulated gate bipolar transistor IGBT2 is connected to the second IO port I / O2, and the emitter thereof is connected to the corresponding second selection probe. Connect its collector to the first test probe connect;

[0083] The gate of the third insulated gate bipolar transistor IGBT3 is connected to the third IO port I / O3, and the emitter thereof is connected to the corresponding third selection probe. Connect its collector to the first test probe connect;

[0084] The gate of the fourth insulated gate bipolar transistor IGBT4 is connected to the fourth IO port I / O4, and the emitter thereof is connected to the corresponding fourth selection probe Connect its collector to the first test probe connect;

[0085] The gate of the fifth insulated gate bipolar transistor IGBT5 is connected to the fifth IO port I / O5, and the emitter thereof is connected to the corresponding first selection probe Connect its collector to the second test probe connect;

[0086] The gate of the sixth insulated gate bipolar transistor IGBT6 is connected to the sixth IO port I / O6, and the emitter thereof is connected to the corresponding second selection probe Connect its collector to the second test probe connect;

[0087] The gate of the seventh insulated gate bipolar transistor IGBT7 is connected to the seventh IO port I / O7, and the emitter thereof is connected to the corresponding third selection probe Connect its collector to the second test probe connect;

[0088] The gate of the eighth insulated gate bipolar transistor IGBT8 is connected to the eighth IO port I / O8, and the emitter thereof is connected to the corresponding fourth selection probe Connect its collector to the second test probe connect;

[0089] The controller K controls the opening or closing of the eight insulated gate bipolar transistors by configuring the first IO port I / O1 to the eighth IO port I / O8 to be in output mode.

[0090] In this embodiment, the circuit board 200 is selected as the test circuit board. Pins are brought out with the first test probe Connect the NAND signal of the test pin and select the test circuit board 200 on Pins are brought out with a second test probe Connect the TEST pin to the NAND signal.

[0091] For an insulated gate bipolar transistor, the transistor is turned on when the gate is at a high level and is turned off when the gate is at a low level. The NAND signal output from the connected test pin is led out to the test circuit board 200. When the pin is turned on, the first test probe and with First choice probe for pin connection In response, the controller K outputs a high level signal through the first IO port I / O1, so that the first test probe is connected and first choice probe The first insulated gate bipolar transistor IGBT1 is turned on, and a low level signal is output through the second IO port I / O2, the third IO port I / O3 and the fourth IO port I / O4, so that the first test probe is connected and the second selection probe The second insulated gate bipolar transistor IGBT2 is connected to the first test probe and the third selection probe The third insulated gate bipolar transistor IGBT3 is connected to the first test probe and the fourth selection probe The fourth insulated gate bipolar transistor IGBT4 is turned off. With the first choice probe Connected, the eMMC test pin outputs NAND signal to pin. And for all but the first choice probe For other selection probes except the first selection probe, since the corresponding controlled switch is closed, the controlled branch where it is located is not turned on. Other selection probes other than the first test probe are not connected , and no signal transmission is performed.

[0092] When the eMMC needs to be tested with the second probe The NAND signal output from the connected test pin is led out to the test circuit board 200. When the pin is turned on, the second test probe needs to be turned on and with Pin connection for the second choice probe In response, the controller K outputs a high level signal through the sixth IO port I / O6, so that the second test probe is connected. and the second selection probe The sixth insulated gate bipolar transistor IGBT6 is turned on, and at the same time, a low level signal is output through the fifth IO port I / O5, the seventh IO port I / O7 and the eighth IO port I / O8, so that the second test probe is connected and first choice probe The fifth insulated gate bipolar transistor IGBT5 is connected to the second test probe and the third selection probe The seventh insulated gate bipolar transistor IGBT7 is connected to the second test probe and the fourth selection probe The eighth insulated gate bipolar transistor IGBT8 is turned off. With the second choice probe Connected, the eMMC test pin outputs NAND signal to pin. And for the second selection probe For other selection probes except the second selection probe, since the corresponding controlled switch is closed, the controlled branch where it is located is not turned on. Other selection probes other than the second test probe are not connected , and no signal transmission is performed.

[0093] In some possible implementations, a plurality of first slots are provided on a side of the bottom plate 110 away from the top plate 120, and the plurality of first slots correspond one-to-one to a plurality of selection probes, and the first end of each selection probe extends into the bottom plate 110 through the corresponding first slot and is gap-matched with the first slot.

[0094] In some possible implementations, a plurality of second slots are provided on one side of the bottom plate 110 close to the top plate 120, and the plurality of second slots correspond one-to-one to the plurality of test probes 150. The first end of each test probe 150 extends into the bottom plate 110 through the corresponding second slot and is gap-matched with the second slot.

[0095] In some possible implementations, a plurality of first through holes are disposed in the center of the base plate 110 , and the plurality of first through holes correspond one-to-one to the plurality of signal probes 140 , and each signal probe 140 passes through a corresponding first through hole and is gap-matched with the first through hole.

[0096] Reference Figure 2 In some possible implementations, a placement groove 160 is fixedly installed on one side of the top plate 120 away from the bottom plate 110, and a limiting frame 161 is set in the placement groove 160. The placement groove 160 is used to place the eMMC to be tested, and the eMMC to be tested is placed in close contact with the limiting frame 161.

[0097] The top plate 120 is provided with a plurality of second through holes, which correspond one to one with the plurality of test probes 150 and the plurality of signal probes 140. The second end of each test probe 150 passes through the corresponding second through hole and is gapped with the second through hole, and the second end of each test probe 150 extends out of the top plate 120 and is connected to the test pin of the eMMC to be tested placed in the placement groove 160. The second end of each signal probe 140 passes through the corresponding second through hole and is gapped with the second through hole, and the second end of each signal probe 140 extends out of the top plate 120 and is connected to the signal pin of the eMMC to be tested placed in the placement groove 160.

[0098] The eMMC testing method according to the embodiment of the present invention will be described in detail below with reference to the accompanying drawings. First, the eMMC testing method according to the embodiment of the present invention will be described with reference to the accompanying drawings.

[0099] An eMMC test method is provided in an embodiment of the present invention. The eMMC test method in the embodiment of the present invention can be applied to a terminal, a server, or software running in a terminal or a server. The terminal can be a tablet computer, a laptop computer, a desktop computer, etc., but is not limited thereto. The server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN, and big data and artificial intelligence platforms.

[0100] Reference Figure 7 The eMMC testing method in the embodiment of the present invention is executed by the controller and may include but is not limited to the following steps:

[0101] S100: Find a test probe connected to a test pin of the eMMC to be tested.

[0102] It should be noted that a plurality of test probes 150 are disposed on one side of the bottom plate 110 of the test fixture 100, wherein at least one test probe 150 can be connected to the test pin of the eMMC to be tested. Since the test pin of the eMMC to be tested may vary depending on the manufacturer and the specifications of the eMMC, the purpose of this step is to determine the position of the test pin reserved on the eMMC to be tested.

[0103] S200: When a test probe connected to a test pin of the eMMC to be tested is found, a coordinate position of the test probe is determined.

[0104] S300: Acquire and detect a test instruction.

[0105] It should be noted that the test instruction carries a lead-out mark, wherein the lead-out mark is defined as the coordinate position of the first pad on the test circuit board 200 for leading out the signal between the flash memory inside the eMMC to be tested and the flash memory controller, and the signal between the flash memory inside the eMMC to be tested and the flash memory controller is a NAND signal.

[0106] S400: When it is detected that the test instruction carries a lead-out identifier, one or more controlled switches corresponding to the test probe are controlled according to the lead-out identifier and the coordinate position of the test probe, so that the NAND signal of the eMMC to be tested is led out from its test pin to the test circuit board.

[0107] In some possible implementations, before step S100, the following steps are also included:

[0108] A1: Take the center of the bottom plate of the test fixture as the coordinate origin, build a two-dimensional coordinate system, determine the coordinate positions of multiple test probes in the two-dimensional coordinate system, and use the coordinate positions as coordinate identifiers. Each test probe carries its corresponding coordinate identifier;

[0109] A2: Determine the coordinate positions of multiple selection probes in a two-dimensional coordinate system, and use the coordinate positions of the selection probes as coordinate identifiers of the selection probes, and each selection probe carries its corresponding coordinate identifier;

[0110] A3: According to the coordinate identifiers carried by the selection probes and the coordinate identifiers carried by the test probes, a mapping relationship between the selection probes and the test probes is established.

[0111] It should be noted that the mapping relationship is that each selection probe 130 corresponds to one or more test probes 150 , and each test probe 150 corresponds to one or more selection probes 130 .

[0112] In some possible implementations, determining the coordinate position of the test probe in step S200 may include the following steps:

[0113] S210: When the test probe connected to the test pin of the eMMC to be tested is found, the coordinate identifier of the test probe connected to the test pin of the eMMC to be tested is detected and identified.

[0114] S220: When the coordinate identifier of the test probe connected to the test pin of the eMMC to be tested is identified, the coordinate position of the test probe connected to the test pin of the eMMC to be tested is determined according to the identified coordinate identifier.

[0115] In some possible implementations, in step S400, controlling one or more controlled switches corresponding to the test probe according to the lead-out identifier and the coordinate position of the test probe may include the following steps:

[0116] S410 , determining one or more selection probes mapped by the test probe according to the coordinate position of the test probe, and determining the coordinate positions of the mapped one or more selection probes.

[0117] In the aforementioned step A3, a mapping relationship between the selection probe 130 and the test probe 150 is constructed. The constructed mapping relationship can be combined with the coordinate position of the test probe 150 connected to the test pin of the eMMC to be tested to determine at least one selected probe 130 to which it is mapped. After determining the selected probe 130 to which it is mapped, the coordinate identifier carried by the selected probe 130 is detected and identified to obtain the coordinate position of the selected probe 130.

[0118] S420, matching the coordinate positions of the mapped one or more selection probes with the extraction identifier to obtain the selection probes matching the extraction identifier.

[0119] In this step, among at least one selection probe 130 mapped by the test probe 150 connected to the test pin of the eMMC to be tested, there are probes corresponding to the selected first pad and probes corresponding to the non-selected first pad. If the test pin of the eMMC to be tested is to be connected with the selected first pad, it is necessary to connect the test probe 150 connected to the test pin of the eMMC to be tested and the selection probe 130 in contact with the first pad. Therefore, it is necessary to determine the selection probe 130 in contact with the first pad, and this selection probe 130 needs to have a mapping relationship with the test probe 150. In this regard, the present application completes the mapping screening of the selection probe 130 through this step, by matching its coordinate position or coordinate identifier with the lead-out identifier, if its coordinate position corresponds to the coordinate position of the first pad in the lead-out identifier, or, its coordinate identifier corresponds to the lead-out identifier, then this selection probe 130 is a selection probe that matches the lead-out identifier. If its coordinate position does not correspond to the coordinate position of the first pad in the lead-out mark, or its coordinate mark does not correspond to the lead-out mark, then this selection probe 130 is not a selection probe that matches the lead-out mark.

[0120] Optionally, the correspondence between the coordinate position of the first pad and the coordinate position of the selection probe may be pre-established, and the correspondence between the lead-out mark and the coordinate mark of the selection probe may also be pre-established.

[0121] S430, determining a controlled switch group according to the coordinate position of the selection probe and the coordinate position of the test probe that match the lead-out identifier.

[0122] It should be noted that the controlled switch group includes a controlled switch connecting the selection probe 130 matching the lead-out identifier and the test probe 150 connected to the test pin of the eMMC to be tested, as well as a controlled switch connecting the test probe 150 connected to the test pin of the eMMC to be tested and other selection probes 130 mapped to this test probe 150.

[0123] In this step, each test probe 150 corresponds to at least one controlled switch, and each selection probe 130 also corresponds to at least one controlled switch, but one controlled switch will only connect one test probe 150 and one selection probe 130. After determining the selection probe 130 that matches the lead-out identifier and the test probe 150 connected to the test pin of the eMMC to be tested, if the test probe 150 connected to the test pin of the eMMC to be tested and the selection probe 130 in contact with the first pad are to be connected, it is necessary to control the controlled switch connecting the test probe 150 and the selection probe 130 to be turned on, so that the controlled branch where the test probe 150 and the selection probe 130 are located is turned on. At the same time, since during the test, one and only one of the multiple controlled branches of the test probe 150 is turned on, it is also necessary to control the controlled switch connecting the test probe 150 and the other selection probes 130 mapped thereto to be turned off. The purpose of this step is to determine the controlled switches that need to be turned on and off.

[0124] S440, control the controlled switches connecting the selection probe and the test probe matching the lead-out identifier to be turned on, and at the same time, the controlled switches connecting the test probe and other selection probes mapped thereto remain closed, so that the test circuit board leads out the signal between the flash memory inside the eMMC and the flash memory controller.

[0125] In this step, the selection probe 130 matching the lead-out mark is connected to the first pad selected on the test circuit board 200, which is the pad for leading out the NAND signal, and the test probe 150 is connected to the test pin of the eMMC to be tested. When the controlled switch connecting the test probe 150 and the selection probe 130 is turned on, and the other controlled switches in the controlled switch group except the turned-on controlled switch remain closed, the selection probe 130 in contact with the selected first pad and the test probe 150 connected to the test pin of the eMMC to be tested are connected, and the NAND signal of the eMMC to be tested is output to the test circuit board 200; and the other controlled branches of the test probe 150 remain closed, and no signal transmission is performed, thereby realizing the lead-out of the NAND signal.

[0126] In some possible implementations, the eMMC testing method further includes:

[0127] Detecting the connection state of the signal probe, where the connection state includes either a connected state or a disconnected state;

[0128] When it is detected that the signal probe is in the connected state, the control signal and / or data signal of the flash memory controller inside the eMMC to be tested, ie, the eMMC signal, is led out to the second pad of the test circuit board through the signal probe.

[0129] It should be noted that when one end of the signal probe 140 is connected to the signal pin of the eMMC to be tested and the other end thereof is connected to the signal probe 140 of the second pad of the test circuit board 200 , the signal probe 140 is in a connected state.

[0130] It should be noted that when one end of the signal probe 140 is not connected to the signal pin of the eMMC to be tested, and / or the other end of the signal probe 140 is connected to the second pad of the test circuit board 200, the signal probe 140 is in an unconnected state.

[0131] In some possible implementations, the eMMC testing method further includes:

[0132] When it is detected that the signal probe is in a disconnected state, the eMMC signal of the eMMC to be tested is not led out.

[0133] In summary, when testing eMMC, it is usually necessary to lead out the signal between the flash memory and the flash memory controller inside the eMMC, namely the NAND signal, and lead out the output signal of the flash memory controller of the eMMC, namely the eMMC signal. The related technology usually uses welding or fixture connection to lead out the NAND signal and eMMC signal of the eMMC to the PCB. Since the setting positions of the test pins of the eMMC are different, the fixture needs to be customized according to the test pins, which increases the test cost; if the welding method is used to complete the test, it may have a negative environmental impact on the internal components of the eMMC, causing the internal data to be lost or the internal components to be damaged.

[0134] In order to eliminate the welding process, reduce the testing cost of eMMC, and at the same time improve the versatility of the test fixture 100 and expand its application scenarios, this specific embodiment provides a specially constructed test fixture 100, which is provided with a selection probe 130, a signal probe 140 and a test probe 150. Each test probe 150 is connected to one or more selection probes 130 through one or more controlled switches, and each selection probe 130 is also connected to one or more test probes 150 through one or more controlled switches. By controlling the controlled switches of the test probe 150 connected to the test pin of the eMMC and the selection probe 130 connected to the selected first pad to be turned on, the effect of leading the NAND signal inside the eMMC to the selected pad on the PCB is achieved; and the control signal or data signal of the eMMC can be led out through the signal probe 140. When the present invention is adopted, the user can modify the position of the test pin according to the demand, and the test pin, signal pin and pad of the PCB of the eMMC can be connected by controlling the opening and closing of the controlled switch. The test fixture 100 is no longer limited by the setting position of the test pin of the eMMC, which improves the versatility and reusability of the test fixture 100, enhances its adaptability to the eMMC, and broadens the application scenarios of the test fixture 100, realizes the low-cost and high-efficiency completion of the eMMC test under the condition of exempting welding, and avoids the situation of the loss of internal data of the eMMC due to welding. The present invention is applicable to an eMMC provided with a test pin, and is particularly applicable to an eMMC packaged in BGA.

[0135] An embodiment of the present invention further provides a computer-readable storage medium, in which a program executable by a processor is stored. When the program executable by the processor is executed by the processor, it is used to execute the above-mentioned eMMC testing method.

[0136] Similarly, the contents of the above method embodiments are all applicable to the present storage medium embodiments. The functions specifically implemented by the present storage medium embodiments are the same as those of the above method embodiments, and the beneficial effects achieved are also the same as those achieved by the above method embodiments.

[0137] In some selectable embodiments, the function / operation mentioned in the block diagram may not occur in the order mentioned in the operation diagram. For example, depending on the function / operation involved, the two boxes shown in succession can actually be executed substantially simultaneously or the boxes can sometimes be executed in reverse order. In addition, the embodiment presented and described in the flow chart of the present invention is provided by way of example, for the purpose of providing a more comprehensive understanding of technology. The disclosed method is not limited to the operation and logic flow presented herein. Selectable embodiments are expected, wherein the order of various operations is changed and the sub-operation of a part for which is described as a larger operation is performed independently.

[0138] In addition, although the present invention is described in the context of functional modules, it should be understood that, unless otherwise specified, one or more of the functions and / or features can be integrated into a single physical device and / or software module, or one or more functions and / or features can be implemented in a separate physical device or software module. It is also understood that a detailed discussion of the actual implementation of each module is unnecessary for understanding the present invention. More specifically, in view of the properties, functions and internal relationships of the various functional modules in the device disclosed herein, the actual implementation of the module will be understood within the conventional skills of the engineer. Therefore, those skilled in the art can implement the present invention set forth in the claims without excessive experimentation using ordinary techniques. It is also understood that the specific concepts disclosed are merely illustrative and are not intended to limit the scope of the present invention, which is determined by the full scope of the appended claims and their equivalents.

[0139] If the functions are implemented in the form of software functional units and sold or used as independent products, they can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of the present invention, or the part that contributes to the prior art or the part of the technical solution, can be embodied in the form of a software product. The computer software product is stored in a storage medium, including several programs to enable a computer device (which can be a personal computer, server, or network device, etc.) to perform all or part of the steps of the methods described in various embodiments of the present invention. The aforementioned storage media include: U disk, mobile hard disk, read-only memory (ROM, Read-Only Memory), random access memory (RAM, Random Access Memory), disk or optical disk, etc., various media that can store program codes.

[0140] The logic and / or steps represented in the flowchart or otherwise described herein, for example, may be considered as an ordered list of executable programs for implementing logical functions, and may be embodied in any computer-readable medium for use by a program execution system, device or apparatus (such as a computer-based system, a system including a processor, or other system that can fetch and execute a program from a program execution system, device or apparatus), or in conjunction with such program execution system, device or apparatus. For purposes of this specification, a "computer-readable medium" may be any device that can contain, store, communicate, propagate or transmit a program for use by a program execution system, device or apparatus, or in conjunction with such program execution system, device or apparatus.

[0141] More specific examples of computer-readable media (a non-exhaustive list) include the following: an electrical connection with one or more wires (electronic device), a portable computer disk case (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable and programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disk read-only memory (CDROM). In addition, the computer-readable medium may even be a paper or other suitable medium on which the program is printed, since the program may be obtained electronically, for example, by optically scanning the paper or other medium, followed by editing, deciphering or, if necessary, processing in another suitable manner, and then stored in a computer memory.

[0142] It should be understood that the various parts of the present invention can be implemented by hardware, software, firmware or a combination thereof. In the above-mentioned embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable program execution system. For example, if implemented by hardware, as in another embodiment, it can be implemented by any one of the following technologies known in the art or their combination: a discrete logic circuit having a logic gate circuit for implementing a logic function for a data signal, a dedicated integrated circuit having a suitable combination of logic gate circuits, a programmable gate array (PGA), a field programmable gate array (FPGA), etc.

[0143] In the above description of this specification, the description with reference to the terms "one embodiment / example", "another embodiment / example" or "certain embodiments / examples" etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic representation of the above terms does not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0144] Although embodiments of the present invention have been shown and described, it will be appreciated by those skilled in the art that various changes, modifications, substitutions and variations may be made to the embodiments without departing from the principles and spirit of the present invention, and that the scope of the present invention is defined by the claims and their equivalents.

[0145] The above is a specific description of the preferred implementation of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art may make various equivalent modifications or substitutions without violating the spirit of the present invention. These equivalent modifications or substitutions are all included in the scope defined by the claims of the present invention.

Claims

1. A test fixture for eMMC, characterized in that: include: A base, comprising a bottom plate and a selection circuit arranged in the bottom plate, wherein the selection circuit comprises a plurality of controlled switches and a controller, and control ends of the plurality of controlled switches are all connected to the controller; A top plate, which is arranged opposite to the base and fixed to each other, and a side of the top plate away from the base is used for placing the eMMC to be tested; A plurality of selection probes are arranged on a side of the bottom plate away from the top plate and vertically extend into the bottom plate, each of the selection probes corresponds to one or more of the controlled switches, and the plurality of selection probes also correspond one-to-one to a plurality of first pads of an external test circuit board, one end of each of the selection probes is connected to a first switch end of the corresponding one or more controlled switches, and the other end of each of the selection probes is used to contact the corresponding first pad; A plurality of signal probes are arranged in the center of the bottom plate, the plurality of signal probes are arranged in a rectangular shape, and the plurality of signal probes correspond one by one to the plurality of second pads of the test circuit board; wherein one end of each of the signal probes passes through the bottom plate and extends out of a side of the bottom plate away from the top plate, one end of each of the signal probes is used to contact the corresponding second pad, the other end of each of the signal probes passes through the top plate and extends out of a surface of a side of the top plate away from the bottom plate, and the other end of each of the signal probes is used to connect to the signal pin of the eMMC to be tested; A plurality of test probes are arranged on a side of the bottom plate close to the top plate and vertically extend into the bottom plate, the plurality of test probes are arranged around the plurality of signal probes, and the plurality of test probes are arranged in a rectangular shape, the spacing between two adjacent test probes is equal, and each of the test probes corresponds to one or more controlled switches; wherein one end of each of the test probes is connected to the second switch end of the corresponding one or more controlled switches, the other end of each of the test probes passes through the top plate and extends out of the surface of the top plate away from the bottom plate, and the other end of each of the test probes is used to connect to the test pin of the eMMC to be tested; Wherein, the number of the test probes is greater than the number of the selection probes.

2. A test fixture for eMMC according to claim 1, characterized in that: The eMMC to be tested adopts BGA153 package.

3. The eMMC test fixture according to claim 1, characterized in that: The controlled switch includes any one of a triode, a field effect transistor, a relay or an IGBT.

4. The eMMC test fixture according to claim 1, characterized in that: The position of the signal probe meets the pin position specified by the eMMC protocol.

5. A test device for eMMC, characterized in that: A test fixture and a test circuit board for an eMMC as described in any one of claims 1 to 4, wherein a plurality of first pads and second pads are arranged on the test circuit board, the first pads are connected to an analog integrated circuit, the first pads are used to lead out signals between a flash memory and a flash memory controller inside the eMMC to be tested to the analog integrated circuit, and the analog integrated circuit is used to test the eMMC to be tested based on the signals between the flash memory and the flash memory controller; the second pads are used to lead out control signals and / or data signals of the flash memory controller inside the eMMC to be tested.

6. A test device for eMMC according to claim 5, characterized in that, The test circuit board adopts BGA153 package.

7. A method for testing eMMC, characterized in that: Applied to an eMMC testing device as claimed in any one of claims 5 to 6, the method comprising the following steps: Find the test probe connected to the test pin of the eMMC to be tested; When a test probe connected to a test pin of the eMMC to be tested is found, a coordinate position of the test probe is determined; Acquire and detect a test instruction, wherein the test instruction carries a lead-out identifier, and the lead-out identifier is defined as a coordinate position of a first pad on a test circuit board for leading out a signal between a flash memory and a flash memory controller inside an eMMC to be tested; When it is detected that the test instruction carries a lead-out identifier, one or more controlled switches corresponding to the test probe are controlled according to the lead-out identifier and the coordinate position of the test probe, so that the signal between the flash memory inside the eMMC to be tested and the flash memory controller is led out from its test pin to the first pad on the test circuit board corresponding to the lead-out identifier.

8. A method for testing eMMC according to claim 7, characterized in that: The step of controlling one or more controlled switches corresponding to the test probe according to the lead-out identifier and the coordinate position of the test probe comprises: Determining one or more selection probes mapped by the test probe according to the coordinate position of the test probe, and determining the coordinate positions of the mapped one or more selection probes; Matching the mapped coordinate positions of one or more selection probes with the extraction identifier to obtain the selection probe matching the extraction identifier; Determine a controlled switch group according to the coordinate position of the selection probe matched with the lead-out identifier and the coordinate position of the test probe, wherein the controlled switch group includes a controlled switch connecting the selection probe matched with the lead-out identifier and the test probe, and the controlled switch group also includes a controlled switch connecting the test probe with other selection probes mapped thereto; The controlled switch connecting the selection probe and the test probe matching the lead-out identifier is controlled to be turned on, while the controlled switch connecting the test probe and other selection probes mapped thereto remains closed, so that the test circuit board leads out the signal between the flash memory inside the eMMC and the flash memory controller.

9. A computer-readable storage medium storing a program executable by a processor, characterized in that: The processor-executable program is used to implement an eMMC testing method as described in any one of claims 7 to 8 when executed by the processor.

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