Hot-swap protection circuit, interface chip and hot-swap system for I2C bus

Abstract

The embodiment of the present invention provides a hot-swap protection circuit, an interface chip and a hot-swap system for an I2C bus, belonging to the field of hot-swap technology. The hot-swap protection circuit of the circuit includes a control circuit, a pull-up circuit and a cut-off circuit. The two input ends of the control circuit are respectively connected to the I2C bus and the secondary board power supply VDD, and the output end is connected to the first input end of the pull-up circuit. The input end of the cut-off circuit is connected to VDD, and the output end is connected to the second input end of the pull-up circuit. The output end of the pull-up circuit is connected to the I2C bus. The control circuit is configured to turn on the pull-up circuit at a set time when VDD is inserted first, so as to pull up the suspended I2C bus through the pull-up circuit. The cut-off circuit is configured to cut off the current inflow path between VDD and the I2C bus when the I2C bus is inserted first. The embodiment of the present invention solves the defects of bad hot-swap caused by the insertion order and the power-on order, and reduces the burden of software and hardware.

Description

Technical Field

[0001] The invention relates to the technical field of hot plugging, and in particular to a hot plugging protection circuit, an interface chip and a hot plugging system for an I2C bus. Background Art

[0002] like Figure 1 As shown, the hardware implementation of data communication between the I2C (Inter-Integrated Circuit) device on the secondary board and the main board depends on the I2C bus (including the defined data line SDA and clock line SCL, hereinafter referred to as the bus) and its adapted secondary board power supply VDD and ground line GND. However, when the I2C device on the secondary board implements the hot-swap function in the form of a board, the insertion order of the I2C bus and the secondary board power supply VDD is unknown, which may cause the I2C bus to be abnormally pulled down or pulled up, and interfere with other devices mounted on the I2C bus; or, due to the power-on sequence, an erroneous level signal may be output. In this regard, the existing technical solution is usually to introduce an ID bus, and configure a monitoring device with an interrupt program adapted to the ID bus on the secondary board, and use the monitoring module to judge the insertion or removal status of the I2C device. However, this solution requires the additional addition of an ID bus and the design of a monitoring program, which often results in a greater hardware burden and software overhead. Summary of the invention

[0003] The purpose of the embodiments of the present invention is to provide a hot-swap protection circuit, an interface chip and a hot-swap system for an I2C bus, so as to at least partially solve the above technical problems.

[0004] In order to achieve the above-mentioned purpose, an embodiment of the present invention provides a hot-swap protection circuit for an I2C bus, comprising a control circuit, a pull-up circuit and a cut-off circuit, wherein two input ends of the control circuit are respectively connected to the I2C bus and the secondary board power supply VDD, and the output end is connected to the first input end of the pull-up circuit, the input end of the cut-off circuit is connected to the secondary board power supply VDD, the output end is connected to the second input end of the pull-up circuit, and the output end of the pull-up circuit is connected to the I2C bus. The control circuit is configured to turn on the pull-up circuit at a set time when the secondary board power supply VDD is inserted first, so as to pull up the suspended I2C bus through the pull-up circuit. The cut-off circuit is configured to cut off the current inflow path formed by the pull-up circuit between the secondary board power supply VDD and the I2C bus when the I2C bus is inserted first.

[0005] Preferably, the control circuit includes a timing circuit and a switch circuit connected in sequence between the secondary board power supply VDD and the pull-up circuit, the pull-up circuit includes a first pull-up sub-circuit and a second pull-up sub-circuit arranged in parallel between the I2C bus and the cut-off circuit, and the first pull-up sub-circuit is directly connected to the timing circuit, while the second pull-up sub-circuit is connected to the timing circuit through the switch circuit. The timing circuit is configured to: turn on the first pull-up sub-circuit and turn on the second pull-up sub-circuit through the switch circuit within the set time when the secondary board power supply VDD is inserted first; and turn off the first pull-up sub-circuit after the set time, and drive the switch circuit to maintain the conduction of the second pull-up sub-circuit.

[0006] Preferably, the cut-off circuit includes a first circuit breaker connected to the first pull-up sub-circuit and a second circuit breaker connected to the second pull-up sub-circuit, and when the first pull-up sub-circuit and the second pull-up sub-circuit each have an internal parasitic diode, the first circuit breaker and the second circuit breaker are respectively diodes that are reversely connected to the corresponding parasitic diodes.

[0007] Preferably, the first circuit breaker and the second circuit breaker are respectively a first diode D1 and a second diode D2. The first pull-up sub-circuit comprises a first resistor R1 and a first PMOS tube M1, one end of the first resistor R1 is connected to the I2C bus, the other end is connected to the drain of the first PMOS tube M1, the gate of the first PMOS tube M1 is connected to the timing circuit, and the source of the first PMOS tube M1 is connected to the secondary board power supply VDD via the first diode D1. The second pull-up sub-circuit comprises a second resistor R2 and a second PMOS tube M2, one end of the second resistor R2 is connected to the I2C bus, the other end is connected to the drain of the second PMOS tube M2, the gate of the second PMOS tube M2 is connected to the timing circuit via the switch circuit, and the source of the second PMOS tube M2 is connected to the secondary board power supply VDD via the second diode D2. Wherein, the positive electrodes of the first diode D1 and the second diode D2 are connected to the secondary board power supply VDD, and the negative electrodes are connected to the sources of the corresponding PMOS tubes.

[0008] Preferably, the resistance of the first resistor R1 is smaller than that of the second resistor R2.

[0009] Preferably, the timing circuit includes: a third resistor R3 and a capacitor C1, wherein one end of the third resistor R3 is connected to the secondary board power supply VDD, and the other end is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, and the output end of the timing circuit is led out from the connecting line between the third resistor R3 and the capacitor C1.

[0010] Preferably, the switch circuit adopts an interlocking logic gate circuit, and two input ends of the interlocking logic gate circuit are respectively connected to the output end of the timing circuit and the I2C bus.

[0011] An embodiment of the present invention further provides an interface chip provided with any of the above-mentioned hot-swap protection circuits.

[0012] An embodiment of the present invention further provides a hot-swap system for an I2C bus, comprising a main board and a secondary board for implementing data communication via the I2C bus, and the secondary board is provided with any of the above-mentioned interface chips.

[0013] Preferably, a control module is further provided on the secondary board, and the control module is connected to the interface chip and the I2C device and is used to control the communication associated with the I2C bus.

[0014] Through the above technical solution, the hot-swap protection circuit of the embodiment of the present invention does not require a special ID line and a monitoring device, and can automatically pull up the suspended bus and cut off the current flow path from the I2C bus to the secondary board power supply according to the insertion state of the I2C bus, thereby solving the defects of poor hot-swap and error signals caused by the insertion sequence and power-on sequence during the hot-swap process, and reducing the burden on software and hardware.

[0015] Other features and advantages of the embodiments of the present invention will be described in detail in the subsequent detailed description. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The accompanying drawings are used to provide a further understanding of the embodiments of the present invention and constitute a part of the specification. Together with the following specific implementations, they are used to explain the embodiments of the present invention, but do not constitute a limitation on the embodiments of the present invention. In the accompanying drawings:

[0017] Figure 1 It is a conventional hardware structure that realizes communication between the main board and the secondary board based on the I2C bus.

[0018] Figure 2 1 is a functional structure diagram of a hot-swap protection circuit for an I2C bus according to an embodiment of the present invention;

[0019] Figure 3 is a functional structure diagram of a hot-swap protection circuit in a preferred embodiment of the present invention;

[0020] Figure 4 is a circuit diagram of a hot-swap protection circuit in an example of an embodiment of the present invention;

[0021] Figure 5 is a schematic diagram of a PMOS tube having a parasitic diode; and

[0022] Figure 6 It is a functional structure diagram of a hot-swap system for an I2C bus according to an embodiment of the present invention.

[0023] Description of Reference Numerals

[0024] 100, control circuit; 200, pull-up circuit; 300, cut-off circuit; 400, CMOS inverter; 500, ESD protection circuit; 110, timing circuit; 120, switch circuit; 130, buffer circuit; 210, first pull-up sub-circuit; 220, second pull-up sub-circuit; 310, first circuit breaker; 320, second circuit breaker. DETAILED DESCRIPTION

[0025] The specific implementation of the embodiment of the present invention is described in detail below in conjunction with the accompanying drawings. It should be understood that the specific implementation described here is only used to illustrate and explain the embodiment of the present invention, and is not used to limit the embodiment of the present invention.

[0026] Figure 2 Schematic diagram of the functional structure of the hot-swap protection circuit for I2C bus according to an embodiment of the present invention. Figure 1 The hardware architecture of hot-swappable I2C devices shown is used to protect the hot-swappable I2C devices between the main board and the secondary board, and in particular to protect the sequential insertion of the I2C bus and the secondary board power supply VDD during the hot-swappable process.

[0027] like Figure 2 As shown, the hot-swap protection circuit includes a control circuit 100, a pull-up circuit 200 and a cut-off circuit 300, and the two input terminals (T1 and T2) of the control circuit 100 are respectively connected to the I2C bus and the secondary board power supply VDD, and the output terminal is connected to the first input terminal of the pull-up circuit 200, the input terminal of the cut-off circuit 300 is connected to the secondary board power supply VDD, and the output terminal is connected to the second input terminal of the pull-up circuit 200, and the output terminal of the pull-up circuit 200 is connected to the I2C bus.

[0028] The control circuit 100 is configured to turn on the pull-up circuit 200 at a set time when the secondary board power supply VDD is inserted first, so as to pull up the suspended I2C bus through the pull-up circuit 200. The cut-off circuit 300 is configured to cut off the current flow path formed by the pull-up circuit 200 between the secondary board power supply VDD and the I2C bus when the I2C bus is inserted first.

[0029] Accordingly, the hot-swap protection circuit of the embodiment of the present invention does not require a dedicated ID line and a monitoring device, and can automatically pull up the suspended bus and cut off the current flow path from the I2C bus to the secondary board power supply according to the insertion status of the I2C bus, thereby solving the defects of poor hot-swap and error signals caused by the insertion sequence and power-on sequence during the hot-swap process, and reducing the burden on software and hardware.

[0030] Figure 3 FIG. 1 is a functional structure diagram of a hot-swap protection circuit in a preferred embodiment of the present invention. Figure 3 As shown, in a preferred embodiment, the control circuit 100 includes a timing circuit 110 and a switch circuit 120 connected in sequence between the sub-board power supply VDD and the pull-up circuit 200, and the pull-up circuit 200 includes a first pull-up sub-circuit 210 and a second pull-up sub-circuit 220 arranged in parallel between the I2C bus and the cut-off circuit 300, and the first pull-up sub-circuit 210 is directly connected to the timing circuit 110, and the second pull-up sub-circuit 220 is connected to the timing circuit 110 through the switch circuit 120.

[0031] The timing circuit 110 is configured to: turn on the first pull-up sub-circuit 210 and turn on the second pull-up sub-circuit 220 through the switch circuit 120 within the set time when the secondary board power supply VDD is inserted first; and turn off the first pull-up sub-circuit 210 after the set time, and drive the switch circuit to maintain the conduction of the second pull-up sub-circuit 220. The timing circuit 110 can adopt a conventional timer circuit, for example, composed of resistors and capacitors, the switch circuit 120 can adopt a conventional logic circuit, for example, implemented by an interlocked NAND gate, and the two pull-up sub-circuits can be implemented by a common pull-up resistor. In this way, in a preferred embodiment of the present invention, the pull-up of the suspended I2C bus can be achieved by the "timing + logic control + pull-up resistor" method, and this implementation method is simple and low in cost.

[0032] More preferably, the cut-off circuit 300 includes a first circuit breaker 310 connected to the first pull-up sub-circuit 210 and a second circuit breaker 320 connected to the second pull-up sub-circuit 220, and when the first pull-up sub-circuit 210 and the second pull-up sub-circuit 220 each have an internal parasitic diode, the first circuit breaker 310 and the second circuit breaker 320 are diodes that are reversely connected to the corresponding parasitic diodes. In this way, the current inflow path between the secondary board power supply VDD and the I2C bus is directly cut off by the reversely connected diodes, which prevents the bus from being pulled down by mistake due to the VDD of the secondary board that may not be powered on during the hot plug process in a simple and economical way.

[0033] Combine the following Figure 4 The example of Figure 3 A specific implementation scheme of the preferred embodiment.

[0034] Figure 4 is a circuit diagram of a hot-swap protection circuit in an example of an embodiment of the present invention. Figure 4 , the first circuit breaker 310 and the second circuit breaker 320 are respectively a first diode D1 and a second diode D2; the first pull-up sub-circuit 210 includes a first resistor R1 and a first PMOS tube M1, one end of the first resistor R1 is connected to the I2C bus, the other end is connected to the drain of the first PMOS tube M1, the gate of the first PMOS tube M1 is connected to the timing circuit, and the source of the first PMOS tube M1 is connected to the secondary board power supply VDD via the first diode D1; the second pull-up sub-circuit 220 includes a second resistor R2 and a second PMOS tube M2, one end of the second resistor R2 is connected to the I2C bus, the other end is connected to the drain of the second PMOS tube M2, the gate of the second PMOS tube M2 is connected to the timing circuit 110 via the switch circuit 120, and the source of the second PMOS tube M2 is connected to the secondary board power supply VDD via the second diode D2. Wherein, the positive electrodes of the first diode D1 and the second diode D2 are connected to the secondary board power supply VDD, and the negative electrodes are connected to the sources of the corresponding PMOS tubes.

[0035] Furthermore, the timing circuit 110 includes: a third resistor R3 and a capacitor C1, wherein one end of the third resistor R3 is connected to the sub-board power supply VDD, and the other end is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, and the connection line between the third resistor R3 and the capacitor C1 leads to the output end of the timing circuit. Figure 4 As shown, the switch circuit 120 may be implemented by an interlocking logic gate circuit (for example, implemented by a NAND gate in the figure), and the two input terminals (respectively denoted as L1 terminal and L2 terminal) of the interlocking logic gate circuit are respectively connected to the output terminal of the timing circuit 110 and the I2C bus, and the output terminal (represented as L3 terminal) is connected to the second pull-up sub-circuit 220. In addition, it can be understood that the input and output terminals of the interlocking logic gate circuit may also be equipped with a buffer circuit 130, which is implemented by, for example, an inverter.

[0036] Combined with this Figure 4 The influence of the insertion sequence of the I2C bus and the secondary board power supply VDD involved in the example of the embodiment of the present invention on hot plugging and the processing scheme can be specifically described as follows.

[0037] First, the situation where the I2C bus is plugged in but the secondary board power supply VDD is not plugged in.

[0038] In this case, the signal at the I2C bus end passes through the parasitic diode series circuit of the first resistor R1 and the first PMOS tube M1 to the VDD end, and the VDD end is connected to the power supply, showing low impedance, which will cause the I2C bus to be pulled low. Therefore, it is necessary to cut off the current flow path from the I2C bus to the secondary board power supply VDD to prevent the VDD of the secondary board that may not be powered on from pulling the I2C bus down by mistake during the hot plugging process.

[0039] In this regard, Figure 4 In the example of FIG. 1 , the first diode D1 and the second diode D2 are provided to cut off the current flow path between the I2C bus and the secondary board power supply VDD. Specifically, as Figure 5 As shown in the figure, a parasitic diode is formed between the source and drain of the PMOS tube, so Figure 4 In the example, the first diode D1 and the second diode D2 are reversely connected with the parasitic diodes of the corresponding PMOS tubes back to back, so that there is no path between the secondary board power supply VDD and the I2C bus, thereby avoiding the I2C bus being pulled down due to the low impedance of the VDD end when the I2C bus is inserted first.

[0040] Second, the sub-board power supply VDD is plugged in but the I2C bus is not plugged in, that is, the I2C bus is floating.

[0041] In this case, since the slave board power supply VDD is inserted before the I2C bus, the slave board I2C bus input will be suspended. The I2C bus is a bidirectional communication (ie, both input and output), which will produce uncertain output.

[0042] In view of this situation, Figure 4In the example, a specific control circuit 100 and a pull-up circuit 200 are designed to cooperate to solve the problem. Among them, the parameters of some components are configured as follows: the resistance of the first resistor R1 is much smaller than that of the second resistor R2. Preferably, the first resistor R1 is a 1kΩ resistor, the second resistor R2 is a 100kΩ resistor, the third resistor is 1000kΩ, and the capacitor C1 is a 1pF capacitor. Accordingly, when VDD is powered on, the third resistor R3 and the capacitor C1 form a timer with a time constant of 1us, which generates a low level with a pulse width of about 1us through the buffer circuit 130 at the L1 end, so that the I2C bus is pulled up through the 1kΩ resistor path (i.e., the first pull-up sub-circuit 210). If the I2C bus is not inserted, the high-impedance bus is pulled up to high, and the 100kΩ resistor path (i.e., the second pull-up sub-circuit 220) is also turned on through the structure composed of the inverter 400, the L2 end of the interlocking logic gate circuit, and the buffer 130 at the output end L3. After 1us, the timer output returns to high, the 1kΩ resistor pull-up is disconnected, and the I2C bus continues to be pulled up through the 100kΩ resistor path. In this way, until a certain moment after the I2C bus is inserted, the main board pulls the bus down, and the 100kΩ resistor path (i.e., the second pull-up sub-circuit 220) is released through the structure composed of the inverter 400, the L2 end of the interlocking logic gate circuit, and the buffer 130 at the output end L3. That is, from the moment the secondary board is powered on, the hot-swap protection circuit of this example detects the I2C bus signal. If the bus is high impedance, the bus is pulled high until the bus is inserted and pulled to a low level by the main board and then released, so as to prevent the secondary board bus input from being suspended due to the VDD power pin (and / or ground pin) of the secondary board being inserted earlier than the bus pin during the hot-swap process, thereby generating uncertain output.

[0043] It should be noted that for the second situation, if the I2C bus is inserted before the secondary board power supply VDD, the protection will not work. The reason is that the network composed of 1kΩ and 100kΩ resistors can only pull up the suspended bus, but cannot pull up the low bus, so it will not affect the normal function of the I2C bus.

[0044] also, Figure 4 There are also some components that are convenient for processing signals from the control module. Their application is easy to understand for those skilled in the art, and they are less related to the embodiments of the present invention, so they will not be described in detail here.

[0045] In addition, for the sake of bus protection, an ESD (Electrostatic Discharge) protection circuit 500 may be provided at the I2C bus end to prevent the failure of electronic devices caused by ESD phenomena.

[0046] Back to Figure 4, it can be seen that even if the CMOS inverter 400 and the ESD protection circuit 500 are added, the electronic devices connected to the I2C bus include: the drain of the NMOS tube, whose source is grounded; the gates of the NMOS tube and the PMOS tube. It is easy to know that there is no parasitic from the bus to the secondary board VDD in these electronic devices, so the CMOS inverter 400 and the ESD protection circuit 500 will not abnormally pull down or pull up the bus.

[0047] In summary, this example proposes a circuit that can implement hot-swap protection without the need for an ID bus and a monitoring module. It detects the state of the I2C bus after hot-swapping and performs hot-swap protection from two aspects, namely: on the one hand, if the bus is suspended, it will be pulled up to the power supply, and the pull-up capability is weak, which will not affect the motherboard from pulling the bus down; on the other hand, if the power supply is connected after the bus, the current flow path from the bus to the secondary board power supply is cut off, preventing the bus from being mistakenly pulled down through this path during the hot-swap process. It should be noted that the effect of the insertion order of the ground wire GND on hot-swapping is consistent with that of the secondary board power supply VDD, so it will not be repeated here.

[0048] The embodiment of the present invention further provides an interface chip, which is provided with any hot-swap protection circuit in the above embodiment. Figure 6 As shown, the interface chip is arranged on the secondary board.

[0049] The present invention also provides a hot-swap system for an I2C bus, the structure of which is as follows: Figure 6 As shown, it includes a main board and a secondary board for realizing data communication through an I2C bus, and the secondary board is provided with the above-mentioned interface chip and control module. Among them, the interaction between the hot-swap protection circuit in the interface chip and the control module can be referred to Figure 4 The control module connects the interface chip and the I2C device to control the communication associated with the I2C bus. For example, the control module controls the I2C device to power on the device, load the device driver, etc. when both the VDD terminal and the I2C bus terminal are correctly connected, and can also control the initialization of the I2C bus and the driver loading.

[0050] It should be noted that, for more implementation details and effects of the interface chip and the hot-swap system, reference may be made to the above-mentioned embodiments of the hot-swap protection circuit, which will not be described in detail here.

[0051] It should also be noted that the terms "include", "comprises" or any other variations thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of more restrictions, the elements defined by the sentence "comprises a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0052] The above are only embodiments of the present application and are not intended to limit the present application. For those skilled in the art, the present application may have various changes and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application should be included within the scope of the claims of the present application.

Claims

1. A hot-swap protection circuit for an I2C bus, characterized in that: The invention comprises a control circuit (100), a pull-up circuit (200) and a cut-off circuit (300), wherein two input ends of the control circuit (100) are respectively connected to an I2C bus and a secondary board power supply VDD, and an output end is connected to a first input end of the pull-up circuit (200); an input end of the cut-off circuit (300) is connected to the secondary board power supply VDD, and an output end is connected to a second input end of the pull-up circuit (200); and an output end of the pull-up circuit (200) is connected to the I2C bus; The control circuit (100) is configured to, when the secondary board power supply VDD is inserted first, turn on the pull-up circuit (200) at a set time, so as to pull up the suspended I2C bus through the pull-up circuit (200); The cut-off circuit (300) is configured to cut off the current inflow path formed by the pull-up circuit (200) between the secondary board power supply VDD and the I2C bus when the I2C bus is inserted first; Wherein, the control circuit (100) comprises a timing circuit (110) and a switch circuit (120) which are sequentially connected between the secondary board power supply VDD and the pull-up circuit (200); The pull-up circuit (200) comprises a first pull-up sub-circuit (210) and a second pull-up sub-circuit (220) which are arranged in parallel between the I2C bus and the cut-off circuit (300), and the first pull-up sub-circuit (210) is directly connected to the timing circuit (110), and the second pull-up sub-circuit (220) is connected to the timing circuit (110) via the switch circuit (120); The timing circuit (110) is configured to: when the secondary board power supply VDD is inserted first, turn on the first pull-up sub-circuit (210) and turn on the second pull-up sub-circuit (220) through the switch circuit (120) within the set time; and after the set time, turn off the first pull-up sub-circuit (210) and drive the switch circuit (120) to maintain the conduction of the second pull-up sub-circuit (220).

2. The hot-swap protection circuit according to claim 1, characterized in that: The cut-off circuit (300) comprises a first circuit breaker (310) connected to the first pull-up sub-circuit (210) and a second circuit breaker (320) connected to the second pull-up sub-circuit (220), and when the first pull-up sub-circuit (210) and the second pull-up sub-circuit (220) each have an internal parasitic diode, the first circuit breaker (310) and the second circuit breaker (320) are respectively diodes that are reversely connected to the corresponding parasitic diodes.

3. The hot-swap protection circuit according to claim 2, characterized in that: The first circuit breaker (310) and the second circuit breaker (320) are respectively a first diode D1 and a second diode D2; The first pull-up sub-circuit (210) comprises a first resistor R1 and a first PMOS transistor M1, one end of the first resistor R1 is connected to the I2C bus, and the other end is connected to the drain of the first PMOS transistor M1, the gate of the first PMOS transistor M1 is connected to the timing circuit (110), and the source of the first PMOS transistor M1 is connected to the secondary board power supply VDD via the first diode D1; The second pull-up sub-circuit (220) comprises a second resistor R2 and a second PMOS transistor M2, one end of the second resistor R2 is connected to the I2C bus, and the other end is connected to the drain of the second PMOS transistor M2, the gate of the second PMOS transistor M2 is connected to the timing circuit (110) via the switch circuit (120), and the source of the second PMOS transistor M2 is connected to the secondary board power supply VDD via the second diode D2; The anodes of the first diode D1 and the second diode D2 are connected to the secondary board power supply VDD, and the cathodes are connected to the source of the corresponding PMOS tube.

4. The hot-swap protection circuit according to claim 3, characterized in that: The resistance of the first resistor R1 is smaller than that of the second resistor R2.

5. The hot-swap protection circuit according to claim 1, characterized in that: The timing circuit (110) comprises: a third resistor R3 and a capacitor C1, wherein one end of the third resistor R3 is connected to the secondary board power supply VDD, and the other end is connected to one end of the capacitor C1, the other end of the capacitor C1 is grounded, and the output end of the timing circuit (110) is led out from the connection line between the third resistor R3 and the capacitor C1.

6. The hot-swap protection circuit according to claim 1, characterized in that: The switch circuit (120) adopts an interlocking logic gate circuit, and the two input ends of the interlocking logic gate circuit are respectively connected to the output end of the timing circuit (110) and the I2C bus.

7. An interface chip, characterized in that: A hot-swap protection circuit as claimed in any one of claims 1 to 6 is provided.

8. A hot-swap system for an I2C bus, characterized in that: It comprises a main board and a sub-board for realizing data communication via an I2C bus, and the interface chip according to claim 7 is arranged on the sub-board.

9. The hot-swap system according to claim 8, characterized in that: The secondary board is also provided with a control module, which is connected to the interface chip and the I2C device and is used to control the communication associated with the I2C bus.

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