A nitride semiconductor device and a method of fabricating the same

Abstract

The application particularly relates to a nitride semiconductor device and a preparation method thereof, the main improvement of the nitride semiconductor device is that electrical isolation is realized through a first insulating structure on a nitride semiconductor film and a deep groove type second insulating structure opened from the back surface of a substrate to the front surface direction, the nitride semiconductor device can continue to use the existing silicon-based GaN epitaxial technology, does not use a relatively expensive SOI substrate, and can complete the preparation of the device and achieve a good isolation effect, the back surface deep groove can be aligned with a scribe lane, area is saved, a slicing yield is improved, and the use of a SiO2 buried layer with low thermal conductivity is avoided, and the heat dissipation capacity of the substrate is ensured.

Description

Technical Field

[0001] This invention relates to the field of gallium nitride power devices, and more specifically to a nitride semiconductor device and its fabrication method. Background Technology

[0002] GaN high electron mobility transistors (HMTs) offer higher power density, switching frequency, and operating temperature than traditional Si power transistors, and have been applied in power conversion applications such as fast charging, photovoltaic inverters, and on-board charging power supplies. Currently, the GaN power device market is dominated by discrete devices, and there is a strong desire to monolithically integrate drive circuits, control circuits, and sensing circuits with GaN power devices to reduce parasitic effects caused by interconnects and thus reduce parasitic losses.

[0003] The half-bridge circuit is the most important unit in power integrated circuits. It consists of the source of the upper power device and the drain of the lower power device connected in series (see [link]). Figure 1 If the upper and lower MOSFETs are monolithically integrated, they must be electrically isolated to avoid crosstalk during switching, which would affect the system's stability and reliability. Commercial GaN power devices are fabricated on conductive Si substrates. If both the upper and lower MOSFETs are fabricated on a conductive Si substrate, a back-gate effect will inevitably occur, leading to a decrease in output current (see...). Figure 2 Therefore, electrical isolation between the upper and lower transistors in a half-bridge circuit is the primary problem to be solved in realizing a GaN monolithic integrated power chip. Summary of the Invention

[0004] Based on this, one of the objectives of the present invention is to provide a nitride semiconductor device that does not require the use of an expensive SOI substrate, achieves electrical isolation through two interconnected insulating structures, has good isolation effect, and the deep trench type second insulating structure can be aligned with the scribing track, saving area and improving the slicing yield.

[0005] The present invention achieves the above-mentioned technical objectives through the following technical solution: a nitride semiconductor device, comprising a substrate, a nitride semiconductor thin film formed on the front side of the substrate, an upper transistor and a lower transistor fabricated on the nitride semiconductor thin film, wherein the upper transistor and the lower transistor are electrically isolated from each other through a first insulating structure and a second insulating structure;

[0006] The first insulating structure is a channel isolation region located on a nitride semiconductor thin film, and the second insulating structure is a deep trench opened from the back side of the substrate toward the front side, the deep trench being connected to the channel isolation region.

[0007] In a preferred embodiment, the device further includes a dielectric layer A, which is deposited on the front side of the device.

[0008] In a preferred embodiment, the deep trench passes through the channel isolation zone and connects to the dielectric layer A.

[0009] In a preferred embodiment, the device further includes a dielectric layer B, which is deposited on the back side of the substrate and in a deep trench.

[0010] In a preferred embodiment, the device further includes a metal layer deposited on the dielectric layer B and in the deep trench.

[0011] In a preferred embodiment, both the upper transistor and the lower transistor include a gate, a source, and a drain, with the source electrically connected to the substrate, and the source of the upper transistor and the drain of the lower transistor electrically connected.

[0012] In a preferred embodiment, the substrate is a conductive substrate or a composite substrate comprising an n-type conductive layer and a p-type conductive layer.

[0013] A second objective of this invention is to provide a method for obtaining a nitride semiconductor device with the above-described structure, comprising the following steps:

[0014] A nitride semiconductor thin film is epitaxially grown on the front side of a substrate to fabricate an upper transistor and a lower transistor for a power device;

[0015] A first insulating structure is fabricated on a nitride epitaxial film between the upper transistor and the lower transistor;

[0016] A second insulating structure is fabricated by creating a deep trench on the back side of the substrate, and the deep trench is connected to the first insulating structure.

[0017] In a preferred embodiment, after the first insulating structure is prepared, the process further includes the steps of temporarily bonding a carrier substrate and thinning the substrate to a preset thickness, wherein the carrier substrate is bonded to the front side of the device.

[0018] In a preferred embodiment, the method further includes the steps of sequentially depositing a dielectric layer B and a metal layer and removing the substrate after the second insulating structure is fabricated.

[0019] As a preferred embodiment, the preparation method of the first insulating structure includes, but is not limited to, ion implantation and trenching.

[0020] In a preferred embodiment, the method further includes a step of depositing a dielectric layer A between the upper transistor and the lower transistor after the transistor fabrication is completed.

[0021] In a preferred embodiment, the method further includes the steps of forming deep metal holes in the dielectric layer A and the nitride epitaxial film to electrically connect the sources of the upper transistor and the lower transistor to the substrate, and to electrically connect the sources of the upper transistor and the drains of the lower transistor.

[0022] Using the method described in this invention, the device can be fabricated using a common substrate and achieve a good isolation effect. It can also avoid the problems of reduced chip usable area and increased interconnect length between upper and lower transistors caused by the large size of the front deep trench. It has good advantages in terms of cost, isolation effect and manufacturability. Attached Figure Description

[0023] Figure 1 This is a schematic diagram of the principle structure of a half-bridge circuit;

[0024] Figure 2 A schematic diagram of the structure of a power device fabricated on a floating substrate and the test results of the back gate effect, wherein (a) is a schematic diagram of the structure of a power device fabricated on a floating substrate and with the lower source electrode grounded and the test results of the back gate effect, and (b) is a schematic diagram of the structure of a power device fabricated on a grounded substrate and the test results of the back gate effect.

[0025] Figure 3 The diagram shows a cross-sectional view of a gallium nitride half-bridge circuit and chip based on PN junction isolation, as well as a back gate effect test structure. (a) is a schematic diagram of the structure, and (b) is the back gate effect test result.

[0026] Figure 4 This is a schematic diagram of the structure of the power device prepared according to the present invention;

[0027] Figure 5 This is a longitudinal cross-sectional schematic diagram of another structure of the power device prepared according to the present invention;

[0028] Figure 6 This is a schematic diagram of the structure after the upper and lower tubes are manufactured in step S1 of Example 1;

[0029] Figure 7 This is a schematic diagram of the structure after temporarily bonding the substrate and thinning the substrate in step S2 of Example 1;

[0030] Figure 8 This is a schematic diagram of the structure after the deep trench is fabricated in step S3 of Example 1;

[0031] Figure 9 This is a schematic diagram of the structure after the dielectric layer B is deposited in step S4 of Example 1;

[0032] Figure 10 This is a schematic diagram of the structure after the back metal layer deposition is completed in step S5 of Example 1;

[0033] Figure 11 This is a schematic diagram of the cross-sectional structure of the power device after the substrate is removed in step S6 of Example 1.

[0034] Figure 12 This is a schematic diagram of the cross-sectional structure of the power device after packaging in step S7 of Example 1;

[0035] The attached diagram lists the components represented by each number as follows:

[0036] 1 Substrate, 2 Nitride semiconductor thin film, 3 Dielectric layer A, 4 Dielectric layer B, 5 Metal layer, 6 First insulating structure, 7 Second insulating structure, 8 First countersunk hole, 9 Second countersunk hole, 10 Carrier substrate, 11 Bonding adhesive, 12 Encapsulating adhesive. Detailed Implementation

[0037] To achieve electrical isolation between the upper and lower transistors in a half-bridge circuit, existing research has proposed... <111> GaN epitaxial structures are grown on SOI substrates with different crystal orientations, and GaN half-bridge circuits are fabricated simultaneously. Electrical isolation is achieved by creating a deep trench between the upper and lower transistors that connects to the SiO2 buried layer in the SOI substrate and filling it with dielectric material. The source is also connected to the p-type conductive Si layer on the SiO2 buried layer through a metal deep hole, achieving equipotential between the source of the upper and lower transistors and the substrate, thereby completely eliminating the back gate effect. The main disadvantages of this monolithic GaN integration technology based on SOI substrates are: (1) SOI substrates are more expensive than traditional conductive Si substrates; (2) Due to the low thermal conductivity of the SiO2 buried layer, the heat dissipation of the substrate is reduced; (3) The SiO2 buried layer in SOI increases the substrate capacitance, thereby increasing parasitic losses; (4) Increasing the thickness of the SiO2 buried layer can increase the voltage withstand capability of the isolation structure or reduce the substrate capacitance, but thicker SiO2 further increases thermal stress and substrate thermal resistance.

[0038] A university of science and technology proposed a PN junction-based isolation scheme: A high-resistivity (400 Ω·cm) n-type Si substrate is used, with boron implanted on the surface to form a 3–4 μm thick heavily doped p-type conductive layer. Then, GaN epitaxial structures are grown on this substrate to fabricate the upper and lower GaN half-bridge devices. A deep trench is created between the upper and lower devices, penetrating the p-type conductive layer and extending into the n-type substrate, and then filled with a dielectric. The sources of both the upper and lower devices are connected to the p-type conductive layer through deep metal vias to eliminate the back-gate effect. See details [link to relevant documentation]. Figure 3This creates a back-to-back PN junction between the sources of the upper and lower transistors, achieving electrical isolation through the PN junction barrier. Furthermore, the drain of the upper transistor is connected to the p-type conductive layer of the substrate via a deep metal via. Therefore, the drains of both the upper and lower transistors form a PNP structure with their respective sources through one side of the substrate, thus achieving avalanche breakdown capability for both transistors and protecting GaN power devices. The advantages of this technique are: inexpensive substrate, low substrate capacitance, and avalanche breakdown capability. However, its defects are: (1) A parasitic BJT transistor structure of PNP is formed between the back electrode of the substrate and the source of the upper and lower transistors. The leakage current of the upper and lower transistors may be amplified by the parasitic BJT transistor; (2) The front deep trench is large in size (50-80μm wide), which occupies chip area on the one hand and increases the length of the interconnect line between the upper and lower transistors on the other hand, thereby increasing the parasitic effect. Its depth is also deep (40-80μm). The isolation effect of the upper and lower transistors is closely related to the depth of the deep trench. If the trench is too shallow, it will not achieve a good isolation effect. For higher withstand voltages above 650V, the required trench depth and width will be larger.

[0039] In view of the problems existing in the current electrical isolation technology between the upper and lower transistors in half-bridge circuits, the present invention provides a nitride semiconductor device that can be fabricated using a common substrate and can achieve a good isolation effect. It can also avoid the problems of reduced chip usable area and increased interconnect length between the upper and lower transistors caused by the large front trench size. It has good advantages in terms of cost, isolation effect and manufacturability.

[0040] To facilitate understanding of this application, a more complete description will be provided below with reference to the accompanying drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein.

[0041] This invention provides a nitride semiconductor device, such as... Figure 4 , 5 As shown, it includes a substrate 1, a nitride semiconductor thin film 2 formed on the front side of the substrate 1, an upper transistor and a lower transistor fabricated on the nitride semiconductor thin film 2, and the upper transistor and the lower transistor are electrically isolated from each other by a first insulating structure 6 and a second insulating structure 7.

[0042] The first insulating structure 6 is a channel isolation region located on the nitride semiconductor thin film 2, and the second insulating structure 7 is a deep trench opened from the back side of the substrate 1 toward the front side, and the deep trench is connected to the channel isolation region, so that the two achieve electrical isolation between the upper transistor and the lower transistor.

[0043] The nitride semiconductor device provided by this invention is based on the traditional GaN process on a low-resistivity silicon substrate. It uses a deep trench on the back side to achieve electrical isolation. It can continue to use the existing Si-based GaN epitaxial technology without using the relatively expensive SOI substrate. The deep trench on the back side can be aligned with the scribing trace, saving area and improving the slicing yield. Furthermore, this semiconductor device can avoid using SiO2 buried layers with low thermal conductivity, ensuring better heat dissipation of the substrate.

[0044] Furthermore, the semiconductor device also includes a dielectric layer A3, which is deposited on the front side of the device, i.e., the surface of the upper transistor and the lower transistor.

[0045] In this invention, the deep trench is connected to the channel isolation region. It can be opened to the channel isolation region, or it can pass through the channel isolation region and be connected to the dielectric layer A3 (including the case of simultaneously penetrating the channel isolation region and the dielectric layer A3. When it is a structure that penetrates the dielectric layer A3, it can include two interconnected parts. One part is obtained by slotting downward from the dielectric layer A3 and filling it with insulating material, and the other part is obtained by slotting from the back side of the substrate 1 towards the front side), to ensure better isolation effect.

[0046] Understandably, dielectrics can be further deposited in the deep trenches, which can achieve better isolation while ensuring the mechanical strength of the substrate.

[0047] Furthermore, those skilled in the art will understand that the deep trench structure is not limited to a simple trench structure; for example, its longitudinal section can also be a trapezoidal structure. Additionally, the deep trench can extend downwards towards the drain of the lower transistor on the substrate layer, forming a stepped deep trench. See [link to relevant documentation] for details. Figure 5 As shown.

[0048] Furthermore, the semiconductor device also includes a dielectric layer B4, which is deposited on the back side of the substrate 1 and in the deep trench. Here, the dielectric layer B4 can be made of a material with high thermal conductivity, such as AlN, to ensure good heat dissipation of the entire device.

[0049] Furthermore, the semiconductor device also includes a metal layer 5, which is deposited on the dielectric layer B 4 and in the deep trench to increase heat dissipation and wafer mechanical strength.

[0050] It is understood that the upper transistor and the lower transistor described in this application both include a gate, a source, and a drain. The source of each transistor is electrically connected to the substrate 1. The source of the upper transistor and the drain of the lower transistor are electrically connected to form a half-bridge circuit.

[0051] For details, see Figure 4The upper transistor includes a second gate G2, a second source S2, and a second drain D2, and the lower transistor includes a first gate G1, a first source S1, and a first drain D1. The first source S1 is electrically connected to the substrate 1 through a first recessed via 8, the second source S2 is electrically connected to the substrate 1 through a second recessed via 9, and the first drain D1 is connected to the second source S2 through the second recessed via 9.

[0052] In this application, the preparation method of the first insulating structure 6 includes, but is not limited to, ion implantation and trenching, with ion implantation being preferred. Using ion implantation to form a trench isolation region as the first insulating structure 6 results in better overall device strength.

[0053] In this application, substrate 1 can be a conductive substrate or a composite substrate containing an n-type conductive layer and a p-type conductive layer. When a composite substrate containing an n-type conductive layer and a p-type conductive layer is used, the parasitic capacitance of the substrate can be reduced.

[0054] The present invention also provides a method for fabricating the above-mentioned nitride semiconductor device, comprising the following steps:

[0055] A nitride semiconductor thin film 2 is epitaxially grown on the front side of substrate 1 to fabricate an upper transistor and a lower transistor for a power device;

[0056] A first insulating structure 6 is fabricated on a nitride epitaxial film 2 between the upper transistor and the lower transistor;

[0057] A deep trench is formed on the back side of the substrate 1 to create a second insulating structure 7, and the deep trench is connected to the first insulating structure 6.

[0058] The method further includes a step of temporarily bonding the carrier substrate 10 and thinning the substrate 1 after the first insulating structure 6 is fabricated, wherein the carrier substrate 10 is bonded to the front side of the device. That is, after temporarily bonding the carrier substrate 10 to the front side of the device, the substrate 1 is thinned to a preset thickness.

[0059] Furthermore, it also includes the steps of sequentially depositing dielectric layer B4 and metal layer 5 after the second insulating structure is fabricated, and removing the substrate 10.

[0060] Furthermore, it also includes the steps of depositing a dielectric layer A3 between the upper transistor and the lower transistor after the transistor fabrication is completed, and the steps of forming deep metal holes in the dielectric layer A3 and the nitride epitaxial film 2 to electrically connect the sources of the upper transistor and the lower transistor to the substrate 1, and to electrically connect the sources of the upper transistor and the drains of the lower transistor.

[0061] To make the technical solution of this application clearer, a further detailed description is provided below with reference to two specific embodiments. It should be explained that the purpose of providing these embodiments is to make the disclosure of this application more thorough and comprehensive, and not to limit the invention. Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used in this specification is only for describing specific embodiments and is not intended to limit the application.

[0062] Example 1

[0063] This embodiment provides a method for fabricating a nitride semiconductor device. Specifically, a first insulating structure is fabricated on a nitride semiconductor thin film epitaxially grown on the front side of a conventional conductive substrate, and a deep trench is fabricated on the back side of the substrate as a second insulating structure, which is then filled with a dielectric and a high thermal conductivity material to achieve electrical isolation of the GaN device on the Si substrate. The method includes the following steps:

[0064] S1, the upper transistor (referred to as the upper transistor) and the lower transistor (referred to as the lower transistor) of the power device are fabricated on the front side of substrate 1: In <111> A nitride semiconductor epitaxial thin film 2 is grown on a conventional conductive Si substrate 1. Upper and lower power devices are fabricated on the nitride semiconductor epitaxial thin film 2. A channel isolation region (i.e., a first insulating structure, which can be achieved through ion implantation) exists between the upper and lower devices on one side of the epitaxial thin film. A dielectric layer A3 is deposited on the surface of the upper and lower devices. The source, drain, and gate electrodes are all led out of the surface of the dielectric layer A3 through metal vias. The sources of the lower and upper devices are connected to the conductive substrate 1 through a first deep hole 8 and a second deep hole 9. The drain of the lower device is connected to the source of the upper device through the second deep hole 9, forming a half-bridge circuit. See [link to specific structure] for details. Figure 6 .

[0065] S2, Temporary Bonding of Carrier Substrate 10 and Substrate Thinning: The gallium nitride wafer is temporarily bonded to the carrier substrate 10 using bonding adhesive 11 (e.g., high-melting-point paraffin). The conductive Si substrate is then thinned to approximately 100–300 μm using mechanical polishing or wet etching. See [link to previous section] Figure 7 .

[0066] S3, Fabrication of the second insulating structure 7: Deep silicon etching is used on the back side of the conductive Si substrate 1 to penetrate the nitride semiconductor epitaxial film 2 and connect to the front dielectric layer A 3. A deep silicon trench is fabricated around the lower or upper transistor to completely surround it, physically isolating the substrates of the upper and lower transistors. The trench can be placed in the dicing channel, saving usable wafer area on the front side. See [reference needed]. Figure 8 .

[0067] S4, deposit a dielectric layer B4 on the back side to fill the deep trench: the dielectric is a material with high thermal conductivity, such as AlN, see [reference needed]. Figure 9 .

[0068] S5, Deposit backside metal layer 5 to fill the deep trench: Deposit metal on the backside using sputtering or electroplating processes to increase heat dissipation and wafer mechanical strength. See [link to relevant documentation] Figure 10 .

[0069] S6, remove the substrate 10 and temporary bonding adhesive 11 to form a gallium nitride power half-bridge circuit with deep trench isolation on the back side. See [link to relevant documentation]. Figure 11 .

[0070] S7, the device has a routing layer (RDL) and solder bumps on the front side, and is encapsulated with plastic 12 on the back side to form a wafer-level chip package (WLCSP).

[0071] The structure of the gallium nitride power device prepared according to the above method is as follows: Figure 12 As shown.

[0072] Example 2

[0073] This embodiment provides another method for fabricating a gallium nitride (GaN) power device. The difference between this GaN power device and the GaN power device in Embodiment 1 lies in the structure of the second insulating structure 7. In fabricating the second insulating structure 7, the substrate below the lower transistor drain is removed by two etching processes, followed by the deposition of dielectric and metal. This structure can reduce substrate leakage current and increase the device's breakdown voltage. The specific fabrication method is as follows:

[0074] S1, the upper transistor (referred to as the upper transistor) and the lower transistor (referred to as the lower transistor) of the power device are fabricated on the front side of substrate 1: In <111> A nitride semiconductor epitaxial thin film 2 is grown on a conventional conductive Si substrate 1. Upper and lower power devices are fabricated on the outer nitride semiconductor epitaxial thin film 2. A channel isolation region (i.e., the first insulating structure, which can be achieved by ion implantation) exists between the upper and lower devices on one side of the epitaxial thin film. A dielectric layer A3 is deposited on the surface of the upper and lower devices. The source, drain, and gate electrodes are all led out of the surface of the dielectric layer A3 through metal holes on the dielectric layer A3. The source of the lower and upper devices is connected to the conductive substrate 1 through a first deep hole 8 and a second deep hole 9. The drain of the lower device is connected to the source of the upper device through the second deep hole 9, forming a half-bridge circuit.

[0075] S2, Temporary bonding carrier substrate 10 and substrate thinning: The gallium nitride wafer is temporarily bonded to the carrier substrate 10 by bonding adhesive 11 (e.g., high melting point paraffin), and the conductive Si substrate is thinned to about 100-300 μm by mechanical grinding or wet etching.

[0076] S3, Fabrication of the second insulating structure 7: A deep trench structure is etched from the back side of the substrate to the front side of the substrate. Part of the etching only extends to the bottom surface of the nitride semiconductor thin film structure below the drain region of the lower transistor, while the other part extends into the interior of the first insulating structure, as detailed below:

[0077] S3-1, a deep silicon etching process is used on the back side of the conductive Si substrate 1 to penetrate the nitride semiconductor epitaxial film 2 and connect to the front dielectric layer A3. A silicon deep trench is made around the lower or upper tube to completely surround the upper or lower tube, physically separating the substrates of the upper and lower tubes. The deep trench can be placed in the dicing channel, which can save the wafer area available on the front side.

[0078] S3-2, the conductive silicon substrate under the drain of the lower transistor is removed by etching. The groove formed after the conductive silicon substrate is removed is connected to the deep trench, that is, the deep trench of the second insulating structure is a stepped deep trench.

[0079] S4, deposit a dielectric layer B4 on the back side to fill the deep trench: the dielectric is a material with high thermal conductivity, such as AlN.

[0080] S5, depositing back metal layer 5 to fill deep trench: depositing metal on the back side through sputtering or electroplating processes to increase heat dissipation and wafer mechanical strength.

[0081] S6, remove the substrate 10 and temporary bonding adhesive 11 to form a gallium nitride power half-bridge circuit with back-side deep-hole isolation.

[0082] The structure of the gallium nitride power device prepared according to the above method is as follows: Figure 5 As shown.

[0083] It should also be noted that the illustrations and descriptions of embodiments in this application are illustrative rather than restrictive. The same reference numerals throughout the embodiments identify the same structures. Additionally, for the sake of understanding and ease of description, the thicknesses of some layers, films, panels, regions, etc., may be exaggerated in the illustrations. It is also understood that when an element such as a layer, film, region, or substrate is referred to as being "on" another element, the element may be directly on the other element or there may be intermediate elements. Furthermore, "on" means positioning an element on or below another element, but does not inherently mean positioning it above another element according to the direction of gravity.

[0084] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the protection scope of the present invention.

Claims

1. A nitride semiconductor device, characterized in that, Includes a substrate (1), a nitride semiconductor thin film (2) formed on the front side of the substrate (1), an upper transistor and a lower transistor fabricated on the nitride semiconductor thin film (2), wherein the upper transistor and the lower transistor are electrically isolated from each other by a first insulating structure (6) and a second insulating structure (7); The first insulating structure (6) is a channel isolation region located on the nitride semiconductor thin film (2), and the second insulating structure (7) is a deep trench opened from the back side of the substrate (1) toward the front side, and the deep trench is connected to the channel isolation region; The deep trench is a stepped deep trench, which extends downwards towards the drain of the lower transistor on the substrate (1). It also includes a dielectric layer B (4), which is deposited on the back side of the substrate (1) and in the deep trench; It also includes a metal layer (5) deposited on the dielectric layer B (4) and in the deep trench.

2. The nitride semiconductor device according to claim 1, characterized in that, It also includes a dielectric layer A (3), which is deposited on the front side of the device.

3. The nitride semiconductor device according to claim 2, characterized in that, The deep trench passes through the channel isolation zone and connects to the dielectric layer A (3).

4. The nitride semiconductor device according to claim 1, characterized in that, Both the upper transistor and the lower transistor include a gate, a source, and a drain. The source of each transistor is electrically connected to the substrate (1). The source of the upper transistor and the drain of the lower transistor are electrically connected.

5. The nitride semiconductor device according to claim 1, characterized in that, The substrate is a conductive substrate or a composite substrate containing an n-type conductive layer and a p-type conductive layer.

6. A method for fabricating a nitride semiconductor device according to any one of claims 1 to 5, characterized in that, Includes the following steps: A nitride semiconductor thin film (2) is epitaxially grown on the front side of a substrate (1) and an upper transistor and a lower transistor of a power device are fabricated. A first insulating structure (6) is prepared on a nitride epitaxial film (2) between the upper transistor and the lower transistor. A deep trench is formed on the back side of the substrate (1) to create a second insulating structure (7) and the deep trench is connected to the first insulating structure (6).

7. The method for fabricating a nitride semiconductor device according to claim 6, characterized in that, After the first insulating structure is prepared, the process also includes the steps of temporarily bonding a substrate (10) and thinning the substrate (1) to a preset thickness, wherein the substrate (10) is bonded to the front side of the device.

8. The method for fabricating a nitride semiconductor device according to claim 6 or 7, characterized in that, It also includes the steps of sequentially depositing dielectric layer B (4) and metal layer (5) and removing substrate (10) after the second insulating structure is fabricated.

9. The method for fabricating a nitride semiconductor device according to claim 6, characterized in that, The preparation method of the first insulating structure includes ion implantation or trenching.

Images