A TDI-CMOS image detector with finely adjustable charge accumulation levels
By designing the second doped region gate structure in the TDI-CMOS image detector and performing timing control, fine adjustment of charge accumulation series is achieved, the problem of not fine adjustment of series in the prior art is solved, and image quality is improved and signal-to-noise ratio.
Patent Information
- Application Number
- CN202310870327.3
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- Filing Date
- 2023-07-14
- Publication Date
- 2024-12-24
- Estimated Expiration
- 2043-07-14
AI Technical Summary
Existing TDI-CMOS image detectors are difficult to achieve fine adjustments when adjusting the charge accumulation series, especially in bright scenes. The image changes too much after the series is adjusted, and the digital gain method will increase noise, making it impossible to achieve optimal signal noise. Compare.
By designing the second doped region gate structure within the pixel unit and performing timing control, fine adjustment of the charge accumulation amount is allowed, non-integer multiple charge accumulation and output are achieved, noise is reduced, and image quality is improved.
The fine adjustment of the series of TDI-CMOS image detectors is achieved, the image quality is optimized, the image is avoided too bright or too dark, the signal-to-noise ratio is improved, and the complexity of subsequent information processing is reduced.
Smart Images
Figure CN117038684B_ABST
Abstract
Description
Technical Field
[0001] The invention relates to a TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages, belonging to the technical field of image detection. Background Art
[0002] Image detectors play an extremely important role in cameras. The performance of image detectors plays a decisive role in the quality of images. Image detector TDI (Time Delay Integration) technology is a method of delayed integration for multiple exposures of the same target, which greatly improves the ability to collect light energy. It has the advantages of high responsiveness, low noise, and wide dynamic range. It can also output signals with a certain signal-to-noise ratio in dark scenes, and plays an important role in industrial detection and environmental monitoring.
[0003] TDI technology was first applied to CCD (Charge Couple Device) image detectors, namely TDI-CCD image detectors. However, since the process of CCD image detectors is different from the mass-produced CMOS process, a large number of CMOS (Complementary Metal Oxide Semiconductor) circuits cannot be directly integrated. With the development of CMOS image detectors, the advantages of CCD and CMOS are combined, and a new type of TDI-CMOS image detector is developed.
[0004] TDI image detectors generally have multiple levels. By selecting different levels, the brightness of the image acquired at different brightness levels can be adjusted to achieve the best image quality. Whether it is the early TDI-CCD image detector or the latest TDI-CMOS image detector, when adjusting the level, it is adjusted in integer multiples. However, due to the complex working conditions of the camera, it is difficult to obtain the best image by adjusting different levels in some environments. Especially for brighter scenes, the required level is relatively small. Although the brightness of the output image can be adjusted by adjusting the level, the image before and after the level adjustment varies greatly. Too bright or too dark cannot reach the state of understanding. Alternatively, the digital gain method is used for adjustment, which is equivalent to increasing the noise of the output image, and the signal-to-noise ratio of the image will not be improved. Therefore, in order to achieve better image quality, a TDI image detector that can finely adjust the charge accumulation level becomes very important, but no TDI image detector that can achieve this capability has been found. Summary of the invention
[0005] The technical problem solved by the present invention is: to overcome the shortcomings of the prior art and propose a TDI-CMOS image detector that can finely adjust the charge accumulation level, and to meet higher requirements for image quality in industrial detection, environmental monitoring, etc. through the structural design and timing control of the gate structure of the second doping area in the pixel unit.
[0006] The technical solution of the present invention is:
[0007] A TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages, comprising a substrate and a plurality of identical pixel units located in the substrate;
[0008] The pixel units each include three non-overlapping doping regions, the first doping region does not contact the second doping region, and the distance between the third doping region and the second doping region is smaller than the distance between the third doping region and the first doping region; the three doping regions each contain ions, and the ion conductivity type in the third doping region is opposite to the ion conductivity type in the first doping region;
[0009] A plurality of gate structures and metal interconnection layers are provided on the surface of the first doped region, a gate structure and a metal interconnection layer are provided on the surface of the second doped region, and interconnection metal is provided on the top of the third doped region; the amount of charge accumulation of the current pixel unit is adjusted by controlling the voltage and timing of the gate structure of the second doped region.
[0010] Preferably, several pixel units are arranged along the charge transfer direction of the TDI-CMOS image detector, the first doping regions in all pixel units are connected together, the second doping regions are separated from each other, and the third doping regions are separated from each other; the interconnection metals on the third doping regions of each pixel unit are connected together and connected to an external power supply, and the gate structure and interconnection metals on the second doping regions of each pixel unit are not connected and are respectively connected to the timing control circuit.
[0011] Preferably, several pixel units are arranged along the length direction of the TDI-CMOS image detector, and the gate structures with the same name located in the first doping region on all pixel units are interconnected together through gates or metals, and are respectively connected to the timing control circuit; in each row, the gate structures located in the second doping region on all pixel units are interconnected together through gates or metals, and are respectively connected to the timing control circuit.
[0012] Preferably, the first doping region, the second doping region and the third doping region are arranged in parallel along a direction perpendicular to the charge transfer direction and parallel to the substrate surface, and the size of the first doping region is larger than the size of the second doping region and the size of the third doping region.
[0013] Preferably, the amount of charge accumulation of the current pixel unit is adjusted by performing voltage and timing control on the gate structure of the second doping region, including:
[0014] When the gate voltage of the gate structure on the second doping region is low, a potential barrier is formed under the gate to prevent the charge in the pixel unit from being discharged, and the charge in the pixel unit is accumulated. According to the timing change of the multiple gates on the first doping region, the accumulated charge under the gate on the first doping region is moved and transferred to the next pixel unit along the charge transfer direction;
[0015] When the gate voltage of the gate structure on the second doping region is high, the charges in the pixel unit will flow into the external power supply through the channel under the gate, and the charges in the pixel unit will be discharged. At this time, all the charges in the pixel unit are cleared;
[0016] In a row transfer cycle, the gate voltage on the second doped region is first high and then low. The ratio of the amount of charge accumulated in the pixel unit to the amount of charge accumulated when the gate voltage on the second doped region is always low is the ratio of the time when the gate voltage on the second doped region is low in this row transfer cycle to the entire row transfer cycle.
[0017] Preferably, when reverse charge accumulation is to be performed, the order of signals on the plurality of gate structures on the first doped region should be opposite to that during forward charge accumulation.
[0018] Preferably, if there are m pixel units arranged along the charge transfer direction of the TDI-CMOS image detector, the selected level is n, n≤m, the charges from the nth level pixel units to the 1st level pixel units are accumulated and output, while the charges generated from the n+1th level to the mth level pixel units do not participate in the accumulation and output; if the charge accumulation direction is the opposite direction of the above, the charges from the nth level to the mth level are accumulated and output, while the charges from the n-1th level to the 1st level do not participate in the accumulation and output, and the number of levels actually participating in the accumulation is m-n+1 levels.
[0019] Preferably, it is required to output all accumulated signals of level n, and the timing control method is: apply a low level to the second doping region gate structure on all pixel units of level n and below, and apply a high level to the second doping region gate structure on the pixel unit of level n+1.
[0020] Preferably, through fine adjustment, that is, applying a low level to the second doping region gate structure on all pixel units of level n-1 and below, and applying a high level to the second doping region gate structure on the pixel unit of level n+1, the duty cycle of the high level applied to the second doping region gate structure in the nth level is controlled, so that the range of the output charge accumulation amount is greater than or equal to level n-1 and less than or equal to level n.
[0021] Preferably, the gate voltages of the second doping regions of all pixel units greater than level n are set to a high level to better remove useless charges.
[0022] The advantages of the present invention compared with the prior art are:
[0023] (1) The present invention can precisely control the charge collection amount of the highest-level pixel unit under the selected level by separating the switches for charge storage and discharge of each pixel unit. This is equivalent to more precisely adjusting the level of the TDI-CMOS image detector to achieve non-integer multiple charge accumulation, which can optimize the image output by the TDI-CMOS image detector and obtain the optimal image under certain brightness conditions without causing the image to be too bright or too dark due to large jumps in the optional level, thereby causing the loss of product details or increasing the complexity of subsequent information processing. At the same time, due to the use of the charge domain accumulation method, no additional noise is introduced, which can improve the signal-to-noise ratio of the output image and improve the image quality.
[0024] (2) The present invention can directly control these switches to select specific levels by adding charge storage and discharge switches to each pixel unit. It is only necessary to give all pixel units a unified transfer timing, without having to individually control the timing of the transfer electrode of each pixel unit, thereby reducing the complexity of control. BRIEF DESCRIPTION OF THE DRAWINGS
[0025] Various other advantages and benefits will become apparent to those of ordinary skill in the art by reading the detailed description of the preferred embodiments below. The accompanying drawings are only for the purpose of illustrating the preferred embodiments and are not to be considered as limiting the present invention. Moreover, the same reference symbols are used throughout the accompanying drawings to represent the same components. In the accompanying drawings:
[0026] Figure 1 A top view schematic diagram of a common TDI-CMOS image detector single pixel structure;
[0027] Figure 2 It is a cross-sectional schematic diagram of a common TDI-CMOS image detector single pixel structure;
[0028] Figure 3 A schematic diagram of a row of pixel structures of a common TDI-CMOS image detector;
[0029] Figure 4 A schematic diagram of a pixel structure of a TDI-CMOS image detector according to an embodiment of the present invention;
[0030] Figure 5 This is a timing diagram of normal operation of a pixel of a TDI-CMOS image detector according to an embodiment of the present invention;
[0031] Figure 6 Schematic diagram of normal charge accumulation and transfer process of a pixel of a TDI-CMOS image detector according to an embodiment of the present invention;
[0032] Figure 7This is a working timing diagram of the TDI-CMOS image detector when finely adjusting the pixel level in the embodiment of the present invention;
[0033] Figure 8 Schematic diagram of charge accumulation and transfer process when fine adjustment of the number of pixels of a TDI-CMOS image detector according to an embodiment of the present invention;
[0034] Fig. 9 This is a working timing diagram of a pixel unit of a TDI-CMOS image detector that clears charges according to an embodiment of the present invention;
[0035] Fig.10 Schematic diagram of the potential well of a pixel unit for clearing charges in a TDI-CMOS image detector according to an embodiment of the present invention. DETAILED DESCRIPTION
[0036] The exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although the exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the embodiments set forth herein. On the contrary, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.
[0037] Common TDI-CMOS image detector single pixel structure such as Figure 1 , Figure 2 As shown, Figure 1 yes Figure 2 Top view along the Z direction. The Y direction is the charge transfer direction of the TDI-CMOS image detector, the X direction is the length direction of the TDI-CMOS image detector array, which is perpendicular to the Y direction on the detector array plane. The Y direction is the thickness direction of the TDI-CMOS image detector, and the Z direction is determined according to the right-hand rule.
[0038] The TDI-CMOS image detector has a substrate 10, the substrate 10 includes a plurality of pixel units P, a first doping region 11 is formed in the pixel unit P; a gate structure 12 is formed on the surface of the first doping region 11; along the X direction, the second doping region 15 is closest to the first doping region, followed by the third doping region 16, and the second doping region 15 and the third doping region 16 are not Figure 1 Marked in the middle; along the X direction, away from Figure 2 The nearest to the middle gate 12 is the gate and interconnecting metal 13 on the second doping region 15 , followed by the interconnecting metal 14 on the third doping region 16 .
[0039] exist Figure 1Only one pixel unit is shown in the figure. For the TDI-CMOS image detector array, along the Y direction, the gate and interconnected metal 13 on the first doping region 11, the second doping region 15, and the interconnected metal 14 on the third doping region 16 all penetrate the upper and lower pixel units. The specific structure is as follows Figure 3 shown.
[0040] When the TDI-CMOS image detector is working, the charge accumulated in each pixel unit is transferred by changing the working timing of each gate 12 of each pixel unit in the Y direction, but the output charge amount can only be accumulated in integer multiples of a single pixel unit, and non-integer multiples of charge superposition cannot be performed.
[0041] In order to solve the technical problem, the present invention proposes a TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages, such as Figure 4 As shown, by disconnecting the gate and metal on the second doping region of each pixel in the Y direction and connecting to independent TX signals in the X direction, and performing corresponding timing control, the TDI-CMOS image detector can be adjusted to any fine level.
[0042] The TDI-CMOS image detector has a substrate 10, and the substrate 10 includes a plurality of pixel units. In the present embodiment, the substrate 10 includes m-level pixel units, including the first-level pixel units to the m-th-level pixel units, and these pixel units are arranged along the first direction Y. The selected level is n, n≤m, and the charges from the n-th-level pixel units to the first-level pixel units are accumulated and output, that is, the charges are accumulated along the negative direction of Y, and the charges generated from the n+1-th-level to the m-th-level pixel units do not participate in the accumulation and output; on the contrary, if the charge accumulation direction is the positive direction of Y, the charges from the n-th-level to the m-th-level are accumulated and output, and the charges from the n-1-th-level to the 1-th-level do not participate in the accumulation and output, and at this time, the actual number of levels participating in the accumulation is m-n+1 levels. The material of the substrate 10 is silicon. In other embodiments, the material of the substrate can also be germanium, silicon germanium or silicon on insulator.
[0043] A first doping region 11 is designed in the substrate of each pixel unit, a gate structure is formed on the surface of the first doping region, and a first ion is provided in the first doping region, and the doping concentration of the first ion is the first concentration. Along the X direction, a second doping region is provided next to the first doping region 11, the second doping region is not in contact with the first doping region, and the second ion is provided in the second doping region, and the doping concentration of the second ion is the second concentration. A third doping region is provided in the substrate next to the second doping region, and the third doping region is not in contact with the first doping region. In the same pixel unit, the three doping regions do not overlap each other, and the third doping region is closer to the second doping region and farther away from the first doping region 11. The third doping region has a third ion, and the doping concentration of the third ion is the third concentration, which is greater than the first concentration, and the first ion and the third ion have different conductivity types. In this embodiment, along the Z direction, there is no other doping region below the first doping region 11; in other embodiments, along the Z direction, there can be one or more different doping regions below the first doping region 11, and even there can be other doping regions below the doping region below the first doping region 11.
[0044] The substrate 10 includes a top surface and a bottom surface, the top surface is used to subsequently form a gate structure 12, and the bottom surface is used for grounding. The surface of the gate structure 12 is provided with an interconnection metal (not shown in the figure). In this embodiment, there are 4 gate structures C1 to C4 on the first doping region 11 of each pixel unit. In other embodiments, there may be a structure different from 4 gates on the first doping region of each pixel unit, such as 2 gates, 3 gates, or even 5 or 6 gates.
[0045] Along the Y direction, the first doping regions in a number of pixel units are connected together; the second doping regions in a number of pixel units are separated from each other; and the third doping regions in a number of pixel units are also separated.
[0046] Along the Y direction, the interconnection metals 14 on the third doping regions in a number of pixel units are connected together and connected to an external VABD power supply; the gates and the interconnection metals 13 on the second doping regions in a number of pixel units are separated from each other.
[0047] Along the X direction, the substrate also includes a number of pixel units, which are connected to Figure 4 In the same row (along the X direction), the gates of the same name of several pixel units are interconnected through gates or metals, including gates C1, C2, C3, C4 and TX, but excluding the interconnection metal on the third doping region, which is connected together at the farthest end of the pixel array along the Y direction. Gates C1, C2, C3, C4 and TX are connected to the timing control circuit at the farthest end of the pixel array along the X direction.
[0048] The same-named gates of all pixel units can be connected to the timing signals C1, C2, C3, and C4 respectively; and the TX gates of the pixel units in each row (along the X direction) are connected together through gates or metals, and the TX gates of different rows are separated by interconnecting metals, and the TX gates of each row are controlled separately by the timing control circuit.
[0049] The VABD power supply is a high voltage power supply. When the TX signal is at a high level, the charge in the pixel unit will flow into the VABD through the channel under the TX gate, so that the charge in the current pixel unit is cleared. When the TX signal is at a low level, a potential barrier is formed under the TX gate to block the charge in the pixel unit from passing through, so that the accumulated charge in the current pixel unit is transferred according to the timing of gates C1, C2, C3, and C4.
[0050] The gates C1, C2, C3, C4 of each pixel are connected to the corresponding timing signals C1, C2, C3, C4, such as Figure 5 , Figure 7 and Fig. 9 If reverse charge accumulation is to be performed, the order of the signals on the gates C1, C2, C3, and C4 should be opposite to that for forward charge accumulation, that is, the signals on the gates C1, C2, C3, and C4 correspond to Figure 5 , Figure 7 and Fig. 9 The timing signals C4, C3, C2, C1 in.
[0051] The present invention is different from conventional TDI-CMOS image detectors in that:
[0052] In the Y direction, the gates and interconnected metals 13 on the second doping regions 15 of adjacent pixels are not connected;
[0053] In the Y direction, the gate electrode on the second doping region 15 of each pixel and the interconnected metal 13 independently lead out a TX signal and are not connected to each other; instead of being uniformly connected to the VABG voltage;
[0054] In the X direction, the TX signals of each pixel are connected together;
[0055] The TX signal of each row is controlled separately and can be high level, low level or periodic signal;
[0056] For m-level pixels, if n-level (n≤m) cumulative output is set, the level range can be accurately adjusted to [n-1,n] by controlling the duty cycle of the TX signal in the pixel with the currently set highest level m; while the level of a conventional TDI-CMOS detector can only be the currently set n level.
[0057] By setting the TX signal to a high level, the C1~C4 (not limited to 4 gates) signal timing of pixels that do not need to accumulate charges can be kept the same as the timing of pixels that normally accumulate charges. There is no need to deliberately reverse the C1~C4 timing of pixels that do not need to accumulate charges, so that the purpose of clearing the charges in unused pixels can be achieved.
[0058] Fine-tune the level by adjusting the TX signal:
[0059] When working according to the normal set number of levels, such as setting it to n levels, it is required to output all the accumulated signals of n levels. The working sequence is as follows: Figure 5 , all TX signals of level n-2 and below should be set to low level like the TX signals of level n-1. Figure 5 At this time, the charge accumulation in the nth and n-1th pixel units is as follows: Figure 6 shown.
[0060] When fine adjustment is required, such as setting it to level n, by adjusting the high level duty cycle Dutyn of TXn, the signal accumulated by level n-Dutyn can be output. The working sequence is as follows: Figure 7 , all TX signals of level n-2 and below should be set to low level like the TX signals of level n-1. Figure 7 At this time, the charge accumulation in the nth and n-1th pixel units is as follows: Figure 8 shown.
[0061] When TXn is directly set to high level and still set to level n, it can only output the signal accumulated at level n-1, which is equivalent to no charge accumulated at level n. At this time, the working sequence is as follows: Fig. 9 , all TX signals of level n-2 and below should be set to low level like the TX signals of level n-1. Fig. 9 At this time, the charge accumulation in the nth and n-1th pixel units is as follows: Fig.10 At this time, it is equivalent to Figure 5 and Figure 6 In the method, the number of levels is set to n-1.
[0062] In this embodiment, if the set number of levels is n, in order to better remove useless charges, all TXs above the nth level (excluding the nth level) can be set to a high level. Through fine adjustment, when the selected number of levels is n, the range of the output charge accumulation amount can be greater than or equal to n-1 levels and less than or equal to n levels. For TDI-CMOS image sensors, since powerful CMOS circuits are integrated internally, n can be set to any integer between the maximum number of pixel array levels m and the minimum number of pixel array levels 1. Therefore, the present invention can achieve the adjustment of any fine number of levels of TDI-CMOS image detectors.
[0063] The gate structure is located on the surface of the first doped region in each pixel unit. By controlling the gate voltage and timing on the second doped region of the highest level in the selected level, the gate voltage on the second doped region of all pixel units higher than the selected level is set high, and the gate voltage on the second doped region of all pixel units lower than the selected level is set low, so that any fine level adjustment of the TDI-CMOS image detector can be achieved.
[0064] The above-described embodiments are only preferred specific implementations of the present invention. Common changes and substitutions made by those skilled in the art within the scope of the technical solution of the present invention should be included in the protection scope of the present invention.
Claims
1. A TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages, characterized in that: It includes a substrate and a plurality of identical pixel units located in the substrate; The pixel units each include three non-overlapping doping regions, the first doping region does not contact the second doping region, and the distance between the third doping region and the second doping region is smaller than the distance between the third doping region and the first doping region; the three doping regions each contain ions, and the ion conductivity type in the third doping region is opposite to the ion conductivity type in the first doping region; A plurality of gate structures and metal interconnection layers are provided on the surface of the first doped region, a gate structure and a metal interconnection layer are provided on the surface of the second doped region, and interconnection metal is provided on the top of the third doped region; By controlling the voltage and timing of the gate structure of the second doping region, the amount of charge accumulation of the current pixel unit is adjusted, including: When the gate voltage of the gate structure on the second doping region is low, a potential barrier is formed under the gate to block the charges in the pixel unit from passing through, and the charges in the pixel unit are accumulated. According to the timing change of the multiple gates on the first doping region, the charges accumulated under the gate on the first doping region are moved and transferred to the next pixel unit along the charge transfer direction; When the gate voltage of the gate structure on the second doping region is high, the charges in the pixel unit will flow into the external power supply through the channel under the gate, and the charges in the pixel unit will be discharged. At this time, all the charges in the pixel unit are cleared; In a row transfer cycle, the gate voltage on the second doped region is first high and then low. The ratio of the amount of charge accumulated in the pixel unit to the amount of charge accumulated when the gate voltage on the second doped region is always low is the ratio of the time when the gate voltage on the second doped region is low in this row transfer cycle to the entire row transfer cycle.
2. A TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages according to claim 1, characterized in that: A plurality of pixel units are arranged along the charge transfer direction of the TDI-CMOS image detector, the first doping regions in all pixel units are connected together, the second doping regions are separated from each other, and the third doping regions are separated from each other; The interconnection metals on the third doping regions of each pixel unit are connected together and connected to an external power supply, the gate structures on the second doping regions of each pixel unit are not connected and are respectively connected to the timing control circuit, and the metal interconnection layers are not connected.
3. The TDI-CMOS image detector capable of finely adjusting the charge accumulation series according to claim 2, characterized in that: Several pixel units are arranged along the length direction of the TDI-CMOS image detector, and the gate structures with the same name located in the first doping area on all the pixel units are interconnected through gates or metals and are respectively connected to the timing control circuit; in each row, the gate structures located in the second doping area on all the pixel units are connected and then connected to the timing control circuit.
4. The TDI-CMOS image detector capable of finely adjusting the charge accumulation series according to claim 1, characterized in that: The first doping region, the second doping region and the third doping region are arranged in parallel along a direction perpendicular to the charge transfer direction and parallel to the substrate surface, and the size of the first doping region is larger than that of the second doping region and the third doping region.
5. The TDI-CMOS image detector capable of finely adjusting the charge accumulation series according to claim 1, characterized in that: When reverse charge accumulation is to be performed, the signal sequence of the plurality of gate structures on the first doped region should be opposite to that of the forward charge accumulation.
6. The TDI-CMOS image detector capable of finely adjusting the charge accumulation series according to claim 2, characterized in that: If there are m pixel units arranged along the charge transfer direction of the TDI-CMOS image detector, and the selected level is n, n≤m, the charges from the nth level pixel unit to the 1st level pixel unit are accumulated and output, and the charge accumulation direction from the nth level pixel unit to the 1st level pixel unit is the first direction, and the charges generated from the n+1th level to the mth level pixel units do not participate in the accumulation and output; if the charge accumulation direction is the opposite direction of the first direction, the charges from the nth level to the mth level are accumulated and output, and the charges from the n-1th level to the 1st level do not participate in the accumulation and output. At this time, the number of levels actually participating in the accumulation is m-n+1 levels.
7. The TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages according to claim 6, characterized in that: It is required to output all the accumulated signals of the nth level, and the timing control method is: apply a low level to the second doping region gate structure on all pixel units of the nth level and below, and apply a high level to the second doping region gate structure on the n+1th level pixel unit.
8. The TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages according to claim 6, characterized in that: Through fine adjustment, that is, applying a low level to the second doping region gate structure on all pixel units of level n-1 and below, and applying a high level to the second doping region gate structure on the pixel unit of level n+1, the high level duty cycle applied to the second doping region gate structure in the nth level is controlled. The above-mentioned high level duty cycle is set by applying a high level first and then a low level to the second doping region gate structure in the nth level, so that the range of the output charge accumulation amount is greater than or equal to level n-1 and less than or equal to level n.
9. A TDI-CMOS image detector capable of finely adjusting the number of charge accumulation stages according to claim 7 or 8, characterized in that: The gate voltages of the second doping regions of all pixel units greater than level n are set to a high level to clear useless charges.