A gate edge medium passivation voltage withstanding structure GaN HEMT device and a preparation method thereof

Abstract

The application discloses a GaN-based HEMT epitaxial structure based on a graded superlattice vacancy buffer layer, and belongs to the technical field of semiconductors. The GaN-based HEMT epitaxial structure comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a GaN channel layer, an AlGaN layer one, an AlGaN layer two, a gate edge medium passivation layer, a source electrode and a drain electrode. A gate electrode and a second passivation layer are further arranged between the source electrode and the drain electrode. In the application, the gate edge medium passivation is deposited, the leakage of the gate current is improved, and the breakdown characteristic is improved. The dielectric constant is improved by reducing the Al component at the top of the AlGaN barrier layer, the polarization charge at the top of the AlGaN material is reduced, the electric field near the drain end of the gate electrode is reduced, and the electric field distribution between the gate electrode and the drain electrode is more uniform. The tensile stress of the upper second passivation layer compensates for the compressive stress of the lower gate edge medium, and the weak tensile stress applied to the channel layer can improve the two-dimensional electron gas concentration of the GaN channel layer, and meanwhile, the on-resistance, the square resistance and other characteristics of the device can be improved.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, specifically relating to a GaNHEMT device with gate edge dielectric passivation and its fabrication method. Background Technology

[0002] Third-generation semiconductors, represented by gallium nitride (GaN) materials, have advantages such as direct bandgap, large band gap, high breakdown field strength, and good thermal conductivity. Furthermore, GaN and aluminum gallium nitride heterojunctions have strong spontaneous and piezoelectric polarization, and can obtain high-concentration, high-electron-mobility two-dimensional electron gases without doping. They have huge potential and market in fields such as radiation resistance, high-temperature high-power, and microwave devices.

[0003] In recent years, with the development of radar and wireless communication, there are higher power requirements for semiconductor materials. First-generation Si and second-generation GaAs semiconductor materials are no longer sufficient, and research focus has shifted to third-generation wide-bandgap semiconductor materials. Due to its large bandgap, gallium nitride (GaN) has a theoretical critical breakdown electric field that is ten times greater than that of silicon, and its high-concentration, high-electron-mobility two-dimensional electron gas gives it high breakdown voltage and low on-resistance in the power field. However, the actual breakdown voltage of GaN HEMTs fabricated in existing technologies still falls far short of their theoretical breakdown voltage limit. Source-drain punch-through, electric field concentration, and excessive bulk leakage current are the main reasons for premature breakdown of GaN power devices. Therefore, various techniques have been used to improve the breakdown voltage of devices, including field plate technology, fluorine ion implantation termination technology, polarized superjunction technology, and buffer layer compensation doping technology. Field plate technology is currently widely used in power electronics and is one of the most common techniques for mitigating electric field concentration effects. The basic principle of field plate technology is to reduce the original high electric field peak value by introducing an additional electric field and to introduce a new electric field peak value at the end of the field plate, while simultaneously expanding the lateral width of the depletion region. Fluorine ion implantation terminal technology injects highly electronegative fluorine-based plasma into the AlGaN barrier layer between the gate and drain electrodes, thereby modulating and optimizing the surface electric field distribution of the device to alleviate the electric field concentration effect and improve the device's final breakdown voltage. Compensation doping technology involves doping the GaN buffer layer with C or Fe, introducing deep-level acceptor traps and increasing the buffer layer's resistance, ultimately reducing the buffer layer leakage current and improving the device's breakdown voltage.

[0004] Avalanche breakdown, caused by a large number of electron-hole pairs generated near the gate-drain edge, is one of the main breakdown mechanisms in GaN-based HEMT devices. To delay avalanche breakdown and reduce leakage current near the drain caused by tunneling by redistributing the high electric field near the gate, common methods include: i) increasing the gate-drain distance; ii) optimizing the field plate structure; and iii) fluorine ion implantation termination technology. However, due to on-resistance limitations, the gate-drain distance cannot be increased indiscriminately. While optimizing the field plate structure significantly improves the field strength distribution and breakdown characteristics, it introduces additional parasitic capacitance, affecting the device's switching and high-frequency characteristics. Some researchers have proposed an air field plate structure, which, while not introducing parasitic capacitance, undoubtedly increases fabrication complexity and cost. Although fluorine ion implantation termination technology does not introduce additional parasitic capacitance, the injection of fluorine-based plasma into the thin AlGaN barrier layer affects the transport characteristics of the 2DEG, ultimately leading to device performance degradation. Therefore, how to improve the gate leakage current of GaN-based power electronic devices and thus increase their operating voltage remains one of the technical problems that urgently need to be solved. Summary of the Invention

[0005] To address the problems existing in the prior art, this invention specifically relates to a gallium nitride (HEMT) device with a gate edge dielectric passivation structure and its fabrication method. In this invention, depositing dielectric passivation at the gate edge improves gate current leakage and enhances breakdown characteristics. Reducing the Al content at the top of the AlGaN barrier layer increases the dielectric constant and lowers the polarization charge at the top of the AlGaN material, thus reducing the electric field near the drain and resulting in a more uniform electric field distribution between the gate and drain. The tensile stress of the upper second passivation layer compensates for the compressive stress of the lower gate edge dielectric, and applying a weak tensile stress to the channel layer improves the two-dimensional electron gas concentration of the GaN channel layer, while also improving the device's on-resistance, sheet resistance, and other characteristics. The device fabrication method proposed in this invention is simple to operate, low in cost, and environmentally friendly while improving performance, exhibiting high operability and feasibility.

[0006] A GaN HEMT device with gate edge dielectric passivation includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, a GaN channel layer, an AlGaN layer one, an AlGaN layer two, a gate edge dielectric passivation layer, a source, and a drain. A gate and a second passivation layer are also disposed between the source and the drain.

[0007] Furthermore, the substrate material is Si, SiC, sapphire, or GaN.

[0008] Furthermore, the nucleation layer material is AlN, and the thickness is 2–100 nm.

[0009] Furthermore, the buffer layer material is iron- or carbon-doped GaN, with a thickness of 100–500 μm.

[0010] Furthermore, the thickness of the GaN channel layer is 300–500 nm.

[0011] Furthermore, in the AlGaN layer one (i.e., the high Al content AlGaN layer), the molar composition of Al is 0.2 to 0.3, and the thickness is 5 to 10 nm; in the AlGaN layer two (the low Al content AlGaN layer), the molar composition of Al is 0.12 to 0.2, and the thickness is 10 to 18 nm.

[0012] Furthermore, the gate metal is Ni / Au, located between the source and drain.

[0013] Furthermore, the second passivation layer material is SiN.

[0014] This invention also provides a method for fabricating a GaN HEMT device with a gate edge dielectric passivation structure, comprising the following steps:

[0015] S1. Epitaxial wafer preparation

[0016] The epitaxial wafer was grown using MOCVD. The epitaxial structure was stacked from bottom to top as a substrate, nucleation layer, buffer layer, GaN channel layer, AlGaN layer one, and AlGaN layer two.

[0017] S2. Clean the epitaxial wafer.

[0018] The epitaxial wafer was cleaned by ultrasonication for 5 minutes each with acetone, ethanol, and deionized water.

[0019] S3, Countertop Isolation

[0020] Apply photoresist, pre-bake, photolithography mesa, use ICP etching equipment to isolate the mesa, and remove the photoresist after etching is complete.

[0021] S4, Source / Drain Electrode Evaporation

[0022] Source and drain metals were deposited on AlGaN layer 2 using an electron beam evaporation stage, and then the metals outside the source and drain regions were removed by ultrasonication in an acetone solution.

[0023] S5, Source / Drain Electrode Annealing

[0024] The source and drain electrodes with ohmic contact are formed by annealing at 830℃ for 30s in an annealing furnace under a N2 atmosphere.

[0025] S6, Forming the gate edge dielectric region

[0026] Partial etching of AlGaN layer 2 is performed in the region near the drain at the gate edge to form a region where the gate edge dielectric region is deposited.

[0027] S7, Gate edge passivation layer deposition

[0028] A dielectric layer is deposited using PECVD or ICPCVD equipment to form a gate edge dielectric passivation layer;

[0029] S8, Etching part of the gate edge dielectric layer

[0030] Only the dielectric of the gate region is etched to the surface of the AlGaN layer;

[0031] S9, gate electrode evaporation

[0032] Gate electrodes were deposited on AlGaN layer 2 using an electron beam evaporation stage;

[0033] S10, Second passivation layer deposition

[0034] A second passivation layer is deposited between the gate and source, and between the gate and drain, using PECVD or ICPCVD equipment.

[0035] The beneficial effects of this invention are:

[0036] (1) The present invention deposits a dielectric passivation at the gate edge, which can improve the leakage of gate current and improve the breakdown characteristics.

[0037] (2) By reducing the Al content at the top of the AlGaN barrier layer, the dielectric constant is increased, the polarization charge at the top of the AlGaN material is reduced, the electric field near the drain of the gate is reduced, and the electric field distribution between the gate and the drain is more uniform.

[0038] (3) The tensile stress of the upper second passivation layer compensates for the compressive stress of the gate edge dielectric below, and the weak tensile stress applied to the channel layer can improve the two-dimensional electron gas concentration of the GaN channel layer, and also compensate for the effect of the low Al content AlGaN layer on the reduction of the two-dimensional electron gas concentration. At the same time, it can improve the on-resistance, sheet resistance and other characteristics of the device.

[0039] (4) This structure, combined with the field plate, can further optimize the electric field distribution between the gate and drain, and improve the breakdown characteristics of the device.

[0040] (5) The preparation process involved in this invention is simple, the material cost is low, and the preparation process is environmentally friendly and safe. The film formation methods involved in the preparation process of this invention, such as electron beam evaporation and MOCVD, are common methods in semiconductor CMOS processes. They can effectively reduce production costs while ensuring the excellent performance of the device, which is in line with the development trend of Moore's Law. Attached Figure Description

[0041] Figure 1 This is a schematic diagram of the epitaxial structure of a voltage-resistant device based on gate edge dielectric passivation.

[0042] Figure 2 This is a flowchart illustrating the device fabrication process in Example 1 of this invention.

[0043] Figure 3 This is a schematic diagram of the device structure in Embodiment 2 of the present invention.

[0044] Figure 4 This is a flowchart illustrating the device fabrication process in Example 2 of this invention. Detailed Implementation

[0045] To better understand the purpose, structure, and function of this invention, the technical solutions in the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments.

[0046] Example 1

[0047] like Figure 1 As shown, this embodiment provides an epitaxial structure for a GaN HEMT device with a gate edge dielectric passivation structure. From bottom to top, the layers are stacked as a substrate, a nucleation layer, a buffer layer, a GaN channel layer, an AlGaN layer one, an AlGaN layer two, a gate edge dielectric passivation layer, a second passivation layer, and a source, a drain, and a gate.

[0048] In this embodiment, the substrate material is Si with a thickness of 1 mm.

[0049] In this embodiment, the nucleation layer material is AlN with a thickness of 20 nm.

[0050] In this embodiment, the buffer layer material is Fe-doped GaN with a thickness of 300 nm.

[0051] In this embodiment, the thickness of the GaN channel layer is 320 nm.

[0052] In this embodiment, the AlGaN layer has a thickness of 8 nm and an Al content of 0.25%.

[0053] In this embodiment, the AlGaN layer has a thickness of 14 nm and an Al content of 0.15%.

[0054] In this embodiment, the gate edge dielectric layer material is SiON with a thickness of 55nm.

[0055] In this embodiment, the second passivation layer material is SiN, and the thickness is 100nm.

[0056] like Figure 2 As shown, this embodiment also provides a GaNHEMT device based on a gate edge dielectric passivation breakdown structure and its fabrication method, including the following steps:

[0057] S1. Epitaxial wafer preparation; The epitaxial wafer is stacked from bottom to top as follows: substrate, nucleation layer, buffer layer, GaN channel layer, AlGaN layer 1, and AlGaN layer 2;

[0058] S2. Clean the epitaxial wafer; ultrasonically clean it in acetone solution for 5 minutes to remove surface organic matter, then ultrasonically clean it in anhydrous ethanol solution for 3 minutes, and finally ultrasonically clean it in deionized water for 3 minutes.

[0059] S3. Apply photoresist, pre-bake, photolithography mesa, use ICP etching equipment to isolate the mesa, and remove the photoresist after etching is completed;

[0060] S4. Coating, pre-baking, photolithography to form source and drain regions, and using an electron beam evaporation stage to deposit source and drain electrodes Ti / Al / Ni / Au = 20 / 140 / 50 / 40nm. After metal stripping, annealing at 830℃ for 30s in N2 atmosphere to obtain ohmic contact source and drain electrodes.

[0061] S5. Apply resist, pre-bake, photolithographically etch the area where the gate edge dielectric grows, and use ICP etching process to etch the area where the gate edge dielectric grows on AlGaN layer 2, with an etching depth of 5nm.

[0062] S6. After pretreating the etched epitaxial wafer with N2 for 3 minutes using ICPCVD, SiON dielectric is deposited. SiH4, N2, and N2O gases are introduced into the ICPCVD equipment at a low temperature of 130°C. The pressure in the reaction chamber is controlled at 1 Pa, and the compressive stress of the SiON film is controlled between 20 MPa and 50 MPa. The SiON dielectric deposition thickness is 55 nm. After the dielectric deposition is completed, the photoresist is removed to form a gate edge dielectric passivation layer.

[0063] S7. Apply resist, pre-bake, photolithographically create the etching area, use ICP to etch the dielectric layer at the gate edge, and etch the dielectric layer of the gate area only to the surface of the AlGaN layer;

[0064] S8. Apply resist, pre-bake, photolithographically print the gate area, use an electron beam evaporation stage to deposit gate electrode Ni / Au = 50 / 150nm, then perform metal lift-off to form the gate;

[0065] S9. Coating, pre-baking, photolithography to create passivation areas, depositing SiN dielectric using ICP-VD equipment, controlling the tensile stress of the SiN film between 50 and 100 MPa, removing the photoresist after dielectric deposition to form the second passivation layer.

[0066] Example 2

[0067] like Figure 3 As shown, this embodiment provides an epitaxial structure for a GaN HEMT device with a gate edge dielectric passivation structure. From bottom to top, the layers are stacked as a substrate, a nucleation layer, a buffer layer, a GaN channel layer, an AlGaN layer one, an AlGaN layer two, a gate edge dielectric passivation layer, a second passivation layer, and a source, a drain, and a gate.

[0068] In this embodiment, the substrate material is Si with a thickness of 1 mm.

[0069] In this embodiment, the nucleation layer material is AlN with a thickness of 20 nm.

[0070] In this embodiment, the buffer layer material is Fe-doped GaN with a thickness of 300 nm.

[0071] In this embodiment, the thickness of the GaN channel layer is 320 nm.

[0072] In this embodiment, the AlGaN layer has a thickness of 8 nm and an Al content of 0.25%.

[0073] In this embodiment, the thickness of the low-Al content AlGaN layer is 14 nm, and the Al content is 0.15.

[0074] In this embodiment, the gate edge dielectric layer material is SiON with a thickness of 55nm.

[0075] In this embodiment, the second passivation layer material is SiN, and the thickness is 100nm.

[0076] like Figure 4 As shown, this embodiment also provides a GaNHEMT device based on a gate edge dielectric passivation breakdown voltage structure and its fabrication method, including the following steps:

[0077] S1. Epitaxial wafer preparation; The epitaxial wafer is stacked from bottom to top as follows: substrate, nucleation layer, buffer layer, GaN channel layer, AlGaN layer 1, and AlGaN layer 2;

[0078] S2. Clean the epitaxial wafer; ultrasonically clean it in acetone solution for 5 minutes to remove surface organic matter, then ultrasonically clean it in anhydrous ethanol solution for 3 minutes, and finally ultrasonically clean it in deionized water for 3 minutes.

[0079] S3. Apply photoresist, pre-bake, photolithography mesa, use ICP etching equipment to isolate the mesa, and remove the photoresist after etching is completed;

[0080] S4. Coating, pre-baking, photolithography to form source and drain regions, and using an electron beam evaporation stage to deposit source and drain electrodes Ti / Al / Ni / Au = 20 / 140 / 50 / 40nm. After metal stripping, annealing at 830℃ for 30s in N2 atmosphere to obtain ohmic contact source and drain electrodes.

[0081] S5. Apply resist, pre-bake, and photolithographically create the area for the growth of the dielectric at the gate edge. Use ICP etching process to etch the area for the growth of the dielectric at the gate edge on the low Al content AlGaN layer, with an etching depth of 5nm.

[0082] S6. After pretreating the etched epitaxial wafer with N2 for 3 minutes using ICPCVD, SiON dielectric is deposited. SiH4, N2, and N2O gases are introduced into the ICPCVD equipment at a low temperature of 130°C. The pressure in the reaction chamber is controlled at 1 Pa, and the compressive stress of the SiON film is controlled between 20 MPa and 50 MPa. The SiON dielectric deposition thickness is 55 nm. After the dielectric deposition is completed, the photoresist is removed to form a gate edge dielectric passivation layer.

[0083] S7. Apply resist, pre-bake, photolithographically create the etching area, use ICP to etch the gate edge dielectric layer, etch the dielectric of the gate region to the AlGaN layer surface, and perform equally spaced longitudinal etching on the edge dielectric beyond the gate region, also etching to the AlGaN layer surface, then remove the resist.

[0084] S8. Apply resist, pre-bake, photolithographically print the gate area, use an electron beam evaporation stage to deposit electrodes Ni / Au = 50 / 150nm, and then perform metal lift-off to form the gate.

[0085] S9. Coating, pre-baking, photolithography to create passivation areas, and depositing SiN dielectric using ICP-VD equipment. The tensile stress of the SiN film is controlled between 50 and 100 MPa. After dielectric deposition, the photoresist is removed to form the second passivation layer.

[0086] The specific embodiments described above further illustrate the purpose, technical solutions, and beneficial effects of this disclosure. It should be understood that the above descriptions are merely specific embodiments of this disclosure and are not intended to limit this disclosure. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this disclosure should be included within the protection scope of this disclosure.

Claims

1. A method for fabricating a GaN HEMT device with gate edge dielectric passivation, characterized in that, Includes the following steps: S1. Epitaxial wafer preparation The epitaxial wafer was grown using MOCVD. The epitaxial structure was stacked from bottom to top as a substrate, nucleation layer, buffer layer, GaN channel layer, AlGaN layer one, and AlGaN layer two. S2. Clean the epitaxial wafer. The epitaxial wafer was cleaned by ultrasonication for 5 minutes each with acetone, ethanol, and deionized water. S3, Countertop Isolation Apply photoresist, pre-bake, photolithography mesa, use ICP etching equipment to isolate the mesa, and remove the photoresist after etching is complete. S4, Source / Drain Electrode Evaporation Source and drain metals were deposited on AlGaN layer 2 using an electron beam evaporation stage, and then the metals outside the source and drain regions were removed by ultrasonication in an acetone solution. S5, Source / Drain Electrode Annealing The source and drain electrodes with ohmic contact are formed by annealing at 830℃ for 30s in an annealing furnace under a N2 atmosphere. S6, Forming the gate edge dielectric region Partial etching of AlGaN layer 2 is performed in the region near the drain at the gate edge to form a region where the gate edge dielectric region is deposited. S7, Gate edge passivation layer deposition A dielectric layer is deposited using PECVD or ICPCVD equipment to form a gate edge dielectric passivation layer; S8, Etching part of the gate edge dielectric layer Only the dielectric of the gate region is etched to the surface of the AlGaN layer; S9, gate electrode evaporation Gate electrodes were deposited on AlGaN layer 2 using an electron beam evaporation stage; S10, Second passivation layer deposition A second passivation layer is deposited between the gate and source, and between the gate and drain, using PECVD or ICPCVD equipment.

2. The method for fabricating a GaN HEMT device with gate edge dielectric passivation according to claim 1, characterized in that, The substrate material is Si, SiC, sapphire, or GaN.

3. The method for fabricating a GaN HEMT device with gate edge dielectric passivation according to claim 1, characterized in that, The nucleation layer material is AlN, and the thickness is 2~100nm.

4. The method for fabricating a GaN HEMT device with gate edge dielectric passivation according to claim 1, characterized in that, The buffer layer material is iron- or carbon-doped GaN with a thickness of 100~500μm.

5. The method for fabricating a GaN HEMT device with gate edge dielectric passivation according to claim 1, characterized in that, The thickness of the GaN channel layer is 300–500 nm.

6. The method for fabricating a GaN HEMT device with gate edge dielectric passivation according to claim 1, characterized in that, The first AlGaN layer has a molar composition of 0.2-0.3 and a thickness of 5-10 nm; the second AlGaN layer has a molar composition of 0.12-0.2 and a thickness of 10-18 nm.

7. The method for fabricating a GaN HEMT device with gate edge dielectric passivation according to claim 1, characterized in that, The gate metal is Ni / Au, located between the source and drain.

8. The method for fabricating a GaN HEMT device with gate edge dielectric passivation according to claim 1, characterized in that, The second passivation layer material is SiN.

9. A GaN HEMT device with gate edge dielectric passivation prepared by the method of claim 1, characterized in that, It includes, from bottom to top, a substrate, a nucleation layer, a buffer layer, a GaN channel layer, an AlGaN layer one, an AlGaN layer two, a gate edge dielectric passivation layer, a source, and a drain. A gate and a second passivation layer are also disposed between the source and the drain.

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