A method for preparing a MOSFET device and a MOSFET device

Abstract

The present invention relates to a method for preparing a MOSFET device and a MOSFET device. The preparation method comprises the following steps: growing an N-type epitaxial region on the surface of a silicon carbide N+ substrate and etching to form an epitaxial layer; depositing a silicon nitride layer and sequentially forming a P-WELL layer, an N Source layer and a P-PLUS layer through a self-alignment process; etching and removing a first gate polysilicon layer and a first oxide layer deposited for positioning in the self-alignment process, and then depositing and etching to obtain a second oxide layer and a second gate polysilicon layer, thereby completing the preparation of the MOSFET device. The present invention introduces a self-alignment process for design and preparation, thereby replacing multiple photolithography steps, avoiding the introduction of impurities or defects through excessive photolithography steps, and facilitating the control of production costs. When the P-WELL layer, the N Source layer and the P-PLUS layer are prepared through the self-alignment process, the positioning accuracy is higher, thereby improving the device performance and reliability.

Description

Technical Field

[0001] The present invention relates to the technical field of power semiconductor devices, and in particular to a method for preparing a MOSFET device and a MOSFET device. Background Art

[0002] Metal-Oxide-Semiconductor Field-Effect Transistor (MOSFET) consists of a three-layer structure of metal-oxide-semiconductor. It is an important semiconductor device used for signal amplification, switch control and voltage regulation in electronic circuits and has excellent electrical properties and controllability.

[0003] In the MOSFET device preparation process, the alignment process is one of the key steps, which is used to ensure that the elements and structures between different pattern layers can be accurately aligned to form the correct circuit layout; photolithography technology prints the integrated circuit pattern on the mask onto the precise surface of the silicon wafer through processes such as exposure and selective chemical etching. However, with the development of chip process nodes and process technology, the number of photolithography times in the alignment process has gradually increased. Each photolithography step involves expensive photolithography machines, mask production, photoresist, mask correction and other equipment and materials. The preparation cost increases with the increase in the number of photolithography times; at the same time, too many photolithography times will also introduce more impurities or defects, for example, it may lead to the introduction of more leakage current paths or reduce the quality of the insulating layer. Summary of the invention

[0004] To this end, the technical problem to be solved by the present invention is to overcome the technical difficulties in the prior art of introducing impurities and high costs due to too many photolithography times of MOSFET devices, and to provide a MOSFET device preparation method and a MOSFET device, in which the device is prepared by a self-alignment process, which effectively improves the switching performance and helps to control costs.

[0005] In a first aspect, in order to solve the above technical problems, the present invention provides a method for preparing a MOSFET device, which comprises:

[0006] Step S1, growing an N-type epitaxial region on the surface of a silicon carbide N+ substrate, and etching the N-type epitaxial region to form an epitaxial layer;

[0007] Wherein, the top of the epitaxial layer includes a protruding portion and a first boundary arranged at the same height on both sides of the protruding portion in the width direction;

[0008] Step S2, depositing a silicon nitride layer, which is located on both sides of the protrusion in the width direction; performing ion implantation into the epitaxial layer along the first boundary, shielding the silicon nitride layer, and forming a P-WELL layer on both sides of the epitaxial layer in the width direction;

[0009] Step S3, depositing a first gate polysilicon layer, which is respectively located on a side of the silicon nitride layer away from the protruding portion; performing ion implantation into the epitaxial layer along the boundary of the P-WELL layer, and forming an N Source layer through shielding by the first gate polysilicon layer;

[0010] Step S4, depositing a first oxide layer, which is respectively located on a side of the first gate polysilicon layer away from the silicon nitride layer; performing ion implantation into the N Source layer and the P-WELL along a boundary of the N Source layer, and forming a P-PLUS layer through shielding by the first oxide layer;

[0011] Step S5, etching and removing the first gate polysilicon layer and the first oxide layer;

[0012] Step S6, depositing and etching to obtain a second oxide layer and a second gate polysilicon layer.

[0013] In one embodiment of the present invention, in step S1, a second boundary is formed above the raised portion, the width of the second boundary is 2000nm~5000nm, the height difference between the second boundary and the first boundary is 1000nm~3000nm; the width of the first boundary on both sides is 3000nm~6000nm.

[0014] In one embodiment of the present invention, in step S2, the silicon nitride layer is deposited by:

[0015] Depositing silicon nitride along the boundary above the epitaxial layer, and etching the silicon nitride to obtain the silicon nitride layer, wherein the bottom of the silicon nitride layer contacts at least a portion of the first boundary, and the width of the silicon nitride layer is 200 nm to 500 nm;

[0016] In the step S2, the P-WELL impurity ion is implanted once or multiple times to obtain the P-WELL layer, the thickness of which is 600nm~1500nm.

[0017] In one embodiment of the present invention, in step S3, the first gate polysilicon layer is deposited by:

[0018] A first polysilicon is deposited on the top of the device obtained in step S2, and the first polysilicon is etched to obtain the first gate polysilicon layer, wherein the bottom of the first gate polysilicon layer contacts at least a portion of the top of the P-WELL layer, and the width of the first gate polysilicon layer is 100nm~800nm.

[0019] In one embodiment of the present invention, in the step S3, after one or more N Source impurity ion implantations, the N Source layer is obtained, and its thickness is 200nm~800nm; the thickness of the N Source layer is less than the thickness of the P-WELL layer.

[0020] In one embodiment of the present invention, in step S4, the first oxide layer is deposited by:

[0021] A first oxide region is deposited on the top of the device obtained in step S3, and the first oxide region is etched to obtain the first oxide layer, wherein the bottom of the first oxide layer contacts at least a portion of the top of the N Source layer, and the width of the first oxide layer is 2000nm~5000nm.

[0022] In one embodiment of the present invention, in the step S4, the P-PLUS layer is obtained through one or more P-PLUS impurity ion implantations, and the thickness of the P-PLUS layer is the sum of the thicknesses of the P-WELL layer and the N Source layer.

[0023] In one embodiment of the present invention, step S6 includes:

[0024] Step S61, depositing a second oxide layer on the top of both sides of the protrusion, wherein the thickness of the second oxide layer is 300nm-800nm;

[0025] Step S62, depositing a second polysilicon on the top of the device obtained in step S61, etching the second polysilicon to obtain the second gate polysilicon layer, the second gate polysilicon layer is respectively located on the side of the silicon nitride layer away from the protruding portion; at the same time, etching the second oxide layer to retain the area located at the bottom of the second gate polysilicon layer, the width of the second gate polysilicon layer and the second oxide layer are both 300nm~1200nm.

[0026] In a second aspect, the present invention further provides a MOSFET device, wherein the MOSFET device is obtained by using the preparation method described in any of the above embodiments.

[0027] In one embodiment of the present invention, a Schottky contact metal layer is further included, and the Schottky contact metal layer is located on the top of the protrusion and between the silicon nitride layers on both sides.

[0028] The above technical solution of the present invention has the following advantages compared with the prior art:

[0029] The MOSFET device preparation method and the MOSFET device described in the present invention are designed and prepared by introducing a self-alignment process, which replaces multiple photolithography steps, avoids the introduction of impurities or defects by too many photolithography steps, and is convenient for controlling production costs. When the P-WELL layer, N Source layer, P-PLUS layer and other regions are prepared by the self-alignment process, the positioning accuracy is higher, thereby improving the device performance and reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] In order to make the content of the present invention more clearly understood, the present invention is further described in detail below according to specific embodiments of the present invention in conjunction with the accompanying drawings, wherein:

[0031] Figure 1 is a flow chart of a method for preparing a MOSFET device in Embodiment 1 of the present invention;

[0032] Figure 2 This is a schematic diagram of the structure in which the growth of the N-type epitaxial region is completed in step S1 of the first embodiment of the present invention;

[0033] Figure 3 This is a schematic diagram of the structure after the processing of step S1 in the first embodiment of the present invention is completed;

[0034] Figure 4 is a schematic diagram of the structure after silicon nitride deposition is completed in step S2 of the first embodiment of the present invention;

[0035] Figure 5 is a schematic diagram of the structure in which the silicon nitride layer is etched in step S2 of the first embodiment of the present invention;

[0036] Figure 6 is a schematic diagram of the structure of the P-WELL layer after processing in step S2 of the first embodiment of the present invention;

[0037] Figure 7 is a schematic diagram of a structure in which the first polysilicon deposition is completed in step S3 of the first embodiment of the present invention;

[0038] Figure 8 is a structural schematic diagram of the first gate polysilicon layer being etched in step S3 of the first embodiment of the present invention;

[0039] Fig. 9 is a schematic diagram of the structure after the N Source layer is processed in step S3 of the first embodiment of the present invention;

[0040] Fig.10 is a schematic diagram of the structure in which the first oxide region is deposited in step S4 of the first embodiment of the present invention;

[0041] Fig.11 is a schematic diagram of a structure in which the first oxide layer is etched in step S4 of the first embodiment of the present invention;

[0042] Fig.12 is a schematic diagram of the structure after the P-PLUS layer is processed in step S4 of the first embodiment of the present invention;

[0043] Fig.13 This is a schematic diagram of the structure after the processing in step S5 of the first embodiment of the present invention is completed;

[0044] Fig.14 This is a schematic diagram of the structure after the processing of step S61 in the first embodiment of the present invention is completed;

[0045] Fig.15 is a schematic diagram of a structure in which the second polysilicon deposition is completed in step S62 of the first embodiment of the present invention;

[0046] Fig.16 It is a structural schematic diagram of a MOSFET device in Embodiment 2 of the present invention;

[0047] Fig.17 It is a schematic diagram of the structure of a MOSFET device in Embodiment 3 of the present invention.

[0048] Explanation of the reference numerals in the specification: 10, silicon carbide N+ substrate; 20, N-type epitaxial region; 21, epitaxial layer; 22, raised portion; 23, first boundary; 24, second boundary; 30, P-WELL layer; 31, N Source layer; 32, P-PLUS layer; 40, silicon nitride; 41, silicon nitride layer; 50, first polysilicon; 51, first gate polysilicon layer; 60, first oxide region; 61, first oxide layer; 70, second oxide layer; 80, second polysilicon; 81, second gate polysilicon layer; 90, Schottky contact metal layer. DETAILED DESCRIPTION

[0049] The present invention is further described below in conjunction with the accompanying drawings and specific embodiments so that those skilled in the art can better understand the present invention and implement it, but the embodiments are not intended to limit the present invention.

[0050] Embodiment 1

[0051] Reference Figure 1 As shown, a first embodiment of the present invention provides a method for preparing a MOSFET device. The preparation method reduces the number of photolithography steps through a self-alignment process, has higher alignment accuracy than the photolithography step, is less likely to introduce impurities, and has lower production costs.

[0052] Specifically, refer to Figure 2 to Figure 16 As shown, the MOSFET device preparation method includes:

[0053] Step S1,

[0054] Reference Figure 2As shown, an N-type epitaxial region 20 is grown on the surface of the silicon carbide N+ substrate 10, and the N-type epitaxial region 20 is etched downward from the upper surface to form an epitaxial layer 21; Figure 3 As shown, the etched grooves on both sides have a larger area so that the epitaxial layer 21 forms a "convex" structure after etching. The top of the epitaxial layer 21 includes a protruding portion 22 and a first boundary 23 arranged at the same height on both sides of the width direction of the protruding portion 22. A second boundary 24 is formed on the top of the protruding portion 22. The width of the second boundary 24 is 2000nm~5000nm, and the height difference between the second boundary 24 and the first boundary 23 is 1000nm~3000nm; the width of the first boundary 23 on both sides is 3000nm~6000nm.

[0055] Step S2,

[0056] Reference Figure 4 As shown, silicon nitride 40 is deposited along the boundary above the epitaxial layer 21; Figure 5 As shown, the silicon nitride 40 on both sides of the device and the silicon nitride 40 in contact with the second boundary 24 are etched, and the silicon nitride 40 in contact with both sides of the protrusion 22 in the width direction is retained to obtain a silicon nitride layer 41; the bottom of the silicon nitride layer 41 is in contact with at least a portion of the first boundary 23, and the width of the silicon nitride layer 41 is 200nm~500nm.

[0057] Reference Figure 6 As shown, ion implantation is performed along the area on the first boundary 23 that is not blocked by the silicon nitride layer 41, and one or more P-WELL impurity ion implantations are performed into the epitaxial layer 21. After being blocked by the silicon nitride layer 41, a P-WELL layer 30 is formed on both sides of the epitaxial layer 21 in the width direction, and the thickness thereof is 600nm~1500nm.

[0058] Step S3,

[0059] Reference Figure 7 As shown, a first polysilicon 50 is deposited along the border on the top of the device obtained in step S2; Figure 8 As shown, the first polysilicon 50 on both sides of the device and the first polysilicon 50 in contact with the second boundary 24 are etched, and the first polysilicon 50 in contact with the side of the silicon nitride layer 41 away from the protrusion 22 is retained to obtain a first gate polysilicon layer 51; the bottom of the first gate polysilicon layer 51 is in contact with at least a portion of the top of the P-WELL layer 30, and the width of the first gate polysilicon layer 51 is 100nm~800nm.

[0060] Reference Fig. 9As shown, ion implantation is performed along the boundary of the P-WELL layer 30 in an area not blocked by the first gate polysilicon layer 51, and one or more N Source impurity ion implantations are performed into the epitaxial layer 21, and an N Source layer 31 is obtained after being blocked by the first gate polysilicon layer 51, and the thickness of the N Source layer 31 is 200nm~800nm; the thickness of the N Source layer 31 is less than the thickness of the P-WELL layer 30.

[0061] Step S4,

[0062] Reference Fig.10 As shown, a first oxide region 60 is formed by depositing on the top of the device obtained in step S3, referring to Fig.11 As shown, part of the first oxide region 60 located on both sides of the device and the first oxide region 60 in contact with the second boundary 24 are etched, and the first oxide region 60 in contact with the side of the first gate polysilicon layer 51 away from the silicon nitride layer 41 is retained to obtain a first oxide layer 61; the bottom of the first oxide layer 61 is in contact with at least a portion of the top of the N Source layer 31, and the width of the first oxide layer 61 is 2000nm~5000nm.

[0063] Reference Fig.12 As shown, ion implantation is performed along the boundary of the N Source layer 31 in an area not blocked by the first oxide layer 61, and one or more P-PLUS impurity ion implantations are performed into the N Source layer 31 and the P-WELL layer 30, and a P-PLUS layer 32 is obtained after being blocked by the first oxide layer 61, and the thickness of the P-PLUS layer 32 is the sum of the thicknesses of the P-WELL layer 30 and the N Source layer 31.

[0064] Step S5,

[0065] Reference Fig.13 As shown, the first gate polysilicon layer 51 and the first oxide layer 61 on the epitaxial layer 21 are removed by an etching process.

[0066] Step S6,

[0067] Step S61, refer to Fig.14 As shown, a second oxide layer 70 is deposited on the top of both sides of the protrusion 22, and the thickness of the second oxide layer 70 is 300nm~800nm;

[0068] Step S62, refer to Fig.15 As shown, in step S61, a second polysilicon 80 is deposited on the top of the device obtained. Fig.16As shown, the second polysilicon 80 is etched to obtain the second gate polysilicon layer 81, and the second gate polysilicon layer 81 is respectively located on the side of the silicon nitride layer 41 away from the protrusion 22; at the same time, the second oxide layer 70 is etched to retain its area located at the bottom of the second gate polysilicon layer 81, and the widths of the second gate polysilicon layer 81 and the second oxide layer 70 are both 300nm~1200nm.

[0069] In the first embodiment of the present invention, the silicon nitride layer 41 can serve as an isolation layer of the gate polysilicon layer, effectively isolating the first gate polysilicon layer 51 and the epitaxial layer 21, and isolating the second gate polysilicon layer 81 and the epitaxial layer 21, so as to realize surface protection of the gate side wall; a protective layer is formed on the surface of the gate side wall by a self-aligned double imaging technology to prevent the surface of the gate side wall from being damaged during the semiconductor structure formation process, thereby extending the service life of the gate side wall, and by adjusting the thickness of the silicon nitride layer 41, parasitic capacitance and device switching loss can be reduced; in addition, in the first embodiment of the present invention, the silicon nitride layer 41 is also used as a mask for ion implantation of the P-WELL layer 30 in the self-aligned process.

[0070] Embodiment 2

[0071] Reference Fig.16 As shown, the second embodiment of the present invention provides a MOSFET device, and the MOSFET device is obtained by the preparation method described in the first embodiment. The MOSFET device includes a silicon nitride layer 41 and gate polysilicon, and forms a P-WELL layer 30, an N Source layer 31 and a P-PLUS layer 32 by a self-alignment process, and the self-alignment process replaces multiple photolithography steps, with higher alignment accuracy, reducing the number of photolithography steps required for preparation, reducing production costs, and avoiding the introduction of impurities or defects during the photolithography process.

[0072] Embodiment 3

[0073] The inventors of this case have found that the parasitic body diode of MOSFET devices accounts for a large proportion of switching losses, and the device performance decreases under high temperature and high current. Currently, external anti-parallel Schottky barrier diodes (Schottky Barrier Diode, SBD) are used to improve switching performance. Since SBD has fast switching speed and low switching loss, it can provide a current path when the MOSFET is turned off, avoiding the parasitic body diode from bearing excessive current and producing bipolar degradation effect, thereby increasing the on-resistance of the device. However, external anti-parallel SBDs are prone to introduce more parasitic capacitance and inductance, affecting device reliability, and on the other hand, they bring problems in terms of preparation cost and total chip area. Accordingly, referring to Fig.17As shown, embodiment 3 of the present invention provides a MOSFET device integrated with an SBD structure, integrating the SBD into the MOSFET device, which includes a MOSFET device as described in embodiment 2, and also includes a Schottky contact metal layer 90, wherein the Schottky contact metal layer 90 is located on the top of the protrusion 22 and between the silicon nitride layers 41 on both sides.

[0074] In the third embodiment of the present invention, the preparation method of the MOSFET device integrated SBD structure is to obtain the following by the preparation method provided in the first embodiment: Fig.16 A MOSFET device is shown, and then a front Schottky metal is formed between the silicon nitride layer 41 through photolithography, metallization and stripping processes, and the Schottky contact metal layer 90 is formed through Schottky annealing to generate an SBD structure. The MOSFET device with an integrated SBD structure provided in the third embodiment of the present invention can enhance the freewheeling capability, suppress the opening of the parasitic body diode, and save the total packaging area at the same time, with high integration, avoid the introduction of parasitic capacitance and inductance, and have higher reliability.

[0075] Obviously, the above embodiments are merely examples for the purpose of clear explanation and are not intended to limit the implementation methods. For those skilled in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all the implementation methods here. The obvious changes or modifications derived therefrom are still within the scope of protection of the present invention.

Claims

1. A method for preparing a MOSFET device, characterized in that: include, Step S1, growing an N-type epitaxial region on the surface of a silicon carbide N+ substrate, and etching the N-type epitaxial region to form an epitaxial layer; Wherein, the top of the epitaxial layer includes a protruding portion and a first boundary arranged at the same height on both sides of the protruding portion in the width direction; Step S2, depositing a silicon nitride layer, which is located on both sides of the protrusion in the width direction; performing ion implantation into the epitaxial layer along the first boundary, shielding the silicon nitride layer, and forming a P-WELL layer on both sides of the epitaxial layer in the width direction; Step S3, depositing a first gate polysilicon layer, which is respectively located on a side of the silicon nitride layer away from the protruding portion; performing ion implantation into the epitaxial layer along the boundary of the P-WELL layer, and forming an N Source layer through shielding by the first gate polysilicon layer; Step S4, depositing a first oxide layer, which is respectively located on a side of the first gate polysilicon layer away from the silicon nitride layer; performing ion implantation into the N Source layer and the P-WELL along a boundary of the N Source layer, and forming a P-PLUS layer through shielding by the first oxide layer; Step S5, etching and removing the first gate polysilicon layer and the first oxide layer; Step S6, depositing and etching to obtain a second oxide layer and a second gate polysilicon layer.

2. The method for preparing a MOSFET device according to claim 1, characterized in that: In the step S1, a second boundary is formed above the protruding portion, the width of the second boundary is 2000nm~5000nm, the height difference between the second boundary and the first boundary is 1000nm~3000nm; the width of the first boundary on both sides is 3000nm~6000nm.

3. The method for preparing a MOSFET device according to claim 1, wherein: In step S2, the silicon nitride layer is deposited by: Depositing silicon nitride along the boundary above the epitaxial layer, and etching the silicon nitride to obtain the silicon nitride layer, wherein the bottom of the silicon nitride layer contacts at least a portion of the first boundary, and the width of the silicon nitride layer is 200 nm to 500 nm; In the step S2, the P-WELL impurity ion is implanted once or multiple times to obtain the P-WELL layer, the thickness of which is 600nm~1500nm.

4. The method for preparing a MOSFET device according to claim 1, wherein: In step S3, the first gate polysilicon layer is deposited by: A first polysilicon is deposited on the top of the device obtained in step S2, and the first polysilicon is etched to obtain the first gate polysilicon layer, wherein the bottom of the first gate polysilicon layer contacts at least a portion of the top of the P-WELL layer, and the width of the first gate polysilicon layer is 100nm~800nm.

5. The method for preparing a MOSFET device according to claim 1 or 4, characterized in that: In the step S3, after one or more N Source impurity ion implantations, the N Source layer is obtained, and the thickness of the N Source layer is 200 nm to 800 nm; the thickness of the N Source layer is less than the thickness of the P-WELL layer.

6. The method for preparing a MOSFET device according to claim 1, characterized in that: In step S4, the first oxide layer is deposited by: A first oxide region is deposited on the top of the device obtained in step S3, and the first oxide region is etched to obtain the first oxide layer, wherein the bottom of the first oxide layer contacts at least a portion of the top of the N Source layer, and the width of the first oxide layer is 2000nm~5000nm.

7. The method for preparing a MOSFET device according to claim 1 or 6, characterized in that: In the step S4, the P-PLUS layer is obtained through one or more P-PLUS impurity ion implantations, and the thickness of the P-PLUS layer is the sum of the thicknesses of the P-WELL layer and the N Source layer.

8. The method for preparing a MOSFET device according to claim 1, wherein: The step S6 comprises: Step S61, depositing a second oxide layer on the top of both sides of the protrusion, wherein the thickness of the second oxide layer is 300nm-800nm; Step S62, depositing a second polysilicon on the top of the device obtained in step S61, etching the second polysilicon to obtain the second gate polysilicon layer, the second gate polysilicon layer is respectively located on the side of the silicon nitride layer away from the protruding portion; at the same time, etching the second oxide layer to retain the area located at the bottom of the second gate polysilicon layer, the width of the second gate polysilicon layer and the second oxide layer are both 300nm~1200nm.

9. A MOSFET device, characterized in that: The MOSFET device is obtained by the preparation method according to any one of claims 1 to 8.

10. The MOSFET device according to claim 9, characterized in that: It also includes a Schottky contact metal layer, which is located on the top of the protrusion and between the silicon nitride layers on both sides.

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