Display data compensation control method and device, electronic equipment and storage medium

Abstract

The application provides a display data compensation control method and device, electronic equipment and storage medium. The display data compensation control method receives display data sent by an upper computer; determines a frame number category corresponding to the display image data according to a field synchronization signal; and in the case of compensation frames, performs algorithm compensation on the display image data based on an algorithm compensation circuit; in the case of non-compensation frames, filters the clock signal of the algorithm compensation circuit. The display data compensation control method filters the clock signal of the algorithm compensation circuit in the case of non-compensation frames, which can reduce the power consumption of the algorithm compensation circuit, reduce the heat generation of the chip, and improve the overall performance of the chip.

Description

Technical Field

[0001] This application relates to the field of display technology, and more specifically, to a display data compensation control method, apparatus, electronic device, and storage medium. Background Technology

[0002] Compared to traditional LCD panels, AMOLED displays offer faster response times, higher contrast ratios, and wider viewing angles. AMOLED display technology is already widely used in wearable devices, mobile phones, televisions, and other products, and it also has significant potential for future applications in flexible and transparent products.

[0003] However, due to manufacturing defects, AMOLED displays inevitably exhibit some visual defects, such as MURA, CROSSTALK, GIR, and LIR phenomena. These visual defects are difficult to compensate for and adjust using simple algorithms to achieve satisfactory visual effects. Therefore, existing visual effect compensation algorithms are highly complex, require large circuit areas, and consume high power, leading to severe chip overheating and impacting the overall chip performance.

[0004] Among them, MURA indicates a type of defect characterized by low contrast, uneven brightness, and irregular shape and area with an area greater than or equal to one pixel; CROSSTALK indicates a scene defect appearing in a bright background with dark blocks; GIR indicates a defect where "because the driver IC is located at one end of the panel, the panel and the driver IC are connected by a metal wire, and the resistance of this metal wire causes a drop in the power supply voltage entering the display area of ​​the panel, resulting in a decrease in the overall brightness of the displayed image on the panel and affecting the visual effect"; LIR indicates a defect where "because the sub-pixels in the AMOLED panel are evenly distributed from top to bottom, the sub-pixels on the panel are connected to the power supply voltage through a metal wire, and the metal wire itself contains resistance, the voltage drop of the resistance will reduce the actual power supply voltage reaching the sub-pixel, resulting in a decrease in the brightness when the sub-pixel emits light and affecting the visual effect". Summary of the Invention

[0005] In view of this, the purpose of this application is to provide a display data compensation control method, device, electronic device and storage medium to solve the technical problem that "existing visual effect compensation algorithms have high complexity, large circuit implementation area and high power consumption, which leads to serious heat generation and affects the overall performance of the chip".

[0006] In a first aspect, embodiments of this application provide a display data compensation control method, which includes:

[0007] Receive display data sent by the host computer; wherein, the display data includes display image data and field synchronization signal;

[0008] Based on the field synchronization signal, the frame number category corresponding to the displayed image data is determined; wherein, the frame number category includes compensated frames and uncompensated frames;

[0009] When the frame type is a compensation frame, the displayed image data is compensated using an algorithm compensation circuit.

[0010] When the frame number category is a non-compensated frame, the clock signal of the algorithm compensation circuit is filtered.

[0011] In the above implementation process, the display data compensation control method receives display data sent by the host computer; determines the frame category corresponding to the display image data based on the field synchronization signal; and performs algorithm compensation on the display image data based on the algorithm compensation circuit when the frame category is a compensation frame; and filters the clock signal of the algorithm compensation circuit when the frame category is a non-compensation frame. This reduces the power consumption of the algorithm compensation circuit, alleviates the chip's heat generation, and improves the overall performance of the chip. This display data compensation control method can solve the technical problem that "existing visual effect compensation algorithms are highly complex, have large circuit implementation areas, and high power consumption, leading to severe heat generation and affecting the overall performance of the chip."

[0012] Optionally, in this embodiment of the application, after the display image data is compensated by the algorithm compensation circuit, the method further includes: sending compensated image data and display image data corresponding to the uncompensated frame to the display device; wherein, the compensated image data refers to the image data obtained after the display image data is compensated by the algorithm compensation circuit.

[0013] In the above implementation process, by sending compensated image data and display image data corresponding to the uncompensated frame to the display device, the display device can display an image based on the received image data.

[0014] Optionally, in this embodiment of the application, filtering the clock signal of the algorithm compensation circuit when the frame number category is a non-compensated frame includes: turning off the clock signal of the algorithm compensation circuit based on the clock shutdown circuit when the frame number category is a non-compensated frame; or, turning off the power supply of the algorithm compensation circuit when the frame number category is a non-compensated frame.

[0015] In the above implementation process, the clock signal of the algorithm compensation circuit can be filtered by either shutting down the clock signal of the algorithm compensation circuit based on the clock shutdown circuit when the frame category is a non-compensated frame, or by disconnecting the power supply of the algorithm compensation circuit. By filtering the clock signal of the algorithm compensation circuit when the frame category is a non-compensated frame, the power loss corresponding to the change of logic state of the field-effect transistor in the case of a non-compensated frame can be eliminated, thereby reducing the power consumption of the algorithm compensation circuit, alleviating the heat generation of the chip, and improving the overall performance of the chip.

[0016] Optionally, in this embodiment of the application, the algorithm compensation circuit includes at least one of the following: DEMURA compensation module, CROSSTALK compensation module, GIR compensation module, and LIR compensation module.

[0017] Optionally, in this embodiment, the number of frames in the compensation frame is greater than or equal to the number of frames in the non-compensated frame.

[0018] In the above implementation process, by limiting the number of compensated frames to be greater than or equal to the number of non-compensated frames, a better visual compensation effect can be obtained.

[0019] Optionally, in the embodiments of this application, the compensation frame is one of an odd frame and an even frame, and the non-compensated frame is the other of the odd frame and the even frame.

[0020] In the above implementation process, by limiting "the compensation frame to one of odd and even frames, and the non-compensated frame to the other of odd and even frames", the displayed image data is compensated evenly, and then a display image with better visual compensation effect is obtained based on "compensated image data and the display image data corresponding to the non-compensated frame".

[0021] Optionally, in this embodiment of the application, the frame rate of the displayed image data is greater than or equal to 60Hz.

[0022] In the above implementation process, by limiting the frame rate of the displayed image data to be greater than or equal to 60Hz, the number of compensation frames can be greater than the refresh rate of the human eye; thus, without affecting the compensation visual effect, the proportion of compensation frames to the total number of displayed frames can be reduced, the power consumption of the algorithm compensation circuit can be reduced, the heat generation of the chip can be alleviated, and the overall performance of the chip can be improved.

[0023] Secondly, embodiments of this application also provide a display data compensation control device, which includes:

[0024] The display data receiving module is used to receive display data sent by the host computer; wherein, the display data includes display image data and field synchronization signal;

[0025] A frame number category determination module is used to determine the frame number category corresponding to the displayed image data based on the field synchronization signal; wherein, the frame number category includes compensated frames and uncompensated frames;

[0026] The algorithm compensation module is used to perform algorithm compensation on the displayed image data based on the algorithm compensation circuit when the frame number category is a compensation frame.

[0027] A clock filtering module is used to filter the clock signal of the algorithm compensation circuit when the frame number category is a non-compensated frame.

[0028] Optionally, in this embodiment of the application, the display data compensation control device further includes: a display data sending module, used to send compensated image data and display image data corresponding to the uncompensated frame to the display device; wherein, the compensated image data refers to image data obtained after performing algorithm compensation on the display image data based on the algorithm compensation circuit.

[0029] Optionally, in this embodiment, the clock filtering module is specifically used to: shut down the clock signal of the algorithm compensation circuit based on the clock shutdown circuit when the frame number category is a non-compensated frame; or, disconnect the power supply of the algorithm compensation circuit when the frame number category is a non-compensated frame.

[0030] Optionally, in the embodiments of this application, the above-mentioned algorithm compensation circuit includes at least one of the following: DEMURA compensation module, CROSSTALK compensation module, GIR compensation module, and LIR compensation module.

[0031] Optionally, in this embodiment of the application, the number of the compensated frames is greater than or equal to the number of the non-compensated frames.

[0032] Optionally, in the embodiments of this application, the compensation frame is one of an odd frame and an even frame, and the non-compensated frame is the other of the odd frame and the even frame.

[0033] Optionally, in this embodiment of the application, the frame rate of the displayed image data is greater than 60Hz.

[0034] Thirdly, embodiments of this application also provide an electronic device, including: a memory and a processor, wherein the memory stores a computer program executable by the processor, and when the computer program is executed by the processor, it performs the display data compensation control method as described in the first aspect above.

[0035] Fourthly, embodiments of this application also provide a computer-readable storage medium storing computer program instructions that, when executed by a processor, perform the display data compensation control method as described in the first aspect above.

[0036] Fifthly, embodiments of this application also provide a display system, including a host computer, a display device, and a display data compensation control device as described in the second aspect above; the display device is configured to display an image based on compensated image data and display image data whose frame number category is non-compensated frames; wherein, the compensated image data refers to image data obtained after performing algorithm compensation on the display image data based on an algorithm compensation circuit.

[0037] This application discloses a display data compensation control method, apparatus, electronic device, and storage medium. The method receives display data sent from a host computer; determines the frame category corresponding to the display image data based on the field synchronization signal; and performs algorithmic compensation on the display image data based on an algorithmic compensation circuit when the frame category is a compensation frame. When the frame category is a non-compensation frame, the clock signal of the algorithmic compensation circuit is filtered. This reduces the power consumption of the algorithmic compensation circuit, alleviates chip heat generation, and improves the overall performance of the chip. This display data compensation control method can solve the technical problem that "existing visual effect compensation algorithms are highly complex, have large circuit implementation areas, and high power consumption, leading to severe heat generation and affecting the overall performance of the chip." Attached Figure Description

[0038] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments of this application will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0039] Figure 1 A flowchart illustrating a display data compensation control method provided in an embodiment of this application;

[0040] Figure 2 This is a schematic diagram of the structure of a display driving circuit provided in an embodiment of this application;

[0041] Figure 3 This is a schematic diagram of the structure of a clock gating circuit provided in an embodiment of this application;

[0042] Figure 4 This is a schematic diagram of the structure of a display data compensation control device provided in an embodiment of this application;

[0043] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0044] The embodiments of the technical solution of this application will now be described in detail with reference to the accompanying drawings. These embodiments are only used to more clearly illustrate the technical solution of this application and are therefore merely examples, and should not be used to limit the scope of protection of this application.

[0045] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs; the terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit this application.

[0046] In the description of the embodiments of this application, technical terms such as "first" and "second" are used only to distinguish different objects and should not be construed as indicating or implying relative importance or implicitly specifying the number, specific order, or primary and secondary relationship of the indicated technical features. In the description of the embodiments of this application, "multiple" means two or more, unless otherwise explicitly defined.

[0047] Please see Figure 1 The illustrated diagram shows a flowchart of a display data compensation control method according to an embodiment of this application. This display data compensation control method may include the following steps:

[0048] Step 101: Receive display data sent by the host computer; wherein, the display data includes display image data and field synchronization signal;

[0049] Step 102: Determine the frame number category corresponding to the displayed image data based on the field synchronization signal; wherein the frame number category includes compensated frames and uncompensated frames;

[0050] Step 103: When the frame number category is a compensation frame, perform algorithm compensation on the displayed image data based on the algorithm compensation circuit;

[0051] Step 104: If the frame number category is a non-compensated frame, filter the clock signal of the algorithm compensation circuit.

[0052] In step 101, the vertical sync signal (VS) refers to "the pulse signal sent by the signal transmitter to the receiver after the vertical scan is completed, so that the vertical scanning pattern of the receiver is synchronized with the transmitter." The display data may also include horizontal sync signals (HS), CMD commands, and other data. In a liquid crystal display (LCD), the horizontal sync signal (HS) selects the effective horizontal signal range on the LCD panel, and the vertical sync signal (VS) selects the effective vertical signal range. The combined effect of the horizontal and vertical sync signals allows for the selection of the effective video signal range on the LCD panel. CMD commands can be algorithm configurations or dynamic algorithm switching configurations issued by a host computer.

[0053] In step 102, for a smartphone display, one field synchronization signal can correspond to one frame, meaning the field frequency (frequency of the field synchronization signal) and the frame frequency (display frame rate) can be the same. For example, if the field frequency is 60 fields / second, the corresponding frame rate is 60 frames / second. For a television display, two field synchronization signals can correspond to one frame, meaning the field frequency is twice the frame rate. For example, if the field frequency is 120 fields / second, the corresponding frame rate is 60 frames / second. Specifically, a counter can be used to count the field synchronization signals, and the frame category corresponding to the displayed image data can be determined based on the counting result. Compensation frames correspond to the number of frames that need algorithm compensation, and non-compensation frames correspond to the number of frames that do not need algorithm compensation. Specifically, odd-numbered frames (the (2n-1)th frame) can be used as compensation frames, and even-numbered frames (the 2nth frame) can be used as non-compensation frames; alternatively, the (3n-2)th and (3n-1)th frames can be used as compensation frames, and the 3nth frame as a non-compensation frame; where n is a positive integer.

[0054] In step 103, the algorithm compensation circuit may include at least one of a DEMURA compensation module, a CROSSTALK compensation module, a GIR compensation module, and an LIR compensation module. Specifically, the algorithm compensation circuit may include only one of the DEMURA compensation module, CROSSTALK compensation module, GIR compensation module, or LIR compensation module; it may also include both a DEMURA compensation module and an LIR compensation module, or both a GIR compensation module and a CROSSTALK compensation module, etc.

[0055] In step 104, "filtering the clock signal of the algorithm compensation circuit" is used to prevent changes in the logic state of the clock signal of the algorithm compensation circuit. This filtering operation can be specifically designed to prevent changes in the logic state of the clock signal. For example, if the frame type is a non-compensated frame, the clock signal of the algorithm compensation circuit can be turned off based on the clock shutdown circuit; or, if the frame type is a non-compensated frame, the power supply to the algorithm compensation circuit can be cut off. This achieves the filtering of the clock signal of the algorithm compensation circuit. By filtering the clock signal of the algorithm compensation circuit (preventing changes in the logic state of the clock signal), the dynamic power consumption in the circuit can be optimized, reducing the overall power consumption of the circuit.

[0056] Therefore, the display data compensation control method provided in this application receives display data sent by a host computer; determines the frame category corresponding to the display image data based on the field synchronization signal; and performs algorithm compensation on the display image data based on the algorithm compensation circuit when the frame category is a compensation frame; and filters the clock signal of the algorithm compensation circuit when the frame category is a non-compensation frame. This reduces the power consumption of the algorithm compensation circuit, alleviates chip heat generation, and improves the overall performance of the chip. This display data compensation control method can solve the technical problem that "existing visual effect compensation algorithms are highly complex, have large circuit implementation areas, and high power consumption, leading to severe heat generation and affecting the overall performance of the chip."

[0057] Please refer to Figure 2 , Figure 2 This is a schematic diagram of a display driving circuit provided in an embodiment of this application. Specifically, the display data compensation control method can be applied to a frame compensation control circuit in the display driving circuit, and the frame compensation control circuit can be implemented by the display data compensation control device described in the second aspect above. It is understood that... Figure 2 The diagram illustrates a scenario where the algorithm compensation circuit includes a DEMURA compensation module, a CROSSTALK compensation module, a GIR compensation module, and an LIR compensation module. Specifically, the display driver circuit can receive display data (including CMD commands, display image data, field synchronization signals, and line synchronization signals) sent by the host computer via the MIPI interface. The display driver circuit configures the algorithm and its dynamic development based on the CMD commands in the display data. The frame compensation control circuit determines the frame number category corresponding to the display image data based on the field synchronization signals in the display data. For display image data with a frame number category of compensation frame, the compensation switch of the algorithm compensation circuit is turned on; for display image data with a frame number category of non-compensation frame, the compensation switch of the algorithm compensation circuit is turned off, and the clock signal of the algorithm compensation circuit is filtered. Figure 2The diagram illustrates a scenario where the clock signal of the algorithm compensation circuit is filtered based on a clock shutdown circuit. Then, display data following the compensation operation (compensated image data and display image data corresponding to the uncompensated frame) is sent to the display device, enabling the display device to display an image based on the received display data.

[0058] In some optional embodiments, after performing algorithmic compensation on the display image data of the frame number category as compensation frame in step 103, the display data compensation control method further includes: sending compensation image data and display image data corresponding to the non-compensation frame to the display device; wherein, the compensation image data refers to the image data obtained after performing algorithmic compensation on the display image data based on the algorithmic compensation circuit.

[0059] The display device can be a device with display function, such as a CRT monitor, LCD monitor, LED monitor, or AMOLED monitor.

[0060] In some optional embodiments, step 104, filtering the clock signal of the algorithm compensation circuit when the frame number category is a non-compensated frame, includes: turning off the clock signal of the algorithm compensation circuit based on the clock shutdown circuit when the frame number category is a non-compensated frame; or, turning off the power supply of the algorithm compensation circuit when the frame number category is a non-compensated frame.

[0061] The clock shutdown circuit can be implemented based on clock-gating. Please refer to [reference needed]. Figure 3 , Figure 3 This is a schematic diagram of a clock gating circuit provided in an embodiment of this application. It can be based on, for example... Figure 3 The clock gating circuit shown, or other existing clock gating circuits, can be used to shut off the clock signal of the algorithm compensation circuit, thereby preventing changes in the logic state of the clock signal; alternatively, the power supply to the algorithm compensation circuit can be cut off based on UPF technology, thus preventing changes in the logic state of the clock signal. Figure 3In this context, ENABLE represents the enable signal sent by the frame compensation control circuit to the clock gating circuit, CLK represents the clock signal of the algorithm compensation circuit, and GCLK represents the clock signal processed by the clock gating circuit. The GCLK signal is obtained by ANDing the CLK signal with the signal output from the Q terminal. Specifically, when the frame type is a compensation frame, the value of ENABLE is 1. In this case, the clock signal processed by the clock gating circuit has the same level as the clock signal input to the clock gating circuit. When the frame type is a non-compensation frame, the value of ENABLE is 0. In this case, the clock signal processed by the clock gating circuit is low, effectively turning off the clock signal of the algorithm compensation circuit and preventing changes in the clock signal's logic state.

[0062] In some optional embodiments, the algorithm compensation circuit includes at least one of the following: DEMURA compensation module, CROSSTALK compensation module, GIR compensation module, and LIR compensation module.

[0063] The algorithm compensation circuit may include only one of the following modules: DEMURA compensation module, CROSSTALK compensation module, GIR compensation module, or LIR compensation module; or it may include all of these modules simultaneously. Specifically, if the display device is an LED display, the algorithm compensation circuit may include a CROSSTALK compensation module; if the display device is an AMOLED display, the algorithm compensation circuit may include a DEMURA compensation module and a CROSSTALK compensation module, or all of these modules simultaneously.

[0064] In some optional embodiments, the number of frames in the compensated frames is greater than or equal to the number of frames in the uncompensated frames.

[0065] By limiting the number of compensation frames to be greater than or equal to the number of non-compensation frames, and by performing algorithmic compensation on the display image data corresponding to the compensation frames, a better visual compensation effect can be obtained.

[0066] In some alternative embodiments, the compensated frame is one of an odd frame and an even frame, and the uncompensated frame is the other of the odd frame and the even frame.

[0067] Specifically, the 2n-1th frame (odd frame) can be used as the compensation frame and the 2nth frame (even frame) can be used as the non-compensation frame; or, the 2nth frame (even frame) can be used as the compensation frame and the 2n-1th frame (odd frame) can be used as the non-compensation frame.

[0068] In some optional embodiments, the frame rate of the displayed image data is greater than or equal to 60Hz.

[0069] By limiting the frame rate of the displayed image data to be greater than or equal to 60Hz, even when the frame rate of the displayed image data is equal to 60Hz and the number of compensated frames is equal to the number of non-compensated frames, the frame rate of the compensated frames can still reach 30Hz, which makes the frame rate of the compensated frames greater than the refresh rate of the human eye (24Hz). Thus, without affecting the compensated visual effect, the proportion of the compensated frames to the total number of displayed frames can be reduced, thereby reducing the power consumption of the algorithm compensation circuit, alleviating the heat generation of the chip, and improving the overall performance of the chip.

[0070] Please refer to Figure 4 , Figure 4 A schematic diagram of a display data compensation control device provided in an embodiment of this application. The display data compensation control device includes:

[0071] The display data receiving module 201 is used to receive display data sent by the host computer; wherein, the display data includes display image data and field synchronization signal;

[0072] The frame number category determination module 202 is used to determine the frame number category corresponding to the displayed image data based on the field synchronization signal; wherein, the frame number category includes compensated frames and uncompensated frames;

[0073] Algorithm compensation module 203 is used to perform algorithm compensation on the displayed image data based on the algorithm compensation circuit when the frame number category is a compensation frame;

[0074] The clock filtering module 204 is used to filter the clock signal of the algorithm compensation circuit when the frame number category is a non-compensated frame.

[0075] It should be understood that this display data compensation control device corresponds to the above-described display data compensation control method embodiment and is capable of executing the various steps involved in the above method embodiment. The specific functions of this display data compensation control device can be found in the description above; to avoid repetition, detailed descriptions are appropriately omitted here. This display data compensation control device includes at least one software function module that can be stored in a memory or embedded in the device's operating system (OS) in the form of software or firmware.

[0076] Please refer to Figure 5 , Figure 5This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. The electronic device 300 provided in this application includes a processor 301 and a memory 302. These components are interconnected and communicate with each other via a communication bus 303 and / or other forms of connection mechanisms (not shown). The memory 302 stores a computer program executable by the processor 301. When the computer program is executed by the processor 301, it performs the display data compensation control method described above.

[0077] This application embodiment also provides a computer-readable storage medium storing computer program instructions, which are executed by processor 301 to perform the above-described display data compensation control method.

[0078] The storage medium can be implemented by any type of volatile or non-volatile storage device or a combination thereof, such as Static Random Access Memory (SRAM), Electrically Erasable Programmable Read-Only Memory (EEPROM), Erasable Programmable Read Only Memory (EPROM), Programmable Red-Only Memory (PROM), Read-Only Memory (ROM), magnetic storage, flash memory, magnetic disk, or optical disk.

[0079] It should be understood that the disclosed apparatus and methods can also be implemented in other ways, given the several embodiments provided in this application. The apparatus embodiments described above are merely illustrative. For example, the flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of apparatus, methods, and computer program products according to various embodiments of this application. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code, which contains one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions marked in the blocks may occur in a different order than those marked in the drawings. For example, two consecutive blocks may actually be executed substantially in parallel, or they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in a block diagram and / or flowchart, and combinations of blocks in block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or action, or using a combination of dedicated hardware and computer instructions.

[0080] In addition, the functional modules in the various embodiments of this application can be integrated together to form an independent part, or each module can exist independently, or two or more modules can be integrated to form an independent part.

[0081] The above description is only an optional implementation of the embodiments of this application, but the protection scope of the embodiments of this application is not limited thereto. Any changes or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the embodiments of this application should be covered within the protection scope of the embodiments of this application.

Claims

1. A display data compensation control method, characterized in that, The method includes: Receive display data sent by the host computer; wherein, the display data includes display image data and field synchronization signal; Based on the field synchronization signal, the frame number category corresponding to the displayed image data is determined; wherein, the frame number category includes compensated frames and uncompensated frames; When the frame type is a compensation frame, the displayed image data is compensated using an algorithm compensation circuit. When the frame number category is a non-compensated frame, the clock signal of the algorithm compensation circuit is filtered. The step of determining the frame category corresponding to the displayed image data based on the field synchronization signal includes: using a counter to count the field synchronization signal, and determining the frame category corresponding to the displayed image data based on the counting result; the compensated frame is one of the odd frame and the even frame, and the uncompensated frame is the other of the odd frame and the even frame.

2. The method according to claim 1, characterized in that, After performing algorithmic compensation on the displayed image data based on the algorithmic compensation circuit, the method further includes: The compensation image data and the display image data corresponding to the uncompensated frame are sent to the display device; wherein, the compensation image data refers to the image data obtained after the display image data is algorithmically compensated based on the algorithm compensation circuit.

3. The method according to claim 1, characterized in that, in, When the frame number category is a non-compensated frame, filtering the clock signal of the algorithm compensation circuit includes: When the frame number category is a non-compensated frame, the clock signal of the algorithm compensation circuit is turned off based on the clock shutdown circuit; or, If the frame type is a non-compensated frame, the power supply to the algorithm compensation circuit is turned off.

4. The method according to claim 1, characterized in that, in, The algorithm compensation circuit includes at least one of the following: DEMURA compensation module, CROSSTALK compensation module, GIR compensation module, and LIR compensation module.

5. The method according to claim 1, characterized in that, in, The number of frames in the compensated frames is greater than or equal to the number of frames in the uncompensated frames.

6. The method according to claim 1, characterized in that, in, The frame rate of the displayed image data is greater than or equal to 60Hz.

7. A display data compensation control device, characterized in that, The device includes: The display data receiving module is used to receive display data sent by the host computer; wherein, the display data includes display image data and field synchronization signal; A frame number category determination module is used to determine the frame number category corresponding to the displayed image data based on the field synchronization signal; wherein, the frame number category includes compensated frames and uncompensated frames; The algorithm compensation module is used to perform algorithm compensation on the displayed image data based on the algorithm compensation circuit when the frame number category is a compensation frame. A clock filtering module is used to filter the clock signal of the algorithm compensation circuit when the frame number category is a non-compensated frame. The frame number category determination module is specifically used to: count the field synchronization signal using a counter, and determine the frame number category corresponding to the displayed image data based on the counting result; the compensated frame is one of the odd frame and the even frame, and the uncompensated frame is the other of the odd frame and the even frame.

8. An electronic device, characterized in that, The electronic device includes: Memory; processor; The memory stores a computer program executable by the processor, which, when executed by the processor, performs the method described in any one of claims 1-6.

9. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores computer program instructions that, when executed by a processor, perform the method described in any one of claims 1-6.

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