Array substrate, display panel and related device

Abstract

The application provides an array substrate, a display panel and a related device. The array substrate comprises a display area and a non-display area surrounding the display area. The non-display area comprises a multiplexing unit, a test unit and a binding unit. At least two of the multiplexing unit, the test unit and the binding unit are located at different side edges of the non-display area, so that the phenomenon of local area overheating caused by the centralized arrangement of the multiplexing unit, the test unit and the binding unit can be avoided, and the service life is prolonged.

Description

Technical Field

[0001] This invention relates to the field of display technology, and in particular to an array substrate, a display panel, and related devices. Background Technology

[0002] A head-up display (HUD) system projects important driving data, such as vehicle data and navigation information, onto the windshield to improve safety while driving.

[0003] Existing vehicle HUD systems using liquid crystal display (LCD) screens suffer from severe localized heat generation due to high backlight levels, which affects the lifespan of the LCD screen. Summary of the Invention

[0004] The present invention provides an array substrate, a display panel, and related devices to extend service life.

[0005] A first aspect of the present invention provides an array substrate comprising:

[0006] Display area and non-display area surrounding the display area;

[0007] The non-display area includes a multiplexing unit, a test unit, and a bonding unit; at least two of the multiplexing unit, the test unit, and the bonding unit are located on different sides of the non-display area.

[0008] In the array substrate provided by the present invention, the multiplexing unit is located on the first side of the non-display area; the test unit is located on the second side of the non-display area; the first side and the second side are arranged opposite to each other.

[0009] In the array substrate provided by the present invention, the multiplexing unit includes a first part and a second part; the testing unit includes a third part and a fourth part;

[0010] The first part of the multiplexing unit and the third part of the test unit are arranged side by side on the first side along the extension direction of the first side of the non-display area;

[0011] The second part of the multiplexing unit and the fourth part of the test unit are arranged side by side on the second side along the extension direction of the second side of the non-display area;

[0012] The first side is positioned opposite the second side.

[0013] In the array substrate provided by the present invention, the bonding unit is located on the third side of the non-display area; the third side is located on the same side as the first side and the second side.

[0014] In the array substrate provided by the present invention, the non-display area further includes a gate driving circuit; the gate driving circuit is located on the fourth side of the non-display area; the fourth side is located on the same side as the first side and the second side, and is disposed opposite to the third side.

[0015] In the array substrate provided by the present invention, the non-display area further includes a gate driving circuit; the gate driving circuit is at least partially located on the third side of the non-display area; on the third side of the non-display area, the gate driving circuit is located on the side of the bonding unit closer to the display area.

[0016] In the array substrate provided by the present invention, the non-display area further includes a first signal trace and a second signal trace; wherein one end of the first signal trace is electrically connected to a multiplexing unit and the other end is electrically connected to a bonding unit; one end of the second signal trace is electrically connected to a test unit and the other end is electrically connected to a bonding unit.

[0017] On the third side of the non-display area, there is a first overlap area between the first signal trace and the gate driving circuit; within the first overlap area, the first signal trace and the gate driving circuit are located in different film layers.

[0018] On the third side of the non-display area, there is a second overlap region between the second signal trace and the gate driving circuit. Within the second overlap region, the second signal trace and the gate driving circuit are located in different film layers.

[0019] In the array substrate provided by the present invention, the first signal trace includes a fifth portion, a first connection portion, and a sixth portion; the sixth portion overlaps with the gate driving circuit portion to form a first overlap region; one end of the fifth portion is connected to a multiplexing unit, and one end of the sixth portion is connected to a bonding unit; the other end of the fifth portion is connected to the other end of the sixth portion through the first connection portion; the sixth portion and the gate driving circuit are located in different film layers, and are located in different film layers from the fifth portion.

[0020] The second signal trace includes a seventh part, a second connection part, and an eighth part; the eighth part overlaps with the gate drive circuit part to form a second overlap region; one end of the seventh part is connected to the test unit, and one end of the eighth part is connected to the bonding unit; the other end of the seventh part is connected to the other end of the eighth part through the second connection part; the eighth part and the gate drive circuit are located in different film layers, and are located in different film layers from the seventh part.

[0021] The array substrate provided by the present invention further includes:

[0022] The multiplexing unit, test unit, bonding unit, gate drive circuit, first signal trace and second signal trace are all located on the substrate.

[0023] The sixth part of the first signal trace is located in the film layer between the film layer containing the gate drive circuit and the substrate.

[0024] The eighth part of the second signal trace is located in a film layer between the film layer containing the gate drive circuit and the substrate.

[0025] The array substrate provided by the present invention further includes:

[0026] The first metal layer is located on one side of the substrate.

[0027] The second metal layer is located on the side of the first metal layer that is away from the substrate.

[0028] The third metal layer is located on the side of the second metal layer that is opposite to the first metal layer;

[0029] The sixth part of the first signal trace is located only in the first metal layer; the fifth part of the first signal trace is located at least simultaneously in the second metal layer and the third metal layer, and the part of the same first signal trace located in the second metal layer and the part located in the third metal layer are interconnected.

[0030] The eighth portion of the second signal trace is located only in the first metal layer; the seventh portion of the second signal trace is located in at least both the second and third metal layers, and the portion of the same first signal trace located in the second metal layer and the portion located in the third metal layer are interconnected.

[0031] In the array substrate provided by the present invention, one end of the first connection portion of the first signal trace is connected to the fifth portion of the first signal trace located in the third metal layer, and the other end is connected to the sixth portion of the first signal trace through a via through an insulating layer between the first metal layer and the third metal layer.

[0032] One end of the second connection portion of the second signal trace is connected to the seventh portion of the second signal trace located in the third metal layer, and the other end is connected to the eighth portion of the second signal trace through a via that passes through the insulating layer between the first metal layer and the third metal layer.

[0033] In the array substrate provided by the present invention, the third side of the non-display area is connected to one end of the first side and one end of the second side, respectively, and the fourth side is connected to the other end of the first side and the other end of the second side, respectively.

[0034] The lengths of the first and second sides are both greater than the lengths of the third and fourth sides; the gate driving circuit is located on the third side of the non-display area and / or on the fourth side of the non-display area.

[0035] A second aspect of the present invention provides a display panel comprising an array substrate as described above.

[0036] A third aspect of the present invention provides a display device comprising a display panel according to any one of the preceding claims.

[0037] A fourth aspect of the present invention provides a head-up display system comprising the display device described in any of the above.

[0038] The beneficial effects of this invention are as follows:

[0039] This invention provides an array substrate, a display panel, and related devices. The array substrate includes a display area and a non-display area surrounding the display area. The non-display area includes a multiplexing unit, a testing unit, and a bonding unit. At least two of the multiplexing unit, testing unit, and bonding unit are located on different sides of the non-display area, which can avoid localized overheating caused by concentrating the multiplexing unit, testing unit, and bonding unit together, thereby extending the service life. Attached Figure Description

[0040] To more clearly illustrate the technical solutions of the embodiments of the present invention, the drawings used in the embodiments of the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0041] Figure 1 This is one of the top view structural schematic diagrams of the array substrate provided in the embodiments of the present invention;

[0042] Figure 2 This is a second top view of the array substrate provided in an embodiment of the present invention;

[0043] Figure 3 This is the third top view schematic diagram of the array substrate provided in the embodiment of the present invention;

[0044] Figure 4 This is the fourth top view schematic diagram of the array substrate provided in the embodiment of the present invention;

[0045] Figure 5 Fifth schematic diagram of the top view structure of the array substrate provided in the embodiment of the present invention;

[0046] Figure 6 This is the sixth top view schematic diagram of the array substrate provided in the embodiment of the present invention;

[0047] Figure 7a This is a partially enlarged schematic diagram of the array substrate provided in an embodiment of the present invention;

[0048] Figure 7b This is a cross-sectional view of the array substrate provided in an embodiment of the present invention. Detailed Implementation

[0049] To make the above-mentioned objects, features, and advantages of the present invention more apparent and understandable, the present invention will be further described below in conjunction with the accompanying drawings and embodiments. However, the exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided to make the present invention more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the figures denote the same or similar structures, and therefore repeated descriptions of them will be omitted. Terms describing position and direction in the present invention are illustrative based on the accompanying drawings, but changes can be made as needed, and all such changes are included within the scope of protection of the present invention. The accompanying drawings of the present invention are for illustrative purposes only and do not represent actual proportions.

[0050] A head-up display (HUD) system projects important driving data, such as vehicle data and navigation information, onto the windshield to improve safety while driving.

[0051] Existing vehicle HUD systems using liquid crystal display (LCD) screens suffer from severe localized heat generation due to high backlight levels, which affects the lifespan of the LCD screen.

[0052] In view of this, the present invention provides an array substrate to solve the above problems.

[0053] Figure 1 This is one of the top view structural schematic diagrams of the array substrate provided in an embodiment of the present invention.

[0054] like Figure 1 As shown, the array substrate includes a display area S1 and a non-display area S2 surrounding the display area S1.

[0055] The display area S1 includes intersecting data lines D and gate lines G. Two adjacent data lines D and two adjacent gate lines G intersect to define a pixel unit. Each pixel unit includes a thin-film transistor (TFT) t and a pixel electrode p. The gate of the TFT t is connected to the gate line G, the source of the TFT t is connected to the data line D, and the drain of the TFT t is connected to the pixel electrode p. Scan signals and data signals are applied to the TFT t through the gate line G and the data line D, respectively, controlling the TFT t to conduct and thus inputting voltage to the pixel electrode p.

[0056] The non-display area S2 includes a multiplexer (MUX) unit 10, a cell test (CT) unit 20, and a bonding unit 30. The multiplexer unit 10, during image display, sequentially opens multiple adjacent data lines D within the time it takes for one row of gate lines G to be open, thereby reducing the number of drive lines on the array substrate. For example, in... Figure 1 In the array substrate shown, the multiplexing unit 10 may include a 1:2 multiplexing circuit. During the time a row of gate lines G is open, the multiplexing unit 10 can sequentially open two adjacent columns of data lines D. In specific implementations, the multiplexing unit 10 may include multiplexing circuits with other ratios, which are not limited here. The test unit 20 is connected to the gate lines G and data lines D respectively, and is used to perform lamp-on testing after the liquid crystal display panel cell assembly process is completed, in order to detect defects such as line defects and surface defects in the liquid crystal display panel. The bonding unit 30 includes multiple connection terminals, each of which is connected to the multiplexing unit 10, the test unit 20, and other driving units disposed on the array substrate. The bonding unit 30 is used to bond with connectors such as flexible printed circuit boards (FPCs) through the connection terminals, and then connect to the driver chip (IC) through the FPC connectors, or directly bond the driver chip to the bonding unit, thereby electrically connecting the driver chip to the multiplexing unit 10, the test unit 20, and other driving units on the array substrate, and driving through the input driving signal of the driver chip. Unless otherwise specified, the embodiments of the present invention Figure 1 The connections between the multiplexing unit 10, the test unit 20, and the bonding unit 30, as well as the connections between the multiplexing unit 10 and the test unit 20 and the gate line G and the data line D, and other connections shown in the following figures are only used to illustrate the connection relationships between the components and do not represent the actual number of signal lines or their specific locations.

[0057] In this embodiment of the invention, at least two of the multiplexing unit 10, the testing unit 20, and the bonding unit 30 are located on different sides of the non-display area S2, thereby dispersing the multiplexing unit 10, the testing unit 20, and the bonding unit 30 relatively around the array substrate. Specifically, when the display panel made using the array substrate provided in this embodiment of the invention displays images, the multiplexing unit 10, the testing unit 20, and the bonding unit 30 all generate a certain amount of heat during operation. Since the multiplexing unit 10, the testing unit 20, and the bonding unit 30 are relatively dispersed around the array substrate, the heat-generating areas of the display panel can be dispersed. This avoids the phenomenon of localized overheating of the display panel caused by concentrating the multiplexing unit 10, the testing unit 20, and the bonding unit 30, thus avoiding the risk of liquid crystal failure in that area due to localized overheating and improving the service life of the liquid crystal display panel.

[0058] In some embodiments, such as Figure 1 As shown, the multiplexing unit 10 is located on the first side S21 of the non-display area S2, and the test unit 20 is located on the second side S22 of the non-display area S2. Since the first side S21 and the second side S22 are located on different sides of the non-display area S2, the heat-generating areas formed by the multiplexing unit 10 and the test unit 20 can be dispersed, avoiding excessively high temperatures in localized areas. Furthermore, by placing the multiplexing unit 10 and the test unit 20 on different sides of the non-display area S2, the bonding unit 30 can be located on the same side as either the multiplexing unit 10 or the test unit 20. Compared to placing the multiplexing unit 10, the test unit 20, and the bonding unit 30 all on the same side of the non-display area, the width of the side where the bonding unit 30 is located can be reduced, thereby reducing the bezel width of the display panel after the driver IC is bonded, which is beneficial for narrow bezel design.

[0059] In some embodiments, such as Figure 1 As shown, the first side S21 of the non-display area S2 is positioned opposite to the second side S22 of the non-display area S2, which is not limited here.

[0060] Figure 2 This is a second top view of the array substrate provided in an embodiment of the present invention.

[0061] In some embodiments, such as Figure 2As shown, the multiplexing unit 10 includes a first part 11 and a second part 12, and the testing unit 20 includes a third part 21 and a fourth part 22. The first part 11 of the multiplexing unit 10 and the third part 21 of the testing unit 20 are arranged side-by-side on the first side S21 along the extension direction of the first side S21 of the non-display area S2; the second part 12 of the multiplexing unit 10 and the fourth part 22 of the testing unit 20 are arranged side-by-side on the second side S22 along the extension direction of the second side S22 of the non-display area. In this embodiment, dividing the multiplexing unit 10 into multiple parts and distributing each part of the multiplexing unit to different sides of the non-display area S2, and similarly dividing the testing unit 20 into multiple parts and distributing each part of the testing unit to different sides of the non-display area S2, can also disperse the heat-generating areas on the array substrate, avoiding excessively high temperatures in localized areas.

[0062] In some embodiments, such as Figure 2 As shown, the first side S21 of the non-display area S2 is positioned opposite to the second side S22 of the non-display area S2. Furthermore, the first portion 11 of the multiplexing unit 10 located on the first side S21 is positioned opposite to the fourth portion 22 of the test unit 20 located on the second side S22, and the third portion 21 of the test unit 20 located on the first side S21 is positioned opposite to the second portion 12 of the multiplexing unit located on the second side S22. In a specific implementation, as follows... Figure 2As shown, the first part 11 of the multiplexing unit 10 is continuously arranged, and the third part 21 of the test unit 20 is continuously arranged. The first part 11 of the multiplexing unit 10 and the third part 21 of the test unit 20 are arranged side by side on the first side S21 of the non-display area S2 along the extension direction of the first side S21. The second part 12 of the multiplexing unit 10 is continuously arranged, and the fourth part 22 of the test unit 20 is continuously arranged. The second part 12 of the multiplexing unit 10 and the fourth part 22 of the test unit 20 are arranged side by side on the second side S22 of the non-display area S2 along the extension direction of the second side S22. In some embodiments, the first part 11 of the multiplexing unit 10 may include a plurality of sub-parts spaced apart from each other, and the third part 21 of the test unit 20 may include a plurality of sub-parts spaced apart from each other. The sub-parts of the first part 11 of the multiplexing unit 10 and the sub-parts of the third part 21 of the test unit 20 are arranged side by side and intersecting each other along the extension direction of the first side S21. The second part 12 of the multiplexing unit 10 may include a plurality of sub-parts spaced apart from each other, and the fourth part 22 of the test unit 20 may include a plurality of sub-parts spaced apart from each other. The sub-parts of the second part 12 of the multiplexing unit 10 and the sub-parts of the fourth part 22 of the test unit 20 are arranged side by side and intersecting each other along the extension direction of the second side S22. This is not limited here.

[0063] Figure 3 This is the third top view schematic diagram of the array substrate provided in the embodiment of the present invention.

[0064] In some embodiments, the binding unit is located on the third side of the non-display area, and the third side is located on the same side as the first and second sides. For example... Figure 3 As shown, taking the multiplexing unit 10 and the test unit 20 respectively located on the first side S21 and the second side S22 opposite to the non-display area S2 as an example, the bonding unit 30 is located on the third side S23 of the non-display area S2, which is on the same side as the first side S21 and the second side S22. By placing the bonding unit 30 on the third side S23 of the non-display area S2, the bonding unit 30 is located on a different side from the multiplexing unit 10 and the test unit 30, thereby further dispersing the heat-generating area on the array substrate, avoiding a decrease in the temperature of the heat-generating area of ​​the array substrate, and further reducing the width of the side where the bonding unit 30 is located, thereby reducing the bezel width on the bonding side of the display panel driver IC, which is beneficial for further narrowing the bezel.

[0065] In some embodiments, the non-display area further includes a gate-on-array (GOA) circuit. The gate-on-array circuit is electrically connected to the gate line G in the display area S1 and is used to input a scan signal to the gate line G during image display, thereby controlling the gate of the thin-film transistor to turn on or off.

[0066] Figure 4 This is the fourth top view of the array substrate provided in an embodiment of the present invention.

[0067] In some embodiments, such as Figure 4 As shown, the gate driving circuit 24 is located on the fourth side S24 of the non-display area. The fourth side S24, along with the first side S21, the second side S22, and the third side S23, are all located on different sides of the non-display area. This disperses the gate driving circuit 40, the multiplexing unit 10, the test unit 20, and the bonding unit 30 around the non-display area S2, preventing the gate driving circuit 40 from generating heat and causing excessively high temperatures in localized areas.

[0068] In specific implementation, such as Figure 4 As shown, taking the multiplexing unit 10 located on the first side S21 of the non-display area S2 and the test unit 20 located on the second side S22 of the non-display area as an example, the four sides S24 can be located on the same side of the first side S21 and the second side S22, and are arranged opposite to the third side S23. The gate driving circuit 40 located on the fourth side S24 is arranged separately from the bonding unit 30 located on the third side S23, which can reduce the bezel width after the bonding unit 30 is bonded to the driver IC, thereby reducing the bezel width of the display panel.

[0069] Figure 5 The fifth schematic diagram of the top view of the array substrate provided in the embodiment of the present invention.

[0070] In some embodiments, the gate driving circuit 40 is at least partially located on the third side S23 of the non-display area S2, and the bonding unit 30 is located on the third side S23 of the non-display area S2. Specifically, as shown in the following implementation... Figure 5 As shown, a portion of the gate driving circuit 40 is located on the third side S23, and a portion is located on the fourth side S24. The third side S23 and the fourth side S24 are arranged opposite to each other. The array substrate can achieve bilateral driving through the gate driving circuit 40 located on the third side S23 and the gate driving circuit 40 located on the fourth side S24. Distributing the gate driving circuit 40 on the third side S23 and the fourth side S24 can also reduce the line density of the non-display area on one side, which is beneficial to signal routing design. In some embodiments, the gate driving circuit 40 can also be entirely disposed on the third side S23 of the non-display area S2, which is not limited here.

[0071] In some embodiments, such as Figure 5 As shown, the gate driving circuit 40 and the bonding unit 30 are arranged side by side on the third side S23 of the non-display area S2, with the gate driving circuit 40 located on the side of the bonding unit 30 closer to the display area S1.

[0072] In this embodiment of the invention, the non-display area S2 further includes a first signal trace and a second signal trace. One end of the first signal trace is electrically connected to the multiplexing unit 10, and the other end is electrically connected to the bonding unit 30. One end of the second signal trace is electrically connected to the test unit 20, and the other end is electrically connected to the bonding unit 30.

[0073] Figure 6 This is the sixth top view schematic diagram of the array substrate provided in the embodiment of the present invention.

[0074] In some embodiments, such as Figure 6 As shown, the bonding unit 30 is located on the third side S23 of the non-display area S2. Part or all of the gate driving circuit 40 is located on the third side S23, and the gate driving circuit 40 within the third side S23 is located on the side of the bonding unit 30 closest to the display area S1. The multiplexing unit 10 is located on the first side S21 of the non-display area S2, and the test unit 20 is located on the second side S22 of the non-display area. The first signal trace 13 is led out from the multiplexing unit 10, extends to the third side S23, and is electrically connected to the bonding unit 30. The second signal trace 23 is led out from the test unit 20, extends to the third side S23, and is electrically connected to the bonding unit 30.

[0075] In specific implementation, such as Figure 6 As shown, on the third side S23 of the non-display area S2, the first signal trace 13 and the gate driving circuit 40 have a first overlap area S41. The first signal trace 13 is routed within this first overlap area S41, avoiding routing around the periphery of the gate driving circuit 40. This reduces the area of ​​the third side S23 of the non-display area S2 used for signal traces, thereby reducing the width of the third side S23 and facilitating a narrow bezel design. Within the first overlap area S41, the first signal trace 13 and the gate driving circuit 40 are located in different film layers to avoid interference between their routing, thus reducing the complexity of the routing design. Figure 6As shown, on the third side S23 of the non-display area S2, the second signal trace 23 and the gate driving circuit 40 have a second overlapping area S42. The second signal trace 23 is routed within this second overlapping area S42, avoiding routing around the periphery of the gate driving circuit 40. This reduces the area of ​​the third side S23 of the non-display area S2 used for signal traces, thereby reducing the width of the third side S23 and facilitating a narrow bezel design. Within the second overlapping area S42, the second signal trace 23 and the gate driving circuit 40 are located in different film layers to avoid interference between their routing, thus reducing the complexity of the routing design.

[0076] In specific implementation, there can be multiple first signal traces 13. On the third side S23 of the non-display area S2, each first signal trace 13 overlaps with the gate driving circuit 40, or a portion of the first signal traces 13 overlaps with the gate driving circuit 40. Similarly, there can be multiple second signal traces 23. On the third side S23 of the non-display area S2, each second signal trace 23 overlaps with the gate driving circuit 40, or a portion of the second signal traces 23 overlaps with the gate driving circuit 40. No limitation is imposed here.

[0077] In some embodiments, the bonding unit 30 is located on the third side S23 of the non-display area S2. Part or all of the gate driving circuit 40 is located on the third side S23, and the gate driving circuit 40 within the third side S23 is located on the side of the bonding unit 30 closest to the display area S1. The multiplexing unit 10 and the test unit 20 can be disposed on other sides of the non-display area S2 besides the third side S23, and the multiplexing unit 10 and the test unit 20 can be disposed on the same side of the non-display area, without limitation. When the multiplexing unit 10 and the test unit 20 are electrically connected to the bonding unit 30 respectively, the first signal trace 13 has a first overlapping area with the gate driving circuit 40 within the third side S23, and the second signal trace 23 has a second overlapping area with the gate driving circuit 40 within the third side S23, thereby reducing the width of the third side S23. For specific implementation, refer to... Figure 6 The embodiments shown are not described in detail here.

[0078] In some embodiments, such as Figure 6As shown, the first signal trace 13 includes a fifth portion 131, a first connection portion 132, and a sixth portion 133. On the third side S23 of the non-display area S2, the sixth portion 133 partially overlaps with the gate driving circuit 40 to form a first overlapping area S41. One end of the fifth portion 131 is connected to the multiplexing unit 10, one end of the sixth portion 133 is connected to the bonding unit 30, and the other end of the fifth portion 131 is connected to the other end of the sixth portion 133 via the first connection portion 132. The sixth portion 133 and the gate driving circuit 40 are located in different film layers, and are also located in different film layers than the fifth portion 131. The first connection portion 132 does not overlap with the gate driving circuit 40, as shown... Figure 6 As shown, the first connecting portion 132 may be located on the first side S21 of the non-display area S2. In some embodiments, the first connecting portion 132 may be located on the third side S23 of the non-display area S2, which is not limited here.

[0079] The second signal trace 23 includes a seventh portion 231, a second connection portion 232, and an eighth portion 233. The eighth portion 233 partially overlaps with the gate drive circuit 40 to form a second overlap region S42. One end of the seventh portion 231 is connected to the test unit 20, and one end of the eighth portion 233 is connected to the bonding unit 30. The other end of the seventh portion 231 is connected to the other end of the eighth portion 233 via the second connection portion 232. The eighth portion 233 is located in a different film layer from the gate drive circuit 40 and in a different film layer from the seventh portion 231. The second connection portion 232 does not overlap with the gate drive circuit 40, as shown below. Figure 6 As shown, the second connecting portion 232 can be disposed on the second side S22 of the non-display area S2. In some embodiments, the second connecting portion 232 can be disposed on the third side S23 of the non-display area S2, which is not limited here.

[0080] Figure 7a This is a partially enlarged schematic diagram of the array substrate provided in an embodiment of the present invention; Figure 7b This is a cross-sectional view of the array substrate provided in an embodiment of the present invention.

[0081] Figure 7a for Figure 6 The enlarged schematic diagram of region a shows the first connection portion 132 of the first signal trace 13 and the adjacent fifth portion 132 and sixth portion 133. Figure 7b for Figure 7a A cross-sectional view along section line AA. (See figure) Figure 7bAs shown, the array substrate includes a substrate 1, and a multiplexing unit 10, a test unit 20, a bonding unit 30, a gate driving circuit 40, a first signal trace 13, and a second signal trace 23 are all disposed on the substrate 1. In a specific implementation, the multiplexing unit 10, the test unit 20, the bonding unit 30, the gate driving circuit 40, the first signal trace 13, and the second signal trace 23 can all be disposed on the same side of the substrate 1.

[0082] In some embodiments, a sixth portion 133 of the first signal trace 13 is disposed between the film layer containing the gate drive circuit 40 and the substrate 1. For example, as Figure 7b As shown, the array substrate further includes a first metal layer 2, a second metal layer 5, and a third metal layer 7 stacked along the layer away from the substrate 1. The first metal layer 2 includes a light-shielding layer between the active layer of the thin-film transistor in the display area and the substrate 1, used to block backlight during image display and prevent backlight from directly illuminating the active layer of the thin-film transistor, thus avoiding leakage current. The second metal layer 5 includes the gate of the thin-film transistor in the display area. The third metal layer 7 includes the source and drain of the thin-film transistor in the display area. The sixth portion 133 of the first signal trace 13 is located in the first metal layer 2 and is traced using the light-shielding metal layer. The lines of the gate driving circuit 40 can be traced in the second metal layer 5 and / or the third metal layer 7, thereby placing the sixth portion 133 of the first signal trace 13 and the gate driving circuit 40 in different film layers. In specific implementations, the lines of the gate driving circuit 40 can also be traced using other conductive film layers located on the side of the first metal layer 2 away from the substrate 1; this is not limited here.

[0083] In some embodiments, the eighth portion 233 of the second signal trace 23 is disposed between the film layer containing the gate drive circuit 40 and the substrate 1. The eighth portion 233 of the second signal trace 23 may be located in the same film layer as the sixth portion 133 of the first signal trace 13. The specific configuration can be made with reference to the sixth portion 133 of the first signal trace 13, which will not be elaborated here.

[0084] In some embodiments, the sixth portion 133 of the first signal trace 13 is located only in the first metal layer 2. The fifth portion 131 of the first signal trace 13 is located at least simultaneously in the second metal layer 5 and the third metal layer 7, and the portion of the same first signal trace 13 located in the second metal layer 5 and the portion located in the third metal layer 7 are interconnected. For example, such as Figure 7bAs shown, the fifth portion 131 of the first signal trace 13 is located in both the second metal layer 6 and the third metal layer 7. The portion of the first signal trace 13 located in the second metal layer 6 and the portion located in the third metal layer 7 are interconnected, thereby increasing the cross-sectional area of ​​the fifth portion 131 of the first signal trace 13, reducing resistance, and avoiding signal loss. In specific implementations, the fifth portion 131 of the same first signal trace 13 can also be located in more conductive film layers, including the second metal layer 5 and the third metal layer 7, and the portions of the fifth portion 131 of the same first signal trace 13 located in each film layer are interconnected, thereby further reducing resistance. This is not limited here.

[0085] In some embodiments, the eighth portion 233 of the second signal trace 23 is located only in the first metal layer 2. The seventh portion 231 of the second signal trace 23 is located at least simultaneously in the second metal layer 5 and the third metal layer 7, and the portion of the same second signal trace 23 located in the second metal layer 5 and the portion located in the third metal layer 7 are interconnected. For specific implementation, the configuration can be referenced to the first signal trace 13, and will not be elaborated here.

[0086] In some embodiments, such as Figure 7b As shown, the fifth portion 131 of the first signal trace 13 is located in both the second metal layer 5 and the third metal layer 7. One end of the first connecting portion 132 of the first signal trace 13 is connected to the fifth portion 131 of the first signal trace 13 located in the third metal layer 7, and the other end is connected to the sixth portion 133 of the first signal trace 13 through a via penetrating the insulating layer between the first metal layer 2 and the third metal layer 7. In a specific implementation, as shown... Figure 7bAs shown, the insulating layer between the first metal layer 2 and the third metal layer 7 includes a buffer layer 3, a gate insulating layer (GI) 4, and an interlayer insulating layer (ILD) 6. The portion of the fifth part 131 located in the second metal layer 5 is connected to the portion located in the third metal layer 7 through a via penetrating the interlayer insulating layer 6. The first connection portion 132 of the first signal trace 13 is located in the third metal layer 7, and one end of the fifth part 131 of the first signal trace 13 and one end of the first connection portion 132 are connected in the third metal layer 7. The other end of the first connection portion 132 is connected to the sixth part 133 of the first signal trace 13 located in the first metal layer 2 through a via penetrating the interlayer insulating layer 6, the gate insulating layer 4, and the buffer layer 3. In the prior art, it is typically necessary to create an opening in the interlayer insulating layer 6 after its formation and before the formation of the third metal layer 7, and then fill the opening with the third metal layer 7 to fabricate the source and drain electrodes of the thin-film transistor. In this embodiment, after forming the interlayer insulating layer 6 on the side of the second metal layer 5 away from the substrate 1, the existing hole-opening step is used to open vias in each insulating layer between the third metal layer 7 and the first metal layer 2 using a mask. Then, the circuit pattern of the third metal layer 7 is fabricated to simultaneously enable conduction between the portion of the first signal trace 13 located in the third metal layer 7 and the portion located in the second metal layer 5, as well as between the portion of the first signal trace 13 located in the third metal layer 7 and the portion located in the first metal layer 2. This avoids increasing the number of masks and can reduce manufacturing costs.

[0087] In some embodiments, the seventh portion 231 of the second signal trace 23 is located in both the second metal layer 5 and the third metal layer 7. One end of the second connection portion 232 of the second signal trace 13 is connected to the seventh portion of the second signal trace 23 located in the third metal layer 7, and the other end is connected to the eighth portion 233 of the second signal trace 23 through a via penetrating the insulating layer between the first metal layer 2 and the third metal layer 5. In specific implementations, the arrangement and connection method between the various portions of the second signal trace 23 can refer to the first signal trace 13, and will not be described in detail here.

[0088] In some embodiments, such as Figures 4-6As shown, the third side S23 of the non-display area S2 is connected to one end of the first side S21 and one end of the second side S22, respectively, and the fourth side S24 is connected to the other end of the first side S21 and the other end of the second side S22, respectively. The lengths of the first side S21 and the second side S22 are both greater than the lengths of the third side S23 and the fourth side S24. The gate driving circuit 40 is located on the third side S23 and / or the fourth side S24 of the non-display area S2. In a specific implementation, the array substrate can be rectangular. The gate driving circuit 40 is disposed on the two short sides of the rectangular array substrate, and the long side of each pixel unit in the display area is parallel to the third and fourth sides of the non-display area, while the short side of the pixel unit is parallel to the first and second sides of the non-display area. This achieves a horizontal screen display mode, avoiding the problem of increased driving algorithm design costs caused by using a vertical screen horizontally.

[0089] Based on the same inventive concept, embodiments of the present invention also provide a display panel, including the array substrate provided in any of the foregoing embodiments.

[0090] In some embodiments, the display panel may be a liquid crystal display (LCD) panel. The LCD panel further includes a counter substrate disposed opposite to the array substrate, and a liquid crystal layer located between the array substrate and the counter substrate. The display panel manufactured using the array substrate provided in the embodiments of the present invention can avoid excessively high temperatures in localized areas of the display panel, thereby improving the lifespan of the display panel. In specific implementations, the display panel provided in the embodiments of the present invention also has other technical effects similar to those of the array substrate provided in any of the foregoing embodiments, which will not be elaborated here.

[0091] In some embodiments, the display panel may also be other types of display panels, such as organic light-emitting diode (OLED) display panels, micro light-emitting diode (Micro LED) display panels, etc., and is not limited thereto. The display panel provided in this embodiment has the same technical effects as the array substrate provided in any of the foregoing embodiments, and will not be described in detail here.

[0092] Based on the same inventive concept, embodiments of the present invention also provide a display device, including the display panel provided in any of the foregoing embodiments.

[0093] In some embodiments, the display device provided in this invention can be a picture generation unit (PGU) of a head-up display (HUD) system. Using the image generation unit fabricated on the array substrate provided in this invention can avoid the problem of excessively high local temperatures on the display panel, which could affect the lifespan of the display panel. This allows for the use of higher backlight brightness to improve the display brightness of the PGU, thereby increasing the projection brightness of the HUD system.

[0094] In some embodiments, the display device provided in this invention may be a mobile phone, tablet computer, laptop computer, television, and monitor, etc., and is not limited thereto.

[0095] The display device provided in this embodiment of the invention has the same technical effects as the display panel provided in any of the foregoing embodiments, and will not be described in detail here.

[0096] Based on the same inventive concept, embodiments of the present invention also provide a head-up display system, including the display device provided in any of the above embodiments. The head-up display system provided in these embodiments can be applied to fields such as automotive, aerospace, and industrial manufacturing, and is not limited thereto. The head-up display system provided in these embodiments has the same technical effects as the display device provided in any of the foregoing embodiments, and will not be described in detail here.

[0097] Although preferred embodiments of the invention have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including both the preferred embodiments and all changes and modifications falling within the scope of the invention.

[0098] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. Therefore, if these modifications and variations fall within the scope of the claims of this invention and their equivalents, this invention also intends to include these modifications and variations.

Claims

1. An array substrate, characterized in that, include: The display area and the non-display area surrounding the display area; The non-display area includes a multiplexing unit, a testing unit, and a binding unit; At least two of the multiplexing unit, the testing unit, and the binding unit are located on different sides of the non-display area; The multiplexing unit includes a first part and a second part; the testing unit includes a third part and a fourth part. The first part of the multiplexing unit and the third part of the test unit are arranged side by side on the first side of the non-display area along the extension direction of the first side of the non-display area. The second part of the multiplexing unit and the fourth part of the test unit are arranged side by side on the second side of the non-display area along the extension direction of the second side of the non-display area. The first side is positioned opposite to the second side.

2. The array substrate as described in claim 1, characterized in that, The binding unit is located on the third side of the non-display area; the third side is located on the same side as the first side and the second side.

3. The array substrate as described in claim 2, characterized in that, The non-display area further includes a gate driving circuit; the gate driving circuit is located on the fourth side of the non-display area; the fourth side is located on the same side as the first side and the second side, and is disposed opposite to the third side.

4. The array substrate as described in claim 2, characterized in that, The non-display area further includes a gate driving circuit; the gate driving circuit is at least partially located on the third side of the non-display area; on the third side of the non-display area, the gate driving circuit is located on the side of the bonding unit closer to the display area.

5. The array substrate as described in claim 4, characterized in that, The non-display area further includes a first signal trace and a second signal trace; wherein one end of the first signal trace is electrically connected to the multiplexing unit and the other end is electrically connected to the bonding unit; one end of the second signal trace is electrically connected to the test unit and the other end is electrically connected to the bonding unit. On the third side of the non-display area, the first signal trace and the gate driving circuit have a first overlap region; within the first overlap region, the first signal trace and the gate driving circuit are located in different film layers; On the third side of the non-display area, there is a second overlap region between the second signal trace and the gate driving circuit. In the second overlap region, the second signal trace and the gate driving circuit are located in different film layers.

6. The array substrate as described in claim 5, characterized in that, The first signal trace includes a fifth portion, a first connection portion, and a sixth portion; the sixth portion overlaps with the gate driving circuit portion to form the first overlapping region; one end of the fifth portion is connected to the multiplexing unit, and one end of the sixth portion is connected to the bonding unit; the other end of the fifth portion is connected to the other end of the sixth portion through the first connection portion; the sixth portion and the gate driving circuit are located in different film layers, and are located in different film layers from the fifth portion; The second signal trace includes a seventh portion, a second connection portion, and an eighth portion; the eighth portion overlaps with the gate drive circuit portion to form the second overlap region; one end of the seventh portion is connected to the test unit, and one end of the eighth portion is connected to the bonding unit; the other end of the seventh portion is connected to the other end of the eighth portion through the second connection portion. The eighth part is located in a different film layer from the gate driving circuit and in a different film layer from the seventh part.

7. The array substrate as described in claim 6, characterized in that, Also includes: The substrate, the multiplexing unit, the test unit, the bonding unit, the gate drive circuit, the first signal trace and the second signal trace are all located on the substrate; The film layer containing the sixth portion of the first signal trace is located between the film layer containing the gate driving circuit and the substrate. The film layer containing the eighth portion of the second signal trace is located between the film layer containing the gate drive circuit and the substrate.

8. The array substrate as claimed in claim 7, characterized in that, Also includes: The first metal layer is located on one side of the substrate. The second metal layer is located on the side of the first metal layer that is away from the substrate. The third metal layer is located on the side of the second metal layer that is opposite to the first metal layer; The sixth portion of the first signal trace is located only in the first metal layer; The fifth portion of the first signal trace is located at least simultaneously in the second metal layer and the third metal layer, and the portion of the same first signal trace located in the second metal layer and the portion located in the third metal layer are interconnected. The eighth portion of the second signal trace is located only in the first metal layer; The seventh portion of the second signal trace is located at least simultaneously in the second metal layer and the third metal layer, and the portion of the same first signal trace located in the second metal layer and the portion located in the third metal layer are interconnected.

9. The array substrate as described in claim 8, characterized in that, One end of the first connection portion of the first signal trace is connected to the fifth portion of the first signal trace located in the third metal layer, and the other end is connected to the sixth portion of the first signal trace through a via penetrating the insulating layer between the first metal layer and the third metal layer. One end of the second connection portion of the second signal trace is connected to the seventh portion of the second signal trace located in the third metal layer, and the other end is connected to the eighth portion of the second signal trace through a via penetrating the insulating layer between the first metal layer and the third metal layer.

10. The array substrate as claimed in claim 3, characterized in that, The third side of the non-display area is connected to one end of the first side and one end of the second side, respectively, and the fourth side is connected to the other end of the first side and the other end of the second side, respectively. The lengths of the first side and the second side are both greater than the lengths of the third side and the fourth side; the gate driving circuit is located on the third side of the non-display area and / or on the fourth side of the non-display area.

11. A display panel, characterized in that, Includes the array substrate as described in any one of claims 1 to 10.

12. A display device, characterized in that, Includes the display panel as described in claim 11.

13. A head-up display system, characterized in that, Includes the display device as described in claim 12.

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