Linear image sensor and method of fabrication and photolithographic mask

Abstract

The application discloses a linear image sensor, a manufacturing method and a photoetching mask plate. The linear image sensor comprises a first chip area and a second chip area, the first chip area and the second chip area are arranged in sequence in a first preset direction, and the circuit arrangement of the first chip area is the same as that of the second chip area; the chip further comprises a plurality of pixels and a conductive circuit extending along a second preset direction, the first chip area and the second chip area are both provided with the pixels, the pixels in the first chip area and the second chip area are electrically connected with the conductive circuit, and the second preset direction has an included angle with the first preset direction. By dividing the linear image sensor into the first chip area and the second chip area with the same circuit arrangement in the first preset direction, and extending the conductive circuit connected with the pixels along the second preset direction, the circuit arranged in the first preset direction of the linear image sensor is reduced, and the difficulty of splicing the linear image sensor in the first preset direction is reduced.

Description

Technical Field

[0001] This invention relates to the field of chip technology, and in particular to a linear image sensor, its fabrication method, and a photomask. Background Technology

[0002] There are many types of chips, such as processors and image sensors. Regardless of the type, all chips undergo multiple exposure and development processes. Among image sensors, linear CMOS image sensors are quite special. Linear CMOS image sensors are "strip"-shaped linear image sensors, typically containing 2K, 4K, 8K, or 16K pixel units horizontally, but only a few or tens of pixels vertically.

[0003] Linear CMOS image sensors have a wide range of applications in industrial inspection, barcode scanning, scanners, machine vision, and other fields. For example, linear CMOS image sensors are suitable for use in copier scanning elements, image scanners, barcode scanners, line scan cameras for visual inspection (film, printed matter, cloth, etc.), grain sorting machines, and banknote recognition systems in bank terminals.

[0004] As market demands for higher resolution, full-well capacity, and photosensitivity of linear CMOS image sensors increase, their size is increasing while pixel size and spacing are decreasing. However, reducing pixel size and spacing leads to a decrease in full-well capacity and photosensitivity, which is unacceptable in many applications. Although using multiple linear CMOS image sensors for image stitching can maintain full-well capacity and photosensitivity while meeting basic operational requirements, the increase in the number of linear CMOS image sensors inevitably leads to a linear increase in cost. Therefore, increasing the size of linear CMOS image sensors has gradually become the mainstream approach. Large-sized linear CMOS image sensors result in excessively long lateral dimensions, even exceeding the maximum size of photomasks in current lithography equipment. Due to the limitations of photomask size, the size of linear CMOS image sensors has gradually reached its limit. Therefore, how to manufacture large-sized linear CMOS image sensors has become a current challenge. Summary of the Invention

[0005] In order to overcome the shortcomings and deficiencies of the existing technology, the purpose of this invention is to provide a linear image sensor, a manufacturing method and a photolithography mask, so as to solve the problem of the difficulty in stitching large-size linear image sensors in the existing technology.

[0006] The objective of this invention is achieved through the following technical solution:

[0007] This invention provides a linear image sensor, comprising:

[0008] The first chip area and the second chip area are arranged sequentially in the first preset direction, and the circuit layout of the first chip area is the same as the circuit layout in the second chip area.

[0009] The linear image sensor further includes multiple pixels and conductive lines extending along the second preset direction. The pixels are provided in both the first chip area and the second chip area. The pixels in the first chip area and the second chip area are electrically connected to the conductive lines. The second preset direction has an angle with the first preset direction.

[0010] Furthermore, the first chip region and each of the second chip regions each include: a pixel array region and a plurality of control circuit regions, and the pixel array region and the plurality of control circuit regions are arranged along the second preset direction.

[0011] Furthermore, the pixel array includes a row of light-shielding pixel regions, which are disposed on one side of the pixel array and include at least one row of pixels.

[0012] Furthermore, each of the control circuit areas is located on the same side of the pixel array, and the light-shielding pixel area is located on the side of the pixel array away from the control circuit area.

[0013] Furthermore, the control circuit area includes a signal control circuit area and a readout quantization circuit area, which are arranged along the second preset direction.

[0014] Furthermore, the conductive circuit includes parallel signal control circuits and data transmission circuits, both of which are electrically connected to the pixel.

[0015] Furthermore, the data transmission lines corresponding to each pixel are located on the same side of the pixel; and / or, the signal control lines corresponding to each pixel are located on the same side of the pixel.

[0016] Furthermore, the pixels corresponding to the first chip area and the second chip area are aligned with each other in the second preset direction; and / or, the linear image sensor includes a control circuit module extending along the first preset direction, the control circuit module units corresponding to each chip area constitute the control circuit module, and the control circuit module units of the same type are located on the same layer; and / or, the second preset direction is perpendicular to the first preset direction.

[0017] Furthermore, the linear image sensor also includes a third chip area to an Nth chip area, where N is an integer greater than or equal to 3, and the first chip area to the Nth chip area are arranged along the first preset direction.

[0018] Furthermore, at least one of the third to Nth chip regions is fabricated based on a different mask than the first and second chip regions.

[0019] Furthermore, the first chip region and / or the Nth chip region includes a column of light-shielding pixels, which is disposed on one side of the pixel array and includes at least one column of pixels.

[0020] This application also provides a method for manufacturing a linear image sensor, suitable for manufacturing the linear image sensor as described above, comprising:

[0021] Provide semiconductor substrates;

[0022] A first mask is provided, and the semiconductor substrate is exposed for the first time using the first mask as a shield, wherein the area of ​​the first exposure corresponds to the first chip area;

[0023] The semiconductor substrate is moved relative to the first mask by a first preset distance in a first preset direction;

[0024] A second mask is provided, and the semiconductor substrate is exposed a second time based on the first preset distance and using the second mask as a shield. The area of ​​the second exposure corresponds to the second chip area.

[0025] The exposure of a chip region in the semiconductor substrate is completed based on the first exposure and the second exposure, wherein the chip region includes the first chip region and the second chip region.

[0026] Furthermore, the process after the second exposure also includes the following steps:

[0027] The material is continuously provided to the Nth mask, and the semiconductor substrate is continuously moved relative to the (N-1)th mask by the (N-1)th preset distance in the first preset direction; wherein, based on the (N-1)th preset distance, the semiconductor substrate is exposed for the Nth time with the Nth mask as a block, and the area of ​​the Nth exposure corresponds to the Nth region, where N is an integer greater than or equal to 3;

[0028] Exposure of a chip region in the semiconductor substrate is completed based on the first exposure to the Nth exposure, wherein the chip region includes the first chip region to the Nth region.

[0029] Furthermore, the first mask to the Nth mask are the same mask.

[0030] Furthermore, the first preset distance is less than or equal to the length of the first mask in the first preset direction.

[0031] Furthermore, the manufacturing method also includes:

[0032] The semiconductor substrate is moved at least once relative to the first mask by a predetermined interval distance in a second predetermined direction, and the steps of the first exposure and the second exposure are repeated to complete the exposure of at least another set of chip regions;

[0033] Repeat the above steps until all chip regions in the semiconductor substrate have been exposed.

[0034] Further, the semiconductor substrate includes: a semiconductor substrate and an etching mask layer formed on the semiconductor substrate, wherein:

[0035] The etching mask layer is exposed for the first time using the first mask as a block; the etching mask layer is exposed for the second time using the second mask as a block; and when the Nth mask exists, the etching mask layer is exposed for the Nth time using the Nth mask as a block, where N is an integer greater than or equal to 3.

[0036] Furthermore, after the exposure of all the chip regions on the semiconductor substrate is completed, the etch mask layer is developed.

[0037] Furthermore, each mask is provided with a first alignment mark pattern and a second alignment mark pattern that cooperates with the first alignment mark pattern at both ends of the first preset direction.

[0038] Furthermore, corresponding first alignment mark and second alignment mark are formed on the semiconductor substrate based on the first alignment mark pattern and the second alignment mark pattern.

[0039] Furthermore, the semiconductor substrate includes the etching mask layer. After the etching mask layer is subjected to line exposure and development, a first alignment mark corresponding to the first alignment mark pattern and a second alignment mark corresponding to the second alignment mark pattern are formed on the etching mask layer.

[0040] Furthermore, the first alignment mark pattern is block-shaped, the second alignment mark pattern is ring-shaped, and the outer edge size of the first alignment mark pattern is smaller than the inner edge size of the second alignment mark pattern; or, the first alignment mark pattern is ring-shaped, the second alignment mark pattern is block-shaped, and the outer edge size of the second alignment mark pattern is smaller than the inner edge size of the first alignment mark pattern.

[0041] Furthermore, the manufacturing method also includes:

[0042] Based on the measurements of the first comparison mark and the second alignment mark, the positions of the first exposure and the second exposure are detected.

[0043] Furthermore, each mask also includes a third alignment mark pattern and a fourth alignment mark pattern that cooperates with the third alignment mark pattern at both ends in the first preset direction, and there is a gap between the first line connecting the first alignment mark pattern and the second alignment mark pattern and the second line connecting the third alignment mark pattern and the fourth alignment mark pattern.

[0044] Furthermore, the first alignment mark pattern, the second alignment mark pattern, the third alignment mark pattern, and the fourth alignment mark pattern are disposed at the top corners of the corresponding photomask.

[0045] Further, the line connecting the first alignment mark pattern and the third alignment mark pattern is located outside the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern crosses the device pattern area; or, the line connecting the first alignment mark pattern and the third alignment mark pattern crosses the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern is located outside the device pattern area.

[0046] The present invention also provides a photomask suitable for the fabrication method of the linear image sensor as described above, wherein the photomask is at least one of the first to the Nth photomasks.

[0047] Furthermore, the photomask includes a device pattern area and an alignment pattern area, wherein when at least one of the first alignment mark pattern, the second alignment mark pattern, the third alignment mark pattern and the fourth alignment mark pattern is present, each pattern is located in the alignment pattern area.

[0048] Furthermore, the line connecting the first alignment mark pattern and the third alignment mark pattern is located outside the device pattern area, and the second alignment mark pattern and the fourth alignment mark pattern cross the device pattern area.

[0049] The beneficial effects of this invention are as follows: by dividing the linear image sensor into a first chip area and a second chip area with the same circuit layout in a first preset direction, and having the conductive lines connected to the pixels extend along a second preset direction, the number of lines arranged in the linear image sensor in the first preset direction is reduced, thereby reducing the difficulty of splicing the linear image sensor in the first preset direction. Attached Figure Description

[0050] Figure 1 This is one of the circuit layout diagrams of the linear image sensor in Embodiment 1 of the present invention;

[0051] Figure 2 This is the second schematic diagram of the circuit layout of the linear image sensor in Embodiment 1 of the present invention;

[0052] Figure 3 This is a schematic diagram of the structure of the linear image sensor in Embodiment 1 of the present invention;

[0053] Figures 4a-4d This is a cross-sectional structural schematic diagram of the method for manufacturing a linear image sensor according to Embodiment 1 of the present invention;

[0054] Figure 5 This is a schematic diagram of the planar structure of the mask in Embodiment 1 of the present invention;

[0055] Figures 6a-6c This is a schematic diagram of the planar structure of the method for manufacturing a linear image sensor in Embodiment 1 of the present invention;

[0056] Figure 7 yes Figure 6c Enlarged structural diagram at point A;

[0057] Figure 8 This is a schematic diagram of the planar structure of the mask in another embodiment of the present invention;

[0058] Figures 9a-9d This is a cross-sectional structural schematic diagram of the method for manufacturing a linear image sensor in Embodiment 2 of the present invention;

[0059] Figure 10 This is a schematic diagram of the planar structure of the semiconductor substrate in Embodiment 2 of the present invention;

[0060] Figure 11 yes Figure 10 Enlarged structural diagram at point B;

[0061] Figure 12 This is a schematic diagram of the planar structure of the linear image sensor in Embodiment 3 of the present invention;

[0062] Figure 13 This is a schematic diagram of the planar structure of the semiconductor substrate in Embodiment 3 of the present invention. Detailed Implementation

[0063] To further illustrate the technical means and effects adopted by the present invention to achieve the intended purpose, the following detailed description, in conjunction with the accompanying drawings and preferred embodiments, provides a detailed explanation of the specific implementation, structure, features, and effects of the linear image sensor, its fabrication method, and photolithographic mask proposed according to the present invention:

[0064] [Example 1]

[0065] Figure 1 This is one of the circuit layout diagrams of the linear image sensor in Embodiment 1 of the present invention. Figure 2 This is the second schematic diagram of the circuit layout of the linear image sensor in Embodiment 1 of the present invention. Figure 3 This is a schematic diagram of the structure of the linear image sensor in Embodiment 1 of the present invention.

[0066] like Figures 1 to 3 As shown, a linear image sensor 10 provided in Embodiment 1 of the present invention includes: a first chip region 10a and a second chip region 10b. The first chip region 10a and the second chip region 10b are arranged sequentially in a first preset direction, and the circuit arrangement in the first chip region 10a is the same as the circuit arrangement in the second chip region 10b, that is, the pixel arrangement and wire distribution in the first chip region 10a and the second chip region 10b are the same.

[0067] The linear image sensor 10 includes multiple pixels 11 and conductive lines extending along a second preset direction. Pixels 11 are provided in both the first chip region 10a and the second chip region 10b. The pixels 11 in the first chip region 10a and the second chip region 10b are electrically connected to the conductive lines. The second preset direction forms an angle with the first preset direction. In this embodiment, the second preset direction is perpendicular to the first preset direction; for example, the first preset direction is a left-right direction, and the second preset direction is a up-down direction. It should be noted that a pixel 11 can represent a photosensitive area unit, which can be composed of a photosensitive element (such as a photodiode PD) and a corresponding pixel circuit, or it can be composed of two or more photosensitive elements shared by a corresponding pixel circuit. In addition, the conductive lines include lines that lead out nodes that need to be electrically led out in the pixel, and can also include lines that need to apply control signals to the corresponding transistor in the pixel. Of course, it can also include conductive lines that need to be connected in existing image sensors. In one example, there are conductive lines arranged along the second preset direction to apply gate signals to the MOS transistor in the pixel.

[0068] In this embodiment, as Figure 1 and Figure 2As shown, the linear image sensor 10 is formed by splicing together a first chip region 10a and a second chip region 10b. Each chip region contains an m×n pixel array, repeatable circuits such as xdec (control signal generation circuit module) and ADC (analog-to-digital converter module), and the components and traces within each chip region are identical. Considering the size of the photomask and the difficulty of chip region splicing, in one example, m is generally selected as 2K or 4K. For the value of n, the mainstream linear image sensors on the market at this stage are generally 4 lines, 8 lines, and 16 lines. Among them, the xdec module is used to generate control signals for pixel array reset, exposure, and readout. In one example, the xdec module can be placed above the pixel array, which is beneficial for chip region splicing and can also avoid the digital control lines of the xdec module crossing the pixels laterally, reducing lateral line crosstalk and delay. The ADC is used to quantize pixel output signals, such as the reset signal Vrst signal and the image signal Vsig signal, to complete the A / D conversion. In one example, the ADC is less than or equal to the chip region width (pixel pitch) to reserve space for ADC control circuit and trace design.

[0069] In this embodiment, both the first chip region 10a and the second chip region 10b include a pixel array region and a plurality of control circuit regions, and the pixel array region and the plurality of control circuit regions are arranged along a second preset direction, that is, when the first preset direction is perpendicular to the second preset direction, the pixel array region and the plurality of control circuit regions are arranged in a vertical direction. The control circuit regions include an xdec module and an ADC, and may also include other necessary circuits from existing image sensors. The pixel array region contains a plurality of pixels 11 and conductive lines connecting the pixels 11 to the xdec module and the ADC.

[0070] like Figure 2As shown, the pixel array includes a light-shielding pixel area 14, which is located on one side of the pixel array and includes at least one row of pixels. If the linear image sensor 10 uses only one set of photomasks for translation and stitching, BLC (black level correction) columns cannot be achieved. Therefore, it must be changed to BLC rows. By masking the bottom row of pixels 11 of the pixel array, a row of gray-black pixels 11 becomes a BLC row. BLC rows can also be used to eliminate the influence of CIS dark current. In one example, the linear image sensor 10 quantizes all pixels 11 simultaneously. Therefore, a BLC row needs to occupy one readout circuit, and the linear image sensor 10 changes from supporting a maximum of n lines of readout to supporting a maximum of n-1 lines of readout. In another example, BLC columns are placed on both sides of the pixel array. This can be achieved by increasing the types of photomasks, i.e., adding photomasks with BLC columns. This allows two or three sets of masks to be stitched together to create a linear image sensor 10 with BLC columns. In a further example, the BLC column is set on both the leftmost and rightmost sides of the final assembled chip. Of course, it can also be set on either the leftmost or rightmost side, depending on the actual needs.

[0071] Furthermore, each control circuit area is located on the same side of the pixel array, and the light-shielding pixel area 14 is located on the side of the pixel array away from the control circuit area. In this embodiment, each control circuit area is located on the upper side of the pixel array, and the light-shielding pixel area 14 is located on the lower side of the pixel array.

[0072] In this embodiment, the control circuit area includes a signal control circuit area 121 and a readout quantization circuit area 122, which are arranged along a second preset direction. The signal control circuit area 121 includes an xdec module, and the readout quantization circuit area 122 includes multiple ADC modules. In a further example, the readout quantization circuit area 122 includes ADC modules that correspond one-to-one with each pixel 11.

[0073] In this embodiment, the conductive lines include a signal control line 131 and a data transmission line 132, both of which are electrically connected to the pixel 11. Specifically, the pixel 11 is connected to the xdec module in the signal control circuit area 121 via the signal control line 131, and the pixel 11 is connected to the ADC module in the readout quantization circuit area 122 via the data transmission line 132. In one example, the multiple signal control lines 131 corresponding to a column of pixels 11 are parallel to each other; the multiple data transmission lines 132 corresponding to a column of pixels 11 are also parallel to each other.

[0074] Furthermore, the data transmission line 132 corresponding to each pixel 11 is located on the same side of the pixel 11; and / or, the signal control line 131 corresponding to each pixel 11 is located on the same side of the pixel 11. See also Figure 1 and Figure 2 The arrangement of the signal control line 131 and the data transmission line 132 is such that they both extend along a second preset direction, thereby reducing the number of lines in the linear image sensor 10 in the first preset direction.

[0075] In this embodiment, the pixels 11 in the first chip area 10a and the second chip area 10b are aligned with each other in a second preset direction, that is, the first chip area 10a and the second chip area 10b are aligned with each other in the vertical direction.

[0076] Furthermore, the linear image sensor 10 includes a control circuit module extending along a first preset direction. The control circuit module is located within a control circuit area. The control circuit module units corresponding to each chip area (first chip area 10a, second chip area 10b) constitute the control circuit module, and control circuit module units of the same type are located on the same layer, thereby facilitating the fabrication of the linear image sensor 10. That is, in this embodiment, the control circuit areas of each chip area are aligned in the second preset direction.

[0077] Figures 4a-4d This is a cross-sectional structural schematic diagram of the method for manufacturing a linear image sensor according to Embodiment 1 of the present invention. Figure 5 This is a schematic diagram of the planar structure of the mask plate in Embodiment 1 of the present invention. Figures 6a-6c This is a schematic diagram of the planar structure of the method for manufacturing a linear image sensor in Embodiment 1 of the present invention. Figure 7 yes Figure 6c A magnified structural diagram at point A in the middle. (See diagram below.) Figures 4a-7 As shown, this embodiment provides a method for manufacturing a linear image sensor, including:

[0078] like Figure 4a As shown, a semiconductor substrate is provided. In one example, the semiconductor substrate includes a semiconductor substrate 100 and an etching mask layer 200 formed on the semiconductor substrate 100. Of course, in other embodiments, the semiconductor substrate can also be any substrate structure commonly used in the art, suitable for subsequent steps, and can be an intermediate structure stack in the device fabrication process.

[0079] In this embodiment, the etching mask layer 200 can be a photoresist, such as a negative photoresist. Of course, the photoresist can also be a positive photoresist. The semiconductor substrate 100 is a wafer. In other embodiments, the etching mask layer 200 can also be made of other materials used to block etching.

[0080] like Figure 4b , Figure 5as well as Figure 6a As shown, a first mask 300 is provided, and the semiconductor substrate is exposed for the first time using the first mask as a shield. The area of ​​the first exposure corresponds to the first region 110a. Figure 6a The first mask 300 has transparent and non-transparent areas, which together form the exposure pattern. The exposed pattern corresponds to the circuit pattern on the linear image sensor 10. Specifically, the first mask and a stepper lithography machine are used to perform the first exposure of the etched mask layer 200, such as... Figure 4b and Figure 6a As shown, after the first exposure, the etch mask layer 200 forms a pattern in the first region 110a that corresponds to a portion of the circuitry in the linear image sensor 10. It is understood that this pattern can only be revealed after the etch mask layer 200 has been developed. Figure 4b This is not a schematic representation of the specific pattern of the mask; the actual pattern can be arranged according to the actual circuit design.

[0081] like Figure 4c and Figure 6b As shown, the semiconductor substrate is moved a first preset distance relative to the first mask 300 in a first preset direction. The first preset direction is the same as the direction in which the linear image sensor 10 needs to be stitched. Specifically, in one example, after the first exposure is completed, the semiconductor substrate is carried by the stage and stepped a first preset distance to the position of the next exposure field.

[0082] Furthermore, a second mask 300 is provided. After moving a first preset distance, the semiconductor substrate is exposed a second time using the second mask as a shield. The area exposed in the second exposure corresponds to the second region 110b. Figure 4c and Figure 6b As is understandable, in the illustrated example, the second mask is fabricated using the same mask as the first mask. To clearly illustrate the concept of this example, both are indicated by the number 300, signifying that the same mask was used.

[0083] Specifically, the etched mask layer 200 is subjected to a second exposure using a second mask and a stepper lithography machine. After the second exposure, the etched mask layer 200 forms a pattern in the second region 110b corresponding to a portion of the circuitry in the linear image sensor 10. It is understood that the size of the exposed area is the same as, or slightly smaller than, the size of the corresponding mask, thereby ensuring that other areas of the etched mask layer 200 are not exposed and become ineffective.

[0084] The exposure of a chip region 110 in a semiconductor substrate is completed based on a first exposure and a second exposure. The chip region 110 includes a first region 110a and a second region 110b. In this embodiment, the chip region 110 is formed by stitching together two exposures; that is, the pattern of a linear image sensor 10 is formed by only one photolithographic stitching. Each chip region 110 corresponds to one linear image sensor 10. In one example, such as... Figure 6b As shown, each region in the chip (such as the first region 110a and the second region 110b) corresponds to three vertically arranged device distribution blocks, that is, after two exposures are stitched together, three vertically arranged device distribution blocks are formed. Of course, in other embodiments, a chip region 110 can also be formed by stitching together more than two exposures, that is, a chip region 110 may include not only the first region 110a and the second region 110b, but also a third region, a fourth region, and more regions, which can be referred to. Figure 12 and Figure 13 .

[0085] like Figure 3 As shown, in this embodiment, the linear image sensor 10 includes a first chip region 10a and a second chip region 10b, which are arranged sequentially in a first preset direction. The first chip region 10a corresponds to a first region 110a, and the second chip region 10b corresponds to a second region 110b. Of course, depending on the length of the linear image sensor 10, it can be divided into more chip regions for formation through more exposures, thus ensuring that the size of the linear image sensor 10 is not limited by the size of the photomask.

[0086] like Figure 6c As shown, the semiconductor substrate is moved at least once relative to the corresponding mask in a second predetermined direction by a predetermined interval distance, and the steps of the first exposure and the second exposure are repeated at least once to complete the exposure of at least one other chip region 110; the above steps are repeated until all chip regions 110 on the semiconductor substrate are exposed. It is understood that each semiconductor substrate is designed with multiple chip regions 110 (…). Figure 6cThe wafer has six chip regions 110. Each chip region 110 is formed through a first exposure and a second exposure. After one chip region 110 is exposed, the mask 300 is moved to the next chip region 110 to be exposed, and the first and second exposure steps are repeated for the next chip region 110, and so on, until all chip regions 110 on the semiconductor substrate are exposed. The second preset direction is set according to the position of the chip regions 110 designed on the wafer. For example, it can be the direction of moving chip region ① to chip region ②, as shown by arrow m in the figure; it can also be the direction of moving chip region ② to chip region ③, as shown by arrow n in the figure; or it can be the direction of moving chip region ② to chip region ④, as shown by arrow y in the figure. In this example, chip regions ①, ②, ③, and ④ are numbered sequentially from top to bottom and from left to right. The direction of arrow m forms a certain angle with the first preset direction, the direction of arrow n is consistent with the first preset direction, and the direction of arrow y is perpendicular to the first preset direction. In one example, the semiconductor substrate is moved relative to the corresponding mask in a second preset direction by a preset interval distance to serve as a cleavage path between adjacent chip regions.

[0087] like Figure 4d As shown, after exposure of all chip regions 110 on the semiconductor substrate is completed, the etching mask layer 200 is developed. In this embodiment, the etching mask layer 200 uses negative photoresist, so after development, the negative photoresist in the illuminated areas is retained, while the negative photoresist in the unilluminated areas is removed. After forming the patterned etching mask layer 200, the semiconductor substrate 100 is further processed, such as dry etching, wet etching, oxidation, etc.

[0088] In this embodiment, the first and second masks are the same mask, meaning the patterns for the two exposures are identical. Therefore, during each exposure, it is not necessary to replace the mask 300 with a different pattern; only the semiconductor substrate needs to be shifted to the next exposure area. In a further example, the circuit layout of the linear image sensor 10 can be designed so that the circuit patterns of the first chip region 10a and the second chip region 10b are identical. Of course, in other embodiments, the first and second masks can also be different masks, meaning the patterns on the first and second masks are not the same.

[0089] Preferably, the first preset distance is less than or equal to the length of the first mask in the first preset direction, ensuring that the edges of the first region 110a and the second region 110b are aligned or partially overlap, thereby improving the stitching effect between the pattern of the next exposure and the pattern of the previous exposure. This is beneficial for linear image sensors 10 where the circuit between the first chip region 10a and the second chip region 10b requires conductive connection. Of course, in other embodiments, when the circuit between the first chip region 10a and the second chip region 10b does not require conductive connection, the first preset distance can be greater than the length of the first mask in the first preset direction, but the spacing between the first region 110a and the second region 110b needs to be controlled to ensure that the spacing between two adjacent pixels in the first preset direction is the same.

[0090] In this embodiment, each mask is provided with a first alignment mark pattern 310 and a second alignment mark pattern 320 that cooperates with the first alignment mark pattern 310 at both ends in the first preset direction, such as Figure 5 As shown, the first alignment mark pattern 310 and the second alignment mark pattern 320 are, for example, OVL boxes. When the semiconductor substrate is exposed using a mask as a shield, a first alignment mark 210 corresponding to the first alignment mark pattern 310 and a second alignment mark 220 corresponding to the second alignment mark pattern 320 are formed on the semiconductor substrate. Specifically, the first alignment mark 210 corresponding to the first alignment mark pattern 310 and the second alignment mark 220 corresponding to the second alignment mark pattern 320 are formed on the etching mask layer 200 of the semiconductor substrate. The first alignment mark 210 and the second alignment mark 220 are used as a reference for subsequent detection of the exposure position. That is, by detecting the positional relationship between the first alignment mark 210 and the second alignment mark 220, the exposure position can be determined, thereby achieving ideal stitching based on the mutually cooperating alignment marks.

[0091] Furthermore, the fabrication method also includes detecting the positions of the first exposure and the second exposure based on measurements of the first alignment mark 210 and the second alignment mark 220. Specifically, when the etch mask layer 200 is exposed, the first alignment mark 210 and the second alignment mark 220 are formed in both the first region 110a and the second region 110b. After exposure, the etch mask layer 200 is developed to reveal all the first alignment marks 210 and the second alignment marks 220. Then, the developed semiconductor substrate is transferred to an OVL metrology instrument for measurement. In an optional example, if the splicing is successful, subsequent process steps can be performed directly. If the measurement shows that the splicing is unsuccessful, the photolithography mask layer (such as a photoresist layer) can be removed, and the exposure can be repeated. After successful splicing is detected, subsequent etching steps can be performed, thus avoiding unnecessary steps and enabling splicing detection based on the photoresist layer. Of course, in other examples, alignment marks can also be made at the positions corresponding to the dicing paths, and detection can be performed based on the alignment marks at those positions. Marks located on the dicing paths do not affect the fabrication of the device.

[0092] In one example, after exposure of all chip regions on the semiconductor substrate is completed, the etch mask layer is developed. That is, after the entire wafer has been exposed, the wafer is developed, and then transferred to an OVL metrology system for measurement. In a further example, the measurement of alignment marks, as described in other prior art, can also be performed simultaneously.

[0093] Preferably, the semiconductor substrate moves a first preset distance relative to the second mask 300 in a first preset direction, equal to the distance between the center points of the first alignment mark pattern 310 and the second alignment mark pattern 320 on the mask 300. Thus, after two exposures, the center points of the second alignment mark 220 in the first region 110a and the first alignment mark 210 in the second region 110b are aligned, facilitating measurement. If the measurement positions of the first and second exposures are the same as the preset exposure positions, it indicates that the stitching of the two exposures is successful.

[0094] In this embodiment, the first alignment mark pattern 310 is block-shaped, and the second alignment mark pattern 320 is ring-shaped. The outer edge dimension of the first alignment mark pattern 310 is smaller than the outer edge dimension of the second alignment mark pattern 320. Of course, in other embodiments, the first alignment mark pattern 310 can also be ring-shaped, and the second alignment mark pattern 320 can be block-shaped, with the outer edge dimension of the second alignment mark pattern 320 smaller than the inner edge dimension of the first alignment mark pattern 310. By setting one of the first alignment mark pattern 310 and the second alignment mark pattern 320 to be block-shaped and the other to be ring-shaped, it is easier to detect whether the exposure stitching is successful. Whether the first alignment mark pattern 310 or the second alignment mark pattern 320 is ring-shaped depends on the polarity of the photoresist used. Of course, in other embodiments, the first alignment mark pattern 310 and the second alignment mark pattern 320 can also be other patterns, as long as the actual exposure position can be detected subsequently.

[0095] like Figure 5 and Figure 7 As shown, the first alignment mark pattern 310 is block-shaped, and the second alignment mark pattern 320 is ring-shaped. If Figure 5 In the diagram, a1 is equal to half the width difference between the first alignment mark pattern 310 and the second alignment mark pattern 320, and b1 is equal to half the length difference between the first alignment mark pattern 310 and the second alignment mark pattern 320. Therefore, the stitching of the two exposures is successful. Of course, a standard for successful stitching can be established based on the design of the alignment marks. In the diagram, c represents the gap between the two alignment marks between the two chip regions 110.

[0096] Furthermore, such as Figure 5 As shown, each photomask (such as the first photomask 300) further includes a third alignment mark pattern 330 and a fourth alignment mark pattern 340 that cooperates with the third alignment mark pattern 330 at both ends in a first preset direction. A gap exists between the first line connecting the first alignment mark pattern 310 and the second alignment mark pattern 320 and the second line connecting the third alignment mark pattern 330 and the fourth alignment mark pattern 340. For example, the first alignment mark pattern 310 and the second alignment mark pattern 320 are located at the upper edge of the photomask 300, and the third alignment mark pattern 330 and the fourth alignment mark pattern 340 are located at the lower edge. Preferably, the first alignment mark pattern 310 and the third alignment mark pattern 330 have the same pattern, only their positions on the photomask 300 are different; the second alignment mark pattern 320 and the fourth alignment mark pattern 340 have the same pattern, only their positions on the photomask 300 are different. By providing alignment mark patterns at both the upper and lower edges of the photomask 300, subsequent detection of the actual exposure position is facilitated. Of course, other patterns and locations can be designed in other examples.

[0097] Furthermore, the first alignment mark pattern 310, the second alignment mark pattern 320, the third alignment mark pattern 330, and the fourth alignment mark pattern 340 are disposed at the top corners of the corresponding mask 300, such as corresponding to the chip dicing area. When the wafer is diced, the alignment marks on the semiconductor substrate 100 can be cut off, so that there are no alignment marks on the edge of the linear image sensor 10.

[0098] [Example 2]

[0099] Figures 9a-9d This is a cross-sectional structural schematic diagram of the method for manufacturing a linear image sensor in Embodiment 2 of the present invention. Figure 10 This is a schematic diagram of the planar structure of the semiconductor substrate in Embodiment 2 of the present invention. Figure 11 yes Figure 10 A magnified structural diagram at point B. (See diagram below.) Figures 9a-11 As shown, the method for manufacturing a linear image sensor provided in Embodiment 2 of the present invention is the same as that in Embodiment 1. Figures 3 to 7 The fabrication method of the linear image sensor in this embodiment is basically the same, except that:

[0100] like Figure 9a As shown, a semiconductor substrate is provided. The semiconductor substrate includes a semiconductor substrate 100 and an etching mask layer 200 formed on the semiconductor substrate 100. In this embodiment, the etching mask layer 200 uses a positive photoresist.

[0101] like Figure 9b As shown, a first photomask 300 is provided. The semiconductor substrate is exposed for the first time using the first photomask as a shield. The area exposed for the first time corresponds to the first region 110a. In this embodiment, since the etching mask layer 200 uses positive photoresist, the first alignment mark pattern 310 is annular, and the second alignment mark pattern 320 is block-shaped. The outer edge size of the second alignment mark pattern 320 is smaller than the inner edge size of the first alignment mark pattern 310.

[0102] like Figure 9c As shown, the semiconductor substrate is moved a first preset distance relative to the first mask 300 in a first preset direction. The first preset direction is the same as the direction in which the linear image sensor 10 needs to be stitched. Specifically, after the first exposure is completed, the semiconductor substrate is carried by the stage and moved a first preset distance to the position of the next exposure field.

[0103] Furthermore, a second mask is provided. After moving a first preset distance, the semiconductor substrate is exposed a second time using the second mask as a shield. The area exposed in the second exposure corresponds to the second region 110b. Specifically, the etching mask layer 200 is exposed a second time using the second mask and a stepper lithography machine. After the second exposure, the etching mask layer 200 forms a pattern in the second region 110b that corresponds to a portion of the circuitry in the linear image sensor 10. It is understood that the size of the exposed area is the same as the size of the corresponding mask, or it may be slightly smaller than the size of the corresponding mask, thereby ensuring that other areas of the etching mask layer 200 are not exposed and fail.

[0104] The exposure of a chip region 110 in a semiconductor substrate is completed by the first exposure and the second exposure. The chip region 110 includes a first region 110a and a second region 110b.

[0105] like Figure 10 As shown, the semiconductor substrate is moved at least once relative to the mask in a second preset direction by a preset interval distance, and the steps of the first exposure and the second exposure are repeated to complete the exposure of at least one other chip region 110; the above steps are repeated until all chip regions 110 on the semiconductor substrate are exposed. Figure 8 The semiconductor substrate has six chip regions 110, meaning that the first and second exposures need to be repeated six times to complete the exposure of all chip regions 110 on the semiconductor substrate.

[0106] like Figure 9d As shown, after exposure of all chip regions 110 on the semiconductor substrate is completed, the etching mask layer 200 is developed. In this embodiment, the etching mask layer 200 uses positive photoresist, so after development, the positive photoresist in the illuminated areas is removed, while the positive photoresist in the unilluminated areas is retained. After forming the patterned etching mask layer 200, the semiconductor substrate 100 is further processed, such as dry etching, wet etching, oxidation, etc.

[0107] like Figure 11 As shown, the first alignment mark pattern 310 is circular, and the second alignment mark pattern 320 is block-shaped. If Figure 11 In the diagram, a1 is equal to half the width difference between the inner edge of the first alignment mark pattern 310 and the outer edge of the second alignment mark pattern 320, and b1 is equal to half the length difference between the inner edge of the first alignment mark pattern 310 and the outer edge of the second alignment mark pattern 320. Therefore, the stitching of the two exposures is successful. In the diagram, c represents the gap between the two alignment marks between the two chip regions 110.

[0108] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1, and will not be repeated here.

[0109] [Example 3]

[0110] Figure 12 This is a schematic diagram of the planar structure of the linear image sensor in Embodiment 3 of the present invention. Figure 13 This is a schematic diagram of the planar structure of the semiconductor substrate in Embodiment 3 of the present invention. Figure 12 and Figure 13 As shown, the linear image sensor 10 and its manufacturing method provided in Embodiment 3 of the present invention are the same as those in Embodiment 1. Figures 1 to 7 ) and Example 2 ( Figures 9a to 11 The linear image sensor 10 and its manufacturing method are basically the same as those in the previous embodiment, except that in this embodiment:

[0111] The linear image sensor 10 also includes a third chip region 10c to an Nth chip region, where N is an integer greater than or equal to 3. The first chip regions 10a to the Nth chip regions are arranged along a first preset direction. In this embodiment, N equals 4, that is, the mask 300 includes a first mask, a second mask, a third mask, and a fourth mask, and a chip region 110 includes a first region 110a, a second region 110b, a third region 110c, and a fourth region 110d. After the first mask, the second mask, the third mask, and the fourth mask are exposed sequentially, the first region 110a, the second region 110b, the third region 110c, and the fourth region 110d are formed respectively. Figure 12 As shown.

[0112] Furthermore, at least one of the third chip regions 10c to the Nth chip region is fabricated using a different mask than the first chip region 10a and the second chip region 10b. This allows them to be used to achieve different functions. In this embodiment, all chip regions are fabricated using the same mask.

[0113] Furthermore, the first chip region 10a and / or the Nth chip region include a column of light-shielding pixels (not shown), which is disposed on one side of the pixel array and includes at least one column of pixels.

[0114] like Figure 12 and Figure 13 As shown, this embodiment also provides a method for manufacturing a linear image sensor, including:

[0115] A semiconductor substrate is provided. Specifically, the semiconductor substrate includes a semiconductor substrate 100 and an etching mask layer 200 formed on the semiconductor substrate 100.

[0116] A first mask 300 is provided, and the semiconductor substrate is exposed for the first time using the first mask as a shield. The area of ​​the first exposure corresponds to the first region 110a.

[0117] The semiconductor substrate is moved a first preset distance relative to the first mask in a first preset direction.

[0118] A second mask is provided. After moving a first preset distance, the semiconductor substrate is exposed a second time using the second mask as a shield. The area exposed a second time corresponds to the second region 110b.

[0119] The second exposure also includes the step of moving the semiconductor substrate relative to the second mask by a second preset distance in a first preset direction;

[0120] The Nth mask is continuously provided, that is, N masks are included, and the semiconductor substrate is moved relative to the (N-1)th mask by the (N-1)th preset distance in the first preset direction. Based on the continuous movement of the (N-1)th preset distance, the etching mask layer 200 of the semiconductor substrate is exposed for the Nth time with the Nth mask as a shield. The area exposed for the Nth time corresponds to the Nth region, where N is an integer greater than or equal to 3.

[0121] The exposure of a chip region 110 in a semiconductor substrate is completed based on the first exposure to the Nth exposure. The chip region 110 includes a first region 110a to the Nth region.

[0122] In this embodiment, N equals 4, meaning it includes a first mask, a second mask, a third mask, and a fourth mask. A chip region 110 includes a first region 110a, a second region 110b, a third region 110c, and a fourth region 110d. The first, second, third, and fourth masks are exposed sequentially to form the first region 110a, the second region 110b, the third region 110c, and the fourth region 110d, respectively. Figure 12 As shown.

[0123] like Figure 12 The linear image sensor 10 manufactured in this embodiment includes a first chip region 10a, a second chip region 10b, a third chip region 10c, and a fourth chip region 10d, which are arranged sequentially in a first preset direction. Specifically, the first chip region 10a corresponds to a first region 110a, the second chip region 10b corresponds to a second region 110b, the third chip region 10c corresponds to a third region 110c, and the fourth chip region 10d corresponds to a fourth region 110d.

[0124] Furthermore, the first to Nth masks are all the same mask. In this embodiment, the first, second, third, and fourth masks are all the same mask, and the patterns on the first, second, third, and fourth masks are identical.

[0125] Preferably, the semiconductor substrate moves the same distance from the first preset distance to the (N-1)th preset distance in the first preset direction, and each distance is less than or equal to the length of the mask in the first preset direction. This ensures that the edges of adjacent regions in a chip region 110 are aligned or partially overlapped, so that the pattern of the next exposure is stitched together with the pattern of the previous exposure.

[0126] Those skilled in the art should understand that the remaining structures and working principles of this embodiment are the same as those of Embodiment 1 or 2, and will not be repeated here.

[0127] like Figure 5 and Figure 8 As shown, this application also provides a photolithographic mask (hereinafter referred to as a mask), which is suitable for the fabrication method of the linear image sensor as described above, wherein the photolithographic mask is at least one of the first to the Nth mask. Figure 5 This is a schematic diagram of the planar structure of the mask plate in Embodiment 1 of the present invention. Figure 8 This is a schematic diagram of the planar structure of the mask in another embodiment of the present invention.

[0128] Furthermore, the photomask includes a device pattern area and an alignment pattern area. The device pattern area corresponds to the circuit pattern on the linear image sensor 10, and the alignment pattern area is used to set alignment mark patterns. In one example, the device pattern area is as follows: Figure 5 and Figure 8 As shown in the elliptical dashed box in the image, align the pattern area as follows: Figure 5 and Figure 8 The square dashed box in the diagram shows that when at least one of the first alignment mark pattern 310, the second alignment mark pattern 320, the third alignment mark pattern 330, and the fourth alignment mark pattern 340 is present, each alignment mark pattern is located in the alignment pattern area. Preferably, the alignment pattern area is located on the upper and lower sides of the device pattern area, thereby facilitating the horizontal parallelism of the photomask for splicing the circuit patterns on the linear image sensor 10.

[0129] Furthermore, such as Figure 8As shown, the line connecting the first alignment mark pattern 310 and the third alignment mark pattern 330 is located outside the device pattern area, and the line connecting the second alignment mark pattern 320 and the fourth alignment mark pattern 340 crosses the device pattern area. Furthermore, the rightmost outer edge of the second alignment mark pattern 320 and the fourth alignment mark pattern 340 is aligned with the rightmost outer edge of the device pattern area. This facilitates aligning the right side of the device pattern area with the right edge of the photomask. Alternatively, in other embodiments, the line connecting the first alignment mark pattern 310 and the third alignment mark pattern 330 may cross the device pattern area, and the line connecting the second alignment mark pattern 320 and the fourth alignment mark pattern 340 may be located outside the device pattern area. Furthermore, the leftmost outer edge of the first alignment mark pattern 310 and the third alignment mark pattern 330 may be aligned with the rightmost outer edge of the device pattern area.

[0130] In this document, the directional terms such as up, down, left, right, front, and back are defined according to the position of the structures in the accompanying drawings and the relative positions of the structures, and are only used for clarity and convenience in expressing the technical solution. It should be understood that the use of these directional terms should not limit the scope of protection claimed in this application. It should also be understood that the terms "first" and "second," etc., used herein are only used for distinction in name and are not used to limit the number or order.

[0131] The above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention in any way. Although the present invention has been disclosed above with reference to preferred embodiments, it is not intended to limit the present invention. Any person skilled in the art can make some modifications or alterations to the above-disclosed technical content without departing from the scope of the technical solution of the present invention, which are equivalent embodiments with equivalent changes. Any simple modifications, equivalent changes and alterations made to the above embodiments based on the technical essence of the present invention without departing from the scope of the technical solution of the present invention shall still fall within the protection scope of the technical solution of the present invention.

Claims

1. A linear image sensor, characterized in that, include: A first chip area and a second chip area are arranged sequentially in a first preset direction, and the circuit layout of the first chip area is the same as the circuit layout in the second chip area. The linear image sensor further includes multiple pixels and conductive lines extending along a second preset direction. The pixels are provided in both the first chip area and the second chip area. The pixels in the first chip area and the second chip area are electrically connected to the conductive lines. The second preset direction has an angle with the first preset direction. The conductive line includes a signal control line and a data transmission line. Both the data transmission line and the signal control line are electrically connected to the pixel. Both the signal control line and the data transmission line extend along the second preset direction. Both the first chip area and the second chip area include: a pixel array area and a plurality of control circuit areas, and the pixel array area and the plurality of control circuit areas are arranged along the second preset direction. The control circuit area includes a signal control circuit area and a readout quantization circuit area, and the signal control circuit area and the readout quantization circuit area are arranged along the second preset direction. The signal control circuit area includes a control signal generation circuit module, and the readout quantization circuit area includes multiple analog-to-digital conversion modules. The pixel is connected to the control signal generation circuit module in the signal control circuit area through the signal control line, and the pixel is connected to the analog-to-digital conversion module in the readout quantization circuit area through the data transmission line. The devices and traces in the first chip area and the second chip area are exactly the same.

2. The linear image sensor according to claim 1, characterized in that, The pixel array region includes a row of light-blocking pixel regions, which are located on one side of the pixel array region and include at least one row of pixels.

3. The linear image sensor according to claim 2, characterized in that, Each of the control circuit areas is located on the same side of the pixel array area, and the light-shielding pixel area is located on the side of the pixel array area away from the control circuit area.

4. The linear image sensor according to claim 1, characterized in that, The data transmission lines corresponding to each pixel are located on the same side of the pixel; and / or, the signal control lines corresponding to each pixel are located on the same side of the pixel.

5. The linear image sensor according to claim 1, characterized in that, The pixels in the first chip area and the second chip area are aligned with each other in the second preset direction; and / or, the linear image sensor includes a control circuit module extending along the first preset direction, the control circuit module units corresponding to each chip area constitute the control circuit module, and the control circuit module units of the same type are located in the same layer; and / or, the second preset direction is perpendicular to the first preset direction.

6. The linear image sensor according to any one of claims 1-5, characterized in that, The linear image sensor further includes a third chip area to an Nth chip area, where N is an integer greater than or equal to 3, and the first chip area to the Nth chip area are arranged along the first preset direction.

7. The linear image sensor according to claim 6, characterized in that, At least one of the third to Nth chip regions is fabricated based on a different mask than the first and second chip regions.

8. The linear image sensor according to claim 7, characterized in that, The first chip region and / or the Nth chip region includes a column of light-shielding pixel regions, which are disposed on one side of the pixel array region and include at least one column of pixels.

9. A method for manufacturing a linear image sensor, suitable for manufacturing the linear image sensor as described in any one of claims 1-8, characterized in that, include: Provide semiconductor substrates; A first mask is provided, and the semiconductor substrate is exposed for the first time using the first mask as a shield. The area of ​​the first exposure corresponds to the first chip area. The semiconductor substrate is moved relative to the first mask by a first preset distance in a first preset direction; A second mask is provided, and the semiconductor substrate is exposed a second time based on the first preset distance and using the second mask as a shield. The area of ​​the second exposure corresponds to the second chip area. The exposure of a chip region in the semiconductor substrate is completed based on the first exposure and the second exposure, wherein the chip region includes the first chip region and the second chip region.

10. The method for manufacturing a linear image sensor according to claim 9, characterized in that, The second exposure is followed by the following steps: The semiconductor substrate is continuously moved relative to the (N-1)th mask in the first preset direction by a preset distance of (N-1)th distance; wherein, based on the (N-1)th preset distance, the semiconductor substrate is exposed for the Nth time using the Nth mask as a shield, and the area exposed for the Nth time corresponds to the Nth region, where N is an integer greater than or equal to 3; Exposure of a chip region in the semiconductor substrate is completed based on the first exposure to the Nth exposure, wherein the chip region includes the first chip region to the Nth region.

11. The method for manufacturing a linear image sensor according to claim 10, characterized in that, The first mask to the Nth mask are the same mask.

12. The method for manufacturing a linear image sensor according to claim 9, characterized in that, The first preset distance is less than or equal to the length of the first mask in the first preset direction.

13. The method for manufacturing a linear image sensor according to claim 9, characterized in that, The manufacturing method further includes: The semiconductor substrate is moved at least once relative to the first mask by a predetermined interval distance in a second predetermined direction, and the steps of the first exposure and the second exposure are repeated to complete the exposure of at least another set of chip regions; Repeat the above steps until all chip regions in the semiconductor substrate have been exposed.

14. The method for manufacturing a linear image sensor according to claim 9, characterized in that, The semiconductor substrate includes: a semiconductor substrate and an etching mask layer formed on the semiconductor substrate, wherein: The etching mask layer is exposed for the first time using the first mask as a block; the etching mask layer is exposed for the second time using the second mask as a block; and when there is an Nth mask, the etching mask layer is exposed for the Nth time using the Nth mask as a block, where N is an integer greater than or equal to 3.

15. The method for manufacturing a linear image sensor according to claim 14, characterized in that, After exposure of all chip regions on the semiconductor substrate is completed, the etched mask layer is developed.

16. The method for manufacturing a linear image sensor according to any one of claims 9-14, characterized in that, Each mask has a first alignment mark pattern and a second alignment mark pattern that cooperates with the first alignment mark pattern at both ends of the first preset direction.

17. The method for manufacturing a linear image sensor according to claim 16, characterized in that, Based on the first alignment mark pattern and the second alignment mark pattern, corresponding first alignment mark and second alignment mark are formed on the semiconductor substrate.

18. The method for manufacturing a linear image sensor according to claim 17, characterized in that, The semiconductor substrate includes an etching mask layer. After the etching mask layer is exposed and developed, a first alignment mark corresponding to the first alignment mark pattern and a second alignment mark corresponding to the second alignment mark pattern are formed on the etching mask layer.

19. The method for manufacturing a linear image sensor according to claim 18, characterized in that, The first alignment mark pattern is block-shaped, and the second alignment mark pattern is ring-shaped, with the outer edge dimension of the first alignment mark pattern being smaller than the inner edge dimension of the second alignment mark pattern; or, the first alignment mark pattern is ring-shaped, and the second alignment mark pattern is block-shaped, with the outer edge dimension of the second alignment mark pattern being smaller than the inner edge dimension of the first alignment mark pattern.

20. The method for manufacturing a linear image sensor according to claim 17, characterized in that, The manufacturing method further includes: Based on the measurements of the first comparison mark and the second alignment mark, the positions of the first exposure and the second exposure are detected.

21. The method for manufacturing a linear image sensor according to claim 17, characterized in that, Each mask also includes a third alignment mark pattern and a fourth alignment mark pattern that cooperates with the third alignment mark pattern at both ends in the first preset direction, and the first line connecting the first alignment mark pattern and the second alignment mark pattern is parallel to each other and has a gap with the second line connecting the third alignment mark pattern and the fourth alignment mark pattern.

22. The method for manufacturing a linear image sensor according to claim 21, characterized in that, The first alignment mark pattern, the second alignment mark pattern, the third alignment mark pattern, and the fourth alignment mark pattern are located at the top corners of the corresponding photomask.

23. The method for manufacturing a linear image sensor according to claim 21, characterized in that, The line connecting the first alignment mark pattern and the third alignment mark pattern is located outside the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern crosses the device pattern area; or, the line connecting the first alignment mark pattern and the third alignment mark pattern crosses the device pattern area, and the line connecting the second alignment mark pattern and the fourth alignment mark pattern is located outside the device pattern area.

24. A photomask, suitable for fabrication of a linear image sensor as described in any one of claims 9-23, characterized in that, The photomask is at least one of the first to the Nth photomasks.

25. The photomask according to claim 24, characterized in that, The photomask includes a device pattern area and an alignment pattern area, wherein when at least one of a first alignment mark pattern, a second alignment mark pattern, a third alignment mark pattern and a fourth alignment mark pattern is present, each pattern is located in the alignment pattern area.

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