Power module with low parasitic inductance, high power density and double-sided heat dissipation and preparation method thereof

Abstract

The present invention provides a power module with low parasitic inductance and high power density and double-sided heat dissipation, and a preparation method thereof. An overlapping layout design is adopted to set the positions of the power copper surface and the power terminal, so that the power copper surfaces and the power terminals of the DC+ node and the DC- node are arranged alternately, thereby enhancing the mutual inductance cancellation effect of the power commutation circuit. Secondly, a copper block connector is used to connect the power circuits of the same node, thereby reducing the self-inductance of the commutation circuit. The optimized design of the present invention reduces the mutual inductance of each power circuit between different DBC linings and between the same lining, and reduces the self-inductance within the same power circuit. Therefore, the present invention can effectively reduce the voltage shock and current oscillation of the chip during the switching process.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor power modules, and in particular relates to a power module with low parasitic inductance, high power density and double-sided heat dissipation and a preparation method thereof. Background Art

[0002] Power modules are widely used in power electronics applications such as electric vehicles and traction locomotives. However, traditional silicon-based power modules are gradually unable to meet the requirements of high temperature and high power density for high-power applications. In contrast, silicon carbide (SiC) power modules are attracting more and more attention with their excellent high-frequency, high-voltage and high-temperature performance, especially in the field of electric vehicles.

[0003] However, most current silicon carbide power modules still use the packaging technology of traditional silicon-based modules, and therefore fail to give full play to the excellent characteristics of silicon carbide power devices. Among them, the parasitic inductance problem is a key challenge for silicon carbide module packaging. Parasitic inductance may not only cause power device turn-off voltage spikes and electromagnetic compatibility issues, but also increase the switching loss of the power module, reduce its reliability, and even cause module failure. In order to give full play to the advantages of silicon carbide power devices, it is urgent to develop packaging integration technology with low parasitic inductance and high power density to better adapt to the performance and application requirements of silicon carbide power devices. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a power module with low parasitic inductance and high power density and double-sided heat dissipation and a preparation method thereof. The technical problem to be solved by the present invention is achieved by the following technical solutions:

[0005] In a first aspect, the present invention provides a power module with low parasitic inductance and high power density and double-sided heat dissipation, comprising:

[0006] An upper DBC liner and a lower DBC liner, wherein the lower DBC liner is arranged in parallel with the upper DBC liner and is electrically connected to a corresponding port of the upper DBC liner;

[0007] Four chips, power terminals, copper block connectors, gate copper surfaces, Kelvin source copper surfaces, output terminals and bonding wires are arranged on the upper DBC substrate and the lower DBC substrate;

[0008] Among them, the power terminal is arranged on the same side of the upper DBC liner and the lower DBC liner, the power terminals of the upper DBC liner and the lower DBC liner both include DC+ power terminals and DC- power terminals, and the DC+ power terminals and the DC- power terminals are arranged alternately with each other; the upper DBC liner and the lower DBC liner are connected through the copper block connector; the output terminal is arranged on the side away from the power terminal; the gate copper surface and the Kelvin source copper surface are adjacently arranged inside the upper DBC liner and the lower DBC liner; the chip is connected to the gate copper surface and the Kelvin source copper surface through the bonding wires.

[0009] In a second aspect, the present invention provides a method for preparing a power module with low parasitic inductance and high power density and double-sided heat dissipation, comprising:

[0010] The first step is to select the upper DBC liner and the lower DBC liner, and apply solder paste on the surface of the prepared upper DBC liner and the lower DBC liner through the steel mesh;

[0011] In the second step, the chips are placed on the designated positions of the upper DBC liner and the lower DBC liner by a chip mounter, and then placed in a vacuum welding furnace for vacuum welding using a graphite fixture;

[0012] The third step is to use ultrasonic cleaning equipment to clean the surface of the chip and liner completed in the second step to remove the residual solder paste;

[0013] The fourth step is to connect the chip source, gate copper surface and Kelvin source copper surface through a bonding machine;

[0014] Step 5: Apply solder paste on the copper block connector surface, the power copper surface surface and the ceramic substrate surface through the steel mesh;

[0015] Step 6: Fix the liner, copper block connector and power terminal by graphite fixture, and then place them in a vacuum welding furnace for vacuum welding;

[0016] Step 7: Use ultrasonic cleaning equipment to clean the liner, power terminal and copper block connector completed in step 6 to remove residual solder paste;

[0017] In the eighth step, in a vacuum potting furnace, insulating material is injected into the module obtained after the seventh step to pot and obtain a power module with low parasitic inductance, high power density and double-sided heat dissipation.

[0018] Beneficial effects:

[0019] 1. The power module of the present invention uses a copper block connector to connect the power circuits of the same node, and realizes the overlapping design of the parallel power circuits inside the chip by optimizing the module layout, which can effectively reduce the parasitic inductance of the power commutation circuit to about 1.2nH, thereby significantly reducing the overvoltage shock and current oscillation phenomenon that occurs in the chip during the switching process.

[0020] 2. The present invention uses a double-sided ceramic substrate for heat dissipation, and places the upper tube chip and the lower tube chip of the half-bridge module on the upper and lower DBC liner in an overlapping manner to optimize the heat dissipation path of the chip. This design increases the heat dissipation area and greatly reduces the thermal resistance of the power module.

[0021] 3. The power module of the present invention has high adaptability to application scenarios with high power density requirements, and is of great significance for reducing the cost and improving the efficiency of new energy vehicle electric drive systems and industrial high-power servo motors.

[0022] The present invention will be further described in detail below with reference to the accompanying drawings and embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 It is a front view of the exploded view of the power module of the present invention

[0024] Figure 2 It is a northwest isometric view of an exploded view of the power module of the present invention.

[0025] Figure 3 yes Figure 1 A schematic diagram of the structure of the lower side of the middle upper DBC liner;

[0026] Figure 4 yes Figure 1 A schematic diagram of the structure of the upper side of the middle and lower DBC liner;

[0027] Figure 5 yes Figure 1 A schematic diagram of the structure of the lower side of the middle upper DBC liner;

[0028] Figure 6 yes Figure 1 A schematic diagram of the structure of the upper side of the middle and lower DBC liner;

[0029] Figure 7 is a circuit diagram of a power module body according to the present invention;

[0030] Figure 8 It is a schematic diagram of the structure of the upper side of the silicon carbide MOSFET chip;

[0031] Fig. 9 is a processing flow chart of the power module of the present invention;

[0032] Fig.10 is a schematic diagram of a commutation circuit path of a power module of the present invention;

[0033] Fig.11 It is a schematic diagram of a power copper surface and a copper block connector of a DC+ node of a power module of the present invention;

[0034] Fig.12 is a schematic diagram of a power copper surface and a copper block connector of a DC-node of a power module of the present invention;

[0035] Fig.13 It is a schematic diagram of the connection method of the upper DBC liner and the lower DBC liner of the power module of the present invention;

[0036] Fig.14 A perspective on the power module chip layout Figure 1 ;

[0037] Fig.15 is a partial left side diagram of a power module having the same commutation path of the power module according to the present invention;

[0038] Fig.16 This is the second schematic diagram of the power module chip layout;

[0039] Fig.17 is a partial diagram of a chip of different commutation circuits of a power module according to the present invention;

[0040] Fig.18 FIG. 4 is a partial diagram of the chip layout of the power module according to the present invention.

[0041] Reference numerals:

[0042] The first chip 1A, the second chip 1B, the third chip 1C, the fourth chip 1D, the fifth chip 1E, the sixth chip 1F, the seventh chip 1G and the eighth chip 1, the first bonding wire 2A, the second bonding wire 2B, the third bonding wire 2C, the fourth bonding wire 2D, the fifth bonding wire 2E, the sixth bonding wire 2F, the seventh bonding wire 2G, the eighth bonding wire 2H, the Kelvin source terminal 311, the first Kelvin source copper surface 3A, the second Kelvin source copper surface 3B, the third Kelvin source copper surface 3C, the fourth Kelvin source copper surface 3D, the fifth Kelvin source copper surface 3E, the sixth Kelvin source copper surface 3F, the seventh Kelvin source copper surface 3G and the eighth Kelvin source copper surface 3H, first gate copper surface 4A, second gate copper surface 4B, third gate copper surface 4C, fourth gate copper surface 4D, fifth gate copper surface 4E, sixth gate copper surface 4F, seventh gate copper surface 4G and eighth gate copper surface 4H, gate terminal 411, ninth bonding wire 5A, tenth bonding wire 5B, eleventh bonding wire 5C, twelfth bonding wire 5D, thirteenth bonding wire 5E, fourteenth bonding wire 5F, fifteenth bonding wire 5G, sixteenth bonding wire 5H, seventeenth bonding wire 6A, eighteenth bonding wire 6B, nineteenth bonding wire 6C, twentieth bonding wire 6D, twenty-first bonding wire 6E, twenty-second bonding wire 6F, The twenty-third bonding wire 6G, the twenty-fourth bonding wire 6H, the first power copper plane 7, the second power copper plane 8, the third power copper plane 9, the fourth power copper plane 10, the fifth power copper plane 11, the sixth power copper plane 12, the seventh power copper plane 13 and the eighth power copper plane 14, the ninth power copper plane 15, the tenth power copper plane 16, the eleventh power copper plane 17, the twelfth power copper plane 18, the thirteenth power copper plane 19, the fourteenth power copper plane 20, the fifteenth power copper plane 21 and the sixteenth power copper plane 22, the first power terminal 23, the second power terminal 24, the third power terminal 25, the fourth power terminal 26, the fifth power terminal 27, the sixth power Terminal 28, seventh power terminal 29, eighth power terminal 30, first insulating layer 31, second insulating layer 32, first output terminal 33, second output terminal 34, first copper block connector 35, second copper block connector 36, third copper block connector 37, fourth copper block connector 38, fifth copper block connector 39, sixth copper block connector 40, seventh copper block connector 41, eighth copper block connector 42, ninth copper block connector 43, tenth copper block connector 44, eleventh copper block connector 45, twelfth copper block connector 46, thirteenth copper block connector 47, fourteenth copper block connector 48, first heat dissipation layer 49, second heat dissipation layer 50. DETAILED DESCRIPTION

[0043] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0044] In order to solve the above problems, the present invention proposes a power module packaging structure with low parasitic inductance, high power density and double-sided heat dissipation. This structure adjusts the power circuit path of the parallel chips through a copper block connector to achieve mutual inductance cancellation. This innovative design can reduce the parasitic inductance of the power commutation circuit to below 1.2nH, effectively reducing the overvoltage shock and current oscillation generated during the chip switching process. In addition, the structure also optimizes the heat dissipation path of the parallel chips, uses a double-sided ceramic substrate for heat dissipation, increases the heat dissipation area, and greatly reduces the thermal resistance of the power module. This module structure is suitable for high power density power electronics application scenarios, and is of great significance for improving the efficiency and system power density of new energy vehicle electric drive systems and industrial high-power servo motors.

[0045] Combination Figures 1 to 9 The present invention provides a power module with low parasitic inductance, high power density and double-sided heat dissipation, comprising:

[0046] An upper DBC liner and a lower DBC liner, wherein the lower DBC liner is arranged in parallel with the upper DBC liner and is electrically connected to a corresponding port of the upper DBC liner;

[0047] Four chips, power terminals, copper block connectors, gate copper surfaces, Kelvin source copper surfaces, output terminals and bonding wires are arranged on the upper DBC substrate and the lower DBC substrate;

[0048] Among them, the power terminal is arranged on the same side of the upper DBC liner and the lower DBC liner, and the power terminals of the upper DBC liner and the lower DBC liner both include a DC+ power terminal and a DC- power terminal, and the DC+ power terminal and the DC- power terminal are arranged alternately with each other; the upper DBC liner and the lower DBC liner are connected through the copper block connector; the output terminal is arranged on the side away from the power terminal; the gate copper surface and the Kelvin source copper surface are adjacently arranged inside the upper DBC liner and the lower DBC liner; the chip is connected to the gate copper surface and the Kelvin source copper surface through the bonding wire.

[0049] The chip of the present invention is a silicon carbide MOSFET chip, the drain of the silicon carbide MOSFET chip is welded on the corresponding upper DBC liner or the lower DBC liner, the source of the silicon carbide MOSFET chip is connected to the corresponding source bonding wire, and the gate of the silicon carbide MOSFET chip is connected to the corresponding gate bonding wire.

[0050] The present invention can also be a power module with low parasitic inductance and high power density and double-sided heat dissipation in a housing, in the form of an electronic product. Of course, the housing of the present invention can be a plastic shell or a metal shell, and the present invention is not limited here. Of course, the present invention can also protect the power module with a filler in the remaining space of the packaging housing. The filler is a resin, an insulating glue or a silicone rubber material,

[0051] The present invention provides a power module with low parasitic inductance and high power density and double-sided heat dissipation, and a preparation method thereof. An overlapping layout design is adopted to set the positions of the power copper surface and the power terminal, so that the power copper surfaces and the power terminals of the DC+ node and the DC- node are arranged alternately, thereby enhancing the mutual inductance cancellation effect of the power commutation circuit. Secondly, a copper block connector is used to connect the power circuits of the same node, thereby reducing the self-inductance of the commutation circuit. The optimized design of the present invention reduces the mutual inductance of each power circuit between different DBC liners and between the same liners, and reduces the self-inductance within the same power circuit. Therefore, the present invention can effectively reduce the voltage shock and current oscillation of the chip during the switching process. The present invention is mainly used in high-frequency, high-power density power electronic devices. In these application scenarios, it is crucial to reduce the parasitic parameters of the power module.

[0052] Combination Figure 1 and Figure 3 The upper DBC liner of the present invention comprises a first insulating layer 31, a first heat dissipation layer, a first metal layer 49, an upper plate gate copper surface and an upper plate Kelvin source copper surface; the gate copper surface arranged in the upper DBC liner is the upper plate gate copper surface, and the Kelvin source copper surface arranged in the upper DBC liner is the upper plate Kelvin source copper surface; the first insulating layer 31 is arranged between the first metal layer and the first heat dissipation layer 49; the chip is arranged at a corresponding position of the first metal layer;

[0053] Combination Figure 1 and Figure 4 , the lower DBC liner includes a second insulating layer 32, a second heat dissipation layer 50, a second metal layer, a lower plate gate copper surface and a lower plate Kelvin source copper surface; the gate copper surface arranged in the lower DBC liner is the lower plate gate copper surface, and the Kelvin source copper surface arranged in the lower DBC liner is the lower plate Kelvin source copper surface; the second insulating layer 32 is arranged between the second metal layer and the second heat dissipation layer 50; the chip is arranged at a corresponding position of the second metal layer;

[0054] Gate terminals are arranged adjacent to each other on the upper plate gate copper surface and the lower plate gate copper surface; the upper plate gate copper surface is connected to the adjacent gate terminal; the lower plate gate copper surface is connected to the adjacent gate terminal; Kelvin source terminals are arranged adjacent to each other on the upper plate Kelvin source copper surface and the lower plate Kelvin source copper surface, the upper plate Kelvin source copper surface is connected to the adjacent Kelvin source terminal; the lower plate Kelvin source copper surface is connected to the adjacent Kelvin source terminal.

[0055] Combination Figure 3-Figure 7 , the first metal layer includes a first power copper plane 7, a second power copper plane 8, a third power copper plane 9, a fourth power copper plane 10, a fifth power copper plane 11, a sixth power copper plane 12, a seventh power copper plane 13 and an eighth power copper plane 14; the second metal layer includes a ninth power copper plane 15, a tenth power copper plane 16, an eleventh power copper plane 17, a twelfth power copper plane 18, a thirteenth power copper plane 19, a fourteenth power copper plane 20, a fifteenth power copper plane 21 and a sixteenth power copper plane 22;

[0056] Among them, the first power copper surface 7 and the second power copper surface 8 constitute a first copper surface area; the third power copper surface 9 and the fourth power copper surface 10 constitute a second copper surface area; the fifth power copper surface 11 and the sixth power copper surface 12 constitute a first copper surface area; the seventh power copper surface 13 and the eighth power copper surface 14 constitute a second copper surface area; the ninth power copper surface 15 and the tenth power copper surface 16 constitute a first copper surface area; the eleventh power copper surface 17 and the twelfth power copper surface 18 constitute a second copper surface area; the thirteenth power copper surface 19 and the fourteenth power copper surface 20 constitute a first copper surface area; the fifteenth power copper surface 21 and the sixteenth power copper surface 22 constitute a second copper surface area; the first copper surface area and the second copper surface area are arranged alternately.

[0057] Combination Figures 3 to 6 , the four chips arranged on the lower DBC substrate include a first chip 1A, a second chip 1B, a third chip 1C and a fourth chip 1D; the four chips arranged on the upper DBC substrate include a fifth chip 1E, a sixth chip 1F, a seventh chip 1G and an eighth chip 1H;

[0058] The first chip 1A is connected to the corresponding position of the first power copper surface 7; the second chip 1B is connected to the corresponding position of the fourth power copper surface 10; the third chip 1C is connected to the corresponding position of the fifth power copper surface 11; the fourth chip 1D is connected to the corresponding position of the eighth power copper surface 14; the fifth chip 1E is connected to the corresponding position of the tenth power copper surface 16; the sixth chip 1F is connected to the corresponding position of the eleventh power copper surface 17; the seventh chip 1G is connected to the corresponding position of the fourteenth power copper surface 20; and the eighth chip 1H is connected to the corresponding position of the fifteenth power copper surface 21.

[0059] In the present invention, the first chip 1A and the first power copper surface 7 are connected by welding, the second chip 1B and the fourth power copper surface 10 are connected by welding, the third chip 1C and the fifth power copper surface 11 are connected by welding, the fourth chip 1D and the eighth power copper surface 14 are connected by welding, the fifth chip 1E and the tenth power copper surface 16 are connected by welding, the sixth chip 1F and the eleventh power copper surface 17 are connected by welding, the seventh chip 1G and the fourteenth power copper surface 20 are connected by welding, and the eighth chip 1H and the fifteenth power copper surface 21 are connected by welding.

[0060] like Fig.14 , Fig.14 The layout of two chips in a power module is shown. In this case, both chips are located on the upper DBC substrate, which does not fully utilize the vertical space. Since the two chips are close to each other, the heat dissipation effect is poor. To achieve better heat dissipation, the horizontal distance between the two chips must be increased, resulting in a decrease in space utilization.

[0061] Fig.15 The layout of two chips in the same commutation loop in this module is shown. The design cleverly utilizes the vertical distance and places the chips of the same commutation loop on different substrates. This effectively increases the distance between the two chips without increasing the horizontal distance. Because the vertical distance is effectively utilized, the space utilization rate is high. Fig.16 The figure below shows the layout of two chips in a power module. The two chips are located on different substrates, but they are placed on the same Z axis. This layout does not effectively utilize the horizontal distance, resulting in a close distance between the two chips, which affects the heat dissipation effect of the module. In order to achieve better heat dissipation, the vertical distance between the two chips needs to be increased, but this will result in a decrease in space utilization. On the contrary, Fig.17The layout of the two chips in different commutation circuits in this module is shown in Figure 1. They cleverly use the horizontal distance to effectively increase the distance between the two chips without increasing the vertical distance. Because the horizontal distance is effectively used, the space utilization rate is high. Finally, Fig.18 Four chips on two commutation circuits are shown, which make full use of the horizontal and vertical space, so the space utilization rate is high and the heat dissipation effect is better.

[0062] Combination Figures 1 to 7 , the power terminal of the present invention includes a first power terminal 23, a second power terminal 24, a third power terminal 25, a fourth power terminal 26, a fifth power terminal 27, a sixth power terminal 28, a seventh power terminal 29 and an eighth power terminal 30;

[0063] Among them, the first power terminal 23, the third power terminal 25, the sixth power terminal 28 and the eighth power terminal 30 are DC-power terminals; the second power terminal 24, the fourth power terminal 26, the fifth power terminal 27 and the seventh power terminal 29 are DC+power terminals; the first power terminal 23 is connected to the second power copper surface 8; the second power terminal 24 is connected to the fourth power copper surface 10; the third power terminal 25 is connected to the sixth power copper surface 12, and the fourth power terminal 26 is connected to the eighth power copper surface 14; the fifth power terminal 27 is connected to the tenth power copper surface 16; the sixth power terminal 28 is connected to the twelfth power copper surface 18; the seventh power terminal 29 is connected to the fourteenth power copper surface 20, and the eighth power terminal 30 is connected to the sixteenth power copper surface 22.

[0064] The first power terminal 23, the second power copper plane 8, the third power terminal 25, the sixth power copper plane 12, the twelfth power copper plane 18, the sixteenth power copper plane 22, the sixth power terminal 28 and the eighth power terminal 30 are DC-nodes; the fifth power terminal 27, the tenth power copper plane 16, the seventh power terminal 29 and the fourteenth power copper plane 20, the second power terminal 24, the fourth power copper plane 10, the fourth power terminal 26, and the eighth power copper plane 14 are DC+nodes. The current in the commutation path flows from the DC+node to the DC-node.

[0065] like Fig.10As shown, the current flows from the tenth power copper plane 16 of the DC+ node to the second power copper plane 8 of the DC- node, from the fourth power copper plane 10 of the DC+ node to the twelfth power copper plane 18 of the DC- node, from the fourteenth power copper plane 20 of the DC+ node to the sixth power copper plane 12 of the DC- node, and from the eighth power copper plane 14 of the DC+ node to the sixteenth power copper plane 22 of the DC- node. This design makes each adjacent commutation loop in opposite directions, and the power terminals of the DC+ and DC- nodes are staggered in the vertical direction, as shown in FIG. Figure 2 As shown, for example, the node of power terminal 23 is DC-, and the node of power terminal 27 is DC+; they are also arranged alternately in the horizontal direction, such as Figure 2 As shown, for example, the node of power terminal 23 is DC-, and the node of power terminal 24 is DC+. This layout makes the direction of each commutation loop in the power module opposite to the direction of the commutation loop closest to it, so the mutual inductance cancellation effect of the inductance is stronger and the total inductance is lower, thereby reducing the voltage overshoot when the module is turned off, reducing the switching loss, and improving the performance, which is especially conducive to high-frequency use.

[0066] Combination Figures 1 to 7 , the output terminal includes a first output terminal and a second output terminal; the first output terminal is arranged on the first insulating layer 31, the first power copper surface 7, the third power copper surface 9, the fifth power copper surface 11 and the seventh power copper surface 13 away from the power terminal, and is connected to the first insulating layer 31, the first power copper surface 7, the third power copper surface 9, the fifth power copper surface 11 and the seventh power copper surface 13;

[0067] The second output terminal is arranged on the second insulating layer 32, the ninth power copper plane 15, the eleventh power copper plane 17, the thirteenth power copper plane 19 and the fifteenth power copper plane 21 away from the power terminal, and is connected to the second insulating layer 32, the ninth power copper plane 15, the eleventh power copper plane 17, the thirteenth power copper plane 19 and the fifteenth power copper plane 21.

[0068] Combination Figures 1 to 7 , the copper block connectors include a first copper block connector 35, a second copper block connector 36, a third copper block connector 37, a fourth copper block connector 38, a fifth copper block connector 39, a sixth copper block connector 40, a seventh copper block connector 41, an eighth copper block connector 42, a ninth copper block connector 43, a tenth copper block connector 44, an eleventh copper block connector 45, a twelfth copper block connector 46, a thirteenth copper block connector 47 and a fourteenth copper block connector 48;

[0069] Among them, one side of the first copper block connector 35 is connected to the second power copper surface 8; one side of the ninth copper block connector 43 is connected to the tenth power copper surface 16, and the other side of the first copper block connector 35 is connected to the other side of the ninth copper block connector 43; one side of the second copper block connector 36 is connected to the fourth power copper surface 10; one side of the eighth copper block connector 42 is connected to the twelfth power copper surface 18; the other side of the first copper block connector 35 is connected to the other side of the eighth copper block connector 42; one side of the third copper block connector 37 is connected to the fourth power copper surface 10; one side of the eleventh copper block connector 45 is connected to the fourteenth power copper surface 20; the other side of the third copper block connector 37 is connected to the other side of the eleventh copper block connector 45; one side of the fourth copper block connector 38 is connected to the sixth power copper surface 12; one side of the tenth copper block connector 44 is connected to the twelfth power copper surface 18; the other side of the fourth copper block connector 38 is connected to the other side of the tenth copper block connector 44; one side of the fifth copper block connector 39 is connected to the sixth power copper surface 12; one side of the twelfth copper block connector 46 is connected to the twelfth power copper surface 18; the other side of the fifth copper block connector 39 is connected to the other side of the twelfth copper block connector 46; one side of the sixth copper block connector 40 is connected to the sixth power copper surface 12; one side of the fourteenth copper block connector is connected to the sixteenth power copper surface 22; the other side of the sixth copper block connector 40 is connected to the other side of the fourteenth copper block connector 48; one side of the seventh copper block connector 41 is connected to the eighth power copper surface 14; one side of the thirteenth copper block connector 47 is connected to the fourteenth power copper surface 20; the other side of the seventh copper block connector 41 is connected to the other side of the thirteenth copper block connector 47.

[0070] Combination Figures 1 to 7 The upper plate Kelvin source copper surface includes a first Kelvin source copper surface 3A, a second Kelvin source copper surface 3B, a third Kelvin source copper surface 3C and a fourth Kelvin source copper surface 3D; the lower plate Kelvin source copper surface includes a fifth Kelvin source copper surface 3E, a sixth Kelvin source copper surface 3F, a seventh Kelvin source copper surface 3G and an eighth Kelvin source copper surface 3H;

[0071] The upper plate gate copper surface includes a first gate copper surface 4A, a second gate copper surface 4B, a third gate copper surface 4C and a fourth gate copper surface 4D; the lower plate gate copper surface includes a fifth gate copper surface 4E, a sixth gate copper surface 4F, a seventh gate copper surface 4G and an eighth gate copper surface 4H, wherein the gate copper surface is adjacent to the corresponding Kelvin source copper surface.

[0072] Wherein, the first Kelvin source copper surface 3A and the third Kelvin source copper surface 3C are located on the same side; the second Kelvin source copper surface 3B and the fourth Kelvin source copper surface 3D are located on the same side; the first Kelvin source copper surface 3A and the second Kelvin source copper surface 3B are located on different sides; the fifth Kelvin source copper surface 3E and the seventh Kelvin source copper surface 3G are located on the same side; the sixth Kelvin source copper surface 3F and the eighth Kelvin source copper surface 3H are located on the same side; the fifth Kelvin source copper surface 3E and the sixth Kelvin source copper surface 3F are located on different sides;

[0073] refer to Figures 1 to 7 , the bonding wires include a first bonding wire 2A, a second bonding wire 2B, a third bonding wire 2C, a fourth bonding wire 2D, a fifth bonding wire 2E, a sixth bonding wire 2F, a seventh bonding wire 2G, an eighth bonding wire 2H, a ninth bonding wire 5A, a tenth bonding wire 5B, an eleventh bonding wire 5C, a twelfth bonding wire 5D, a thirteenth bonding wire 5E, a fourteenth bonding wire 5F, a fifteenth bonding wire 5G, a sixteenth bonding wire 5H, a seventeenth bonding wire 6A, an eighteenth bonding wire 6B, a nineteenth bonding wire 6C, a twentieth bonding wire 6D, a twenty-first bonding wire 6E, a twenty-second bonding wire 6F, a twenty-third bonding wire 6G, and a twenty-fourth bonding wire 6H;

[0074] One side of the first bonding wire 2A is connected to the first chip 1A, and the other side is connected to the second power copper surface 8; one side of the second bonding wire 2B is connected to the second chip 1B, and the other side is connected to the third power copper surface 9; one side of the third bonding wire 2C is connected to the third chip 1C, and the other side is connected to the sixth power copper surface 12; one side of the fourth bonding wire 2D is connected to the fourth chip 1D, and the other side is connected to the seventh power copper surface 13; one side of the fifth bonding wire 2E is connected to the fifth chip 1E, and the other side is connected to the ninth power copper surface 15; one side of the sixth bonding wire 2F is connected to the sixth chip 1F, and the other side is connected to the twelfth power copper surface 18; one side of the seventh bonding wire 2G is connected to the seventh chip 1G, and the other side is connected to the thirteenth power copper surface 19; one side of the eighth bonding wire 2H is connected to the eighth chip 1H, and the other side is connected to the sixteenth power copper surface 22;

[0075] The ninth bonding wire 5A is connected to the first chip 1A on one side, and connected to the first gate copper surface on the other side; the tenth bonding wire 5B is connected to the second chip 1B on one side, and connected to the second gate copper surface on the other side; the eleventh bonding wire 5C is connected to the third chip 1C on one side, and connected to the third gate copper surface on the other side; the twelfth bonding wire 5D is connected to the fourth chip 1D on one side, and connected to the fourth gate copper surface on the other side; the thirteenth bonding wire 5E is connected to the fifth chip 1E on one side, and connected to the fifth gate copper surface on the other side; the fourteenth bonding wire 5F is connected to the sixth chip 1F on one side, and connected to the sixth gate copper surface on the other side; the fifteenth bonding wire 5G is connected to the seventh chip 1G on one side, and connected to the seventh gate copper surface on the other side; the sixteenth bonding wire 5H is connected to the eighth chip 1H on one side, and connected to the eighth gate copper surface on the other side; the seventeenth bonding wire 6A is connected to the first chip 1 The eighteenth bonding wire 6B is connected to the second chip 1B on one side, and to the second Kelvin source copper surface 3A on the other side; the nineteenth bonding wire 6B is connected to the third chip 1C on one side, and to the third Kelvin source copper surface 3C on the other side; the twentieth bonding wire 6D is connected to the fourth chip 1D on one side, and to the fourth Kelvin source copper surface 3D on the other side; the twenty-first bonding wire 6E is connected to the fifth chip 1E on one side, and to the fifth Kelvin source copper surface on the other side; the twenty-second bonding wire 6F is connected to the sixth chip 1F on one side, and to the sixth Kelvin source copper surface on the other side; the twenty-third bonding wire 6G is connected to the seventh chip 1G on one side, and to the seventh Kelvin source copper surface on the other side; the twenty-fourth bonding wire 6H is connected to the eighth chip 1H on one side, and to the eighth Kelvin source copper surface on the other side.

[0076] like Fig.11 and Fig.12 As shown, the copper block connector connects the power copper planes of the same nodes dispersed on the upper and lower boards. For example, the dispersed fourth power copper plane 10, the tenth power copper plane 16, the eighth power copper plane 14 and the fourteenth power copper plane 20 are connected together by the copper block connector, just like connecting the dispersed DC+ nodes to each other. Similarly, the dispersed second power copper plane 8, the sixth power copper plane 12, the twelfth power copper plane 18 and the sixteenth power copper plane 22 are also connected together by the copper block connector, so that they are all DC- nodes. This innovative design effectively reduces the loop resistance and total inductance.

[0077] like Fig. 9 As shown, the present invention provides a method for preparing a power module with low parasitic inductance, high power density and double-sided heat dissipation to prepare the power module with low parasitic inductance, high power density and double-sided heat dissipation of the present invention.

[0078] The materials and equipment required for the process of the present invention are as follows:

[0079] Customized ceramic substrates, commercialized power chips, customized terminals (several quantities), steel mesh for applying solder paste at specific locations on the ceramic substrate, solder paste materials, vacuum heating furnaces, and potting materials for insulation.

[0080] The preparation process is as follows:

[0081] The first step is to select the upper DBC liner and the lower DBC liner, and apply solder paste on the surface of the prepared upper DBC liner and the lower DBC liner through the steel mesh;

[0082] The steel mesh of the present invention should be cut to a suitable thickness to ensure the connection of the solder and to ensure that there is no excessive application. The first insulating layer and the second insulating layer can be made of materials including Al2O3, AlN, Si3N4, composite resin, etc., and any one of them or a combination thereof can be used alone. It is recommended that the thickness of the first insulating layer and the second insulating layer is 0.6 mm. The first metal layer 12 and the second metal layer 22 should be copper, and the thickness thereof is preferably 0.3 mm.

[0083] In the second step, the chips are placed on the designated positions of the upper DBC liner and the lower DBC liner by a chip mounter, and then placed in a vacuum welding furnace for vacuum welding using a graphite fixture;

[0084] The third step is to use ultrasonic cleaning equipment to clean the surface of the chip and liner completed in the second step to remove the residual solder paste;

[0085] The fourth step is to connect the chip source, gate copper surface and Kelvin source copper surface through a bonding machine;

[0086] The fifth step is to apply solder paste on the surface of the copper block connector, the surface of the power copper surface and the surface of the ceramic substrate through the steel mesh; the solder paste material is Sn63-Pb37.

[0087] Step 6: Fix the liner, copper block connector and power terminal by graphite clamps, and then place them in a vacuum welding furnace for vacuum welding; the welding temperature is set to 180°C.

[0088] Step 7: Use ultrasonic cleaning equipment to clean the liner, power terminal and copper block connector completed in step 6 to remove residual solder paste;

[0089] In the eighth step, in a vacuum potting furnace, insulating material is injected into the module obtained after the seventh step to pot and obtain a power module with low parasitic inductance, high power density and double-sided heat dissipation.

[0090] The filler of the present invention may also be made of other suitable materials such as resin, insulating glue, silicone rubber, etc., to improve the insulation strength and protect the chip at the same time.

[0091] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0092] Although the present application is described herein in conjunction with various embodiments, in the process of implementing the claimed application, those skilled in the art may understand and implement other variations of the disclosed embodiments by reviewing the drawings, the disclosure, and the appended claims. In the claims, the word "comprising" does not exclude other components or steps, and "a" or "an" does not exclude a plurality of components or steps.

[0093] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A power module with low parasitic inductance, high power density and double-sided heat dissipation, characterized in that: include: An upper DBC liner and a lower DBC liner, wherein the lower DBC liner is arranged in parallel with the upper DBC liner and is electrically connected to a corresponding port of the upper DBC liner; Four chips, power terminals, copper block connectors, gate copper surfaces, Kelvin source copper surfaces, output terminals and bonding wires are arranged on the upper DBC substrate and the lower DBC substrate; Wherein, the power terminal is arranged on the same side of the upper DBC liner and the lower DBC liner, the power terminals of the upper DBC liner and the lower DBC liner both include a DC+ power terminal and a DC- power terminal, and the DC+ power terminal and the DC- power terminal are arranged alternately with each other; the upper DBC liner and the lower DBC liner are connected through the copper block connector; the output terminal is arranged on a side away from the power terminal; the gate copper surface and the Kelvin source copper surface are adjacently arranged inside the upper DBC liner and the lower DBC liner; the chip is connected to the gate copper surface and the Kelvin source copper surface through the bonding wire; The upper DBC liner includes a first insulating layer, a first heat dissipation layer, a first metal layer, an upper plate gate copper surface and an upper plate Kelvin source copper surface; the gate copper surface arranged in the upper DBC liner is the upper plate gate copper surface, and the Kelvin source copper surface arranged in the upper DBC liner is the upper plate Kelvin source copper surface; the first insulating layer is arranged between the first metal layer and the first heat dissipation layer; the chip is arranged at a corresponding position of the first metal layer; The lower DBC liner includes a second insulating layer, a second heat dissipation layer, a second metal layer, a lower plate gate copper surface and a lower plate Kelvin source copper surface; the gate copper surface arranged in the lower DBC liner is the lower plate gate copper surface, and the Kelvin source copper surface arranged in the lower DBC liner is the lower plate Kelvin source copper surface; the second insulating layer is arranged between the second metal layer and the second heat dissipation layer; the chip is arranged at a corresponding position of the second metal layer; Gate terminals are disposed adjacent to each other on the upper plate gate copper surface and the lower plate gate copper surface; the upper plate gate copper surface is connected to the adjacent gate terminal; the lower plate gate copper surface is connected to the adjacent gate terminal; Kelvin source terminals are disposed adjacent to each other on the upper plate Kelvin source copper surface and the lower plate Kelvin source copper surface, the upper plate Kelvin source copper surface is connected to the adjacent Kelvin source terminal; the lower plate Kelvin source copper surface is connected to the adjacent Kelvin source terminal; The first metal layer includes a first power copper plane, a second power copper plane, a third power copper plane, a fourth power copper plane, a fifth power copper plane, a sixth power copper plane, a seventh power copper plane and an eighth power copper plane; The second metal layer includes a ninth power copper plane, a tenth power copper plane, an eleventh power copper plane, a twelfth power copper plane, a thirteenth power copper plane, a fourteenth power copper plane, a fifteenth power copper plane and a sixteenth power copper plane; Among them, the first power copper surface and the second power copper surface form a first copper surface area; the third power copper surface and the fourth power copper surface form a second copper surface area; the fifth power copper surface and the sixth power copper surface form a first copper surface area; the seventh power copper surface and the eighth power copper surface form a second copper surface area; the ninth power copper surface and the tenth power copper surface form a first copper surface area; the eleventh power copper surface and the twelfth power copper surface form a second copper surface area; the thirteenth power copper surface and the fourteenth power copper surface form a first copper surface area; the fifteenth power copper surface and the sixteenth power copper surface form a second copper surface area; the first copper surface area and the second copper surface area are arranged alternately; The power terminals include a first power terminal, a second power terminal, a third power terminal, a fourth power terminal, a fifth power terminal, a sixth power terminal, a seventh power terminal and an eighth power terminal; Among them, the first power terminal, the third power terminal, the sixth power terminal and the eighth power terminal are DC-power terminals; the second power terminal, the fourth power terminal, the fifth power terminal and the seventh power terminal are DC+power terminals; the first power terminal is connected to the second power copper surface; the second power terminal is connected to the fourth power copper surface; the third power terminal is connected to the sixth power copper surface, and the fourth power terminal is connected to the eighth power copper surface; the fifth power terminal is connected to the tenth power copper surface; the sixth power terminal is connected to the twelfth power copper surface; the seventh power terminal is connected to the fourteenth power copper surface, and the eighth power terminal is connected to the sixteenth power copper surface.

2. The power module with low parasitic inductance and high power density and double-sided heat dissipation according to claim 1, characterized in that: The output terminal comprises a first output terminal and a second output terminal; the first output terminal is arranged on the first insulating layer, the first power copper surface, the third power copper surface, the fifth power copper surface and the seventh power copper surface away from the power terminal, and is connected to the first insulating layer, the first power copper surface, the third power copper surface, the fifth power copper surface and the seventh power copper surface; The second output terminal is arranged on the second insulating layer, the ninth power copper plane, the eleventh power copper plane, the thirteenth power copper plane and the fifteenth power copper plane away from the power terminal, and is connected to the second insulating layer, the ninth power copper plane, the eleventh power copper plane, the thirteenth power copper plane and the fifteenth power copper plane.

3. The power module with low parasitic inductance and high power density and double-sided heat dissipation according to claim 2, characterized in that: The copper block connectors include a first copper block connector, a second copper block connector, a third copper block connector, a fourth copper block connector, a fifth copper block connector, a sixth copper block connector, a seventh copper block connector, an eighth copper block connector, a ninth copper block connector, a tenth copper block connector, an eleventh copper block connector, a twelfth copper block connector, a thirteenth copper block connector and a fourteenth copper block connector; Among them, one side of the first copper block connector is connected to the second power copper surface; one side of the ninth copper block connector is connected to the tenth power copper surface, and the other side of the first copper block connector is connected to the other side of the ninth copper block connector; one side of the second copper block connector is connected to the fourth power copper surface; one side of the eighth copper block connector is connected to the twelfth power copper surface; the other side of the first copper block connector is connected to the other side of the eighth copper block connector; one side of the third copper block connector is connected to the fourth power copper surface; one side of the eleventh copper block connector is connected to the fourteenth power copper surface; the other side of the third copper block connector is connected to the other side of the eleventh copper block connector; one side of the fourth copper block connector is connected to the sixth power copper surface; one side of the tenth copper block connector is connected to the twelfth power copper surface; the other side of the fourth copper block connector is connected to the other side of the tenth copper block connector; one side of the fifth copper block connector is connected to the sixth power copper surface; one side of the twelfth copper block connector is connected to the twelfth power copper surface; the other side of the fifth copper block connector is connected to the other side of the twelfth copper block connector; one side of the sixth copper block connector is connected to the sixth power copper surface; one side of the fourteenth copper block connector is connected to the sixteenth power copper surface; the other side of the sixth copper block connector is connected to the other side of the fourteenth copper block connector; one side of the seventh copper block connector is connected to the eighth power copper surface; one side of the thirteenth copper block connector is connected to the fourteenth power copper surface; the other side of the seventh copper block connector is connected to the other side of the thirteenth copper block connector.

4. The power module with low parasitic inductance and high power density and double-sided heat dissipation according to claim 3, characterized in that: The four chips arranged on the lower DBC substrate include a first chip, a second chip, a third chip and a fourth chip; the four chips arranged on the upper DBC substrate include a fifth chip, a sixth chip, a seventh chip and an eighth chip (1H); The first chip is connected to the corresponding position of the first power copper surface; the second chip is connected to the corresponding position of the fourth power copper surface; the third chip is connected to the corresponding position of the fifth power copper surface; the fourth chip is connected to the corresponding position of the eighth power copper surface; the fifth chip is connected to the corresponding position of the tenth power copper surface; the sixth chip is connected to the corresponding position of the eleventh power copper surface; the seventh chip is connected to the corresponding position of the fourteenth power copper surface; and the eighth chip (1H) is connected to the corresponding position of the fifteenth power copper surface.

5. The power module with low parasitic inductance and high power density and double-sided heat dissipation according to claim 4, characterized in that: The upper plate Kelvin source copper surface includes a first Kelvin source copper surface, a second Kelvin source copper surface, a third Kelvin source copper surface and a fourth Kelvin source copper surface; the lower plate Kelvin source copper surface includes a fifth Kelvin source copper surface, a sixth Kelvin source copper surface, a seventh Kelvin source copper surface and an eighth Kelvin source copper surface; The first Kelvin source copper surface and the third Kelvin source copper surface are located on the same side; the second Kelvin source copper surface and the fourth Kelvin source copper surface are located on the same side; the first Kelvin source copper surface and the second Kelvin source copper surface are located on different sides; the fifth Kelvin source copper surface and the seventh Kelvin source copper surface are located on the same side; the sixth Kelvin source copper surface and the eighth Kelvin source copper surface are located on the same side; the fifth Kelvin source copper surface and the sixth Kelvin source copper surface are located on different sides; The upper plate gate copper surface includes a first gate copper surface, a second gate copper surface, a third gate copper surface and a fourth gate copper surface; the lower plate gate copper surface includes a fifth gate copper surface, a sixth gate copper surface, a seventh gate copper surface and an eighth gate copper surface; wherein the gate copper surface is adjacent to the corresponding Kelvin source copper surface.

6. The power module with low parasitic inductance and high power density and double-sided heat dissipation according to claim 5, characterized in that: The bonding wires include a first bonding wire, a second bonding wire, a third bonding wire, a fourth bonding wire, a fifth bonding wire, a sixth bonding wire, a seventh bonding wire, an eighth bonding wire, a ninth bonding wire, a tenth bonding wire, an eleventh bonding wire, a twelfth bonding wire, a thirteenth bonding wire, a fourteenth bonding wire, a fifteenth bonding wire, a sixteenth bonding wire, a seventeenth bonding wire, an eighteenth bonding wire, a nineteenth bonding wire, a twentieth bonding wire, a twenty-first bonding wire, a twenty-second bonding wire, a twenty-third bonding wire, and a twenty-fourth bonding wire; One side of the first bonding wire is connected to the first chip, and the other side is connected to the second power copper surface; one side of the second bonding wire is connected to the second chip, and the other side is connected to the third power copper surface; one side of the third bonding wire is connected to the third chip, and the other side is connected to the sixth power copper surface; one side of the fourth bonding wire is connected to the fourth chip, and the other side is connected to the seventh power copper surface; one side of the fifth bonding wire is connected to the fifth chip, and the other side is connected to the ninth power copper surface; one side of the sixth bonding wire is connected to the sixth chip, and the other side is connected to the twelfth power copper surface; one side of the seventh bonding wire is connected to the The seventh chip is connected to the thirteenth power copper surface on one side, and the other side is connected to the thirteenth power copper surface; the eighth bonding wire is connected to the eighth chip on one side, and the other side is connected to the sixteenth power copper surface on the other side; the ninth bonding wire is connected to the first chip on one side, and the other side is connected to the first gate copper surface on the other side; the tenth bonding wire is connected to the second chip on one side, and the other side is connected to the second gate copper surface on the other side; the eleventh bonding wire is connected to the third chip on one side, and the other side is connected to the third gate copper surface on the other side; the twelfth bonding wire is connected to the fourth chip on one side, and the other side is connected to the fourth gate copper surface; the thirteenth bonding wire is connected to the fifth chip on one side, and the One side of the fourteenth bonding wire is connected to the sixth chip, and the other side is connected to the sixth gate copper surface; one side of the fourteenth bonding wire is connected to the sixth chip, and the other side is connected to the sixth gate copper surface; one side of the fifteenth bonding wire is connected to the seventh chip, and the other side is connected to the seventh gate copper surface; one side of the sixteenth bonding wire is connected to the eighth chip, and the other side is connected to the eighth gate copper surface; one side of the seventeenth bonding wire is connected to the first chip, and the other side is connected to the first Kelvin source copper surface; one side of the eighteenth bonding wire is connected to the second chip, and the other side is connected to the second Kelvin source copper surface; one side of the nineteenth bonding wire is connected to the third chip; The 20th bonding wire is connected to the fourth chip on one side, and the other side is connected to the fourth Kelvin source copper surface on the other side; the 21st bonding wire is connected to the fifth chip on one side, and the other side is connected to the fifth Kelvin source copper surface on the other side; the 22nd bonding wire is connected to the sixth chip on one side, and the other side is connected to the sixth Kelvin source copper surface on the other side; the 23rd bonding wire is connected to the seventh chip on one side, and the other side is connected to the seventh Kelvin source copper surface on the other side; the 24th bonding wire is connected to the eighth chip on one side, and the other side is connected to the eighth Kelvin source copper surface on the other side.

7. A method for preparing a power module with low parasitic inductance, high power density and double-sided heat dissipation, characterized in that: A power module with low parasitic inductance and high power density and double-sided heat dissipation as claimed in any one of claims 1 to 6 is prepared, the preparation method comprising: The first step is to select the upper DBC liner and the lower DBC liner, and apply solder paste on the surface of the prepared upper DBC liner and the lower DBC liner through the steel mesh; In the second step, the chips are placed on the designated positions of the upper DBC liner and the lower DBC liner by a chip mounter, and then placed in a vacuum welding furnace for vacuum welding using a graphite fixture; The third step is to use ultrasonic cleaning equipment to clean the surface of the chip and liner completed in the second step to remove the residual solder paste; The fourth step is to connect the chip source, gate copper surface and Kelvin source copper surface through a bonding machine; Step 5: Apply solder paste on the copper block connector surface, the power copper surface surface and the ceramic substrate surface through the steel mesh; Step 6: Fix the liner, copper block connector and power terminal by graphite fixture, and then place them in a vacuum welding furnace for vacuum welding; Step 7: Use ultrasonic cleaning equipment to clean the liner, power terminal and copper block connector completed in step 6 to remove residual solder paste; In the eighth step, in a vacuum potting furnace, insulating material is injected into the module obtained after the seventh step to pot and obtain a power module with low parasitic inductance, high power density and double-sided heat dissipation.

Images