A digital brake valve self-checking control system

Abstract

The present disclosure relates to a kind of digital brake valve self-checking control system, including control circuit, power drive circuit, monitoring circuit and current sensor;Control circuit and power drive circuit are connected, monitoring circuit is arranged between power drive circuit and digital brake valve, and the input end of monitoring circuit is connected with the output end of power drive circuit, current sensor is connected with power drive circuit and control circuit respectively;Current sensor, for collecting the bus current of power drive circuit;Monitoring circuit, for collecting the level signal information output by the output end of power drive circuit when digital brake valve is in the first working state;Control circuit, for determining whether digital brake valve has failed based on the level signal information collected by monitoring circuit;And in the case of determining that failure has occurred, determine the fault type of digital brake valve based on bus current and level signal information.The present disclosure can reliably detect the failure of digital brake valve.

Description

Technical Field

[0001] This disclosure relates to the field of digital servo control, and more particularly to a digital brake valve self-test control system. Background Technology

[0002] Digital brake valves, as a new type of digital hydraulic control component, offer advantages over traditional servo valves, including simple structure, robustness, low cost, strong resistance to contamination, low leakage, and high fault tolerance, making them an important member of the digital hydraulic component family. BIT (Built-in Test) technology refers to a technique where a system relies on internally designed self-testing circuits and software modules to perform system self-testing, fault diagnosis, and isolation. Aircraft braking systems have high reliability and safety requirements; therefore, BIT monitoring design for the braking system controller is essential to improve system reliability.

[0003] In related technologies, the digital brake valve of an aircraft is monitored by acquiring the current value of the drive output port through an analog acquisition circuit. This method uses a large number of circuit components and suffers from low integration and low reliability. Summary of the Invention

[0004] This disclosure provides a digital brake valve self-test control system.

[0005] According to a first aspect of this disclosure, a digital brake valve self-test control system is provided, the system comprising: a control circuit, a power drive circuit, a monitoring circuit, and a current sensor; wherein the control circuit and the power drive circuit are connected, the monitoring circuit is disposed between the power drive circuit and the digital brake valve, and the input terminal of the monitoring circuit is connected to the output terminal of the power drive circuit, and the current sensor is connected to both the power drive circuit and the control circuit.

[0006] The current sensor is used to collect the bus current of the power drive circuit;

[0007] The monitoring circuit is used to collect the level signal information output by the output terminal of the power drive circuit when the digital brake valve is in the first working state.

[0008] The control circuit is used to determine whether the digital brake valve has malfunctioned based on the level signal information collected by the monitoring circuit; and if a malfunction is determined, to determine the malfunction type of the digital brake valve based on the bus current and the level signal information.

[0009] Furthermore, the power drive circuit includes multiple output terminals, one of which is used to control a digital brake valve;

[0010] The monitoring circuit is used to collect the level signal information output by each of the output terminals;

[0011] The control circuit is used to determine the faulty digital brake valve among the multiple digital brake valves based on the level signal information output by each of the output terminals.

[0012] Furthermore, the system also includes a pressure sensor; wherein the pressure sensor is connected to both the digital brake valve and the control circuit.

[0013] The pressure sensor is used to collect pressure data of the digital brake valve when the digital brake valve is in the second working state.

[0014] The control circuit is used to determine, based on the pressure data, whether the digital brake valve is experiencing a valve core jamming fault.

[0015] Furthermore, the monitoring circuit includes: an access resistor, an optocoupler, and a pull-up resistor; wherein the access resistor is connected to the input terminal of the optocoupler, and the pull-up resistor is connected to the output terminal of the optocoupler.

[0016] According to a second aspect of this disclosure, a fault detection method for a digital brake valve is provided, the method comprising:

[0017] The digital brake valve is controlled to be in the first working state;

[0018] When the digital brake valve is in its first working state, the level signal information output from the output terminal of the power drive circuit of the digital brake valve is collected.

[0019] Based on the level signal information collected by the monitoring circuit, it is determined whether the digital brake valve has malfunctioned;

[0020] If a fault is detected, the bus current of the power drive circuit is obtained, and the fault type of the digital brake valve is determined based on the bus current and the level signal information.

[0021] Furthermore, determining whether the digital brake valve has malfunctioned based on the level signal information collected by the monitoring circuit includes:

[0022] The power drive circuit acquires the level signal information output from each output terminal; wherein the power drive circuit includes multiple output terminals, and one output terminal is used to control a digital brake valve;

[0023] Based on the level signal information output by each of the output terminals, the faulty digital brake valve is determined among the multiple digital brake valves.

[0024] Furthermore, determining whether the digital brake valve has malfunctioned based on the level signal information collected by the monitoring circuit includes:

[0025] The number of abnormal level detections is determined by collecting the level signal information within a preset time period;

[0026] If the number of abnormal detections exceeds a preset threshold, it is determined that the digital brake valve has malfunctioned.

[0027] Furthermore, if it is determined that the digital brake valve has malfunctioned based on the level signal information, the correlation between the information value of the level signal information and the current value of the bus current is determined;

[0028] Determine the preset fault type that matches the aforementioned association;

[0029] The preset fault type is determined as the fault type of the digital brake valve.

[0030] Furthermore, when the digital brake valve is in its second operating state, pressure data of the digital brake valve is collected.

[0031] Based on the pressure data, determine whether the digital brake valve is experiencing a valve core jamming fault.

[0032] According to a third aspect of this disclosure, an electronic device is provided. The electronic device includes a memory and a processor, wherein the memory stores a computer program, and the processor executes the program to implement the method described above.

[0033] According to a fourth aspect of this disclosure, a computer-readable storage medium is provided having a computer program stored thereon that, when executed by a processor, implements the methods described above.

[0034] The digital brake valve self-test control system provided in this disclosure includes a control circuit, a power drive circuit, a monitoring circuit, and a current sensor. The control circuit and the power drive circuit are connected. The monitoring circuit is located between the power drive circuit and the digital brake valve, and its input terminal is connected to the output terminal of the power drive circuit. The current sensor is connected to both the power drive circuit and the control circuit. The current sensor is used to collect the bus current of the power drive circuit. The monitoring circuit is used to collect the level signal information output by the output terminal of the power drive circuit when the digital brake valve is in a first working state. The control circuit is used to determine whether the digital brake valve has malfunctioned based on the level signal information collected by the monitoring circuit. If a malfunction is determined, the control circuit determines the malfunction type of the digital brake valve based on the bus current and the level signal information. Therefore, this embodiment first determines whether the digital brake valve has malfunctioned through the level signal information collected by the monitoring circuit, and then determines the malfunction type of the digital brake valve through the bus current and the level signal information of the power drive circuit. The circuit structure of this embodiment is simple and highly integrated, and can accurately and reliably obtain the malfunction type of the digital brake valve. Attached Figure Description

[0035] Further details, features, and advantages of this disclosure are disclosed in the following description of exemplary embodiments in conjunction with the accompanying drawings, in which:

[0036] Figure 1 A schematic diagram of the structure of a digital brake valve self-test control system provided as an exemplary embodiment of the present disclosure;

[0037] Figure 2 A schematic diagram of the structure of a digital brake valve self-test control system provided as another exemplary embodiment of this disclosure;

[0038] Figure 3 A schematic diagram of the structure of a monitoring circuit and a power drive circuit provided in an exemplary embodiment of this disclosure;

[0039] Figure 4 A flowchart of a digital brake valve self-test control method provided as an exemplary embodiment of this disclosure;

[0040] Figure 5 A logical diagram of a self-testing procedure provided for an exemplary embodiment of this disclosure;

[0041] Figure 6 A flowchart of a digital brake valve self-test control method provided as another exemplary embodiment of this disclosure;

[0042] Figure 7 A structural block diagram of an electronic device provided as an exemplary embodiment of this disclosure;

[0043] Figure 8A block diagram of a computer system provided for an exemplary embodiment of this disclosure. Detailed Implementation

[0044] Embodiments of this disclosure will now be described in more detail with reference to the accompanying drawings. While some embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be construed as limited to the embodiments set forth herein. Rather, these embodiments are provided to provide a more thorough and complete understanding of this disclosure. It should be understood that the accompanying drawings and embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of protection of this disclosure.

[0045] It should be understood that the steps described in the method embodiments of this disclosure may be performed in different orders and / or in parallel. Furthermore, the method embodiments may include additional steps and / or omit the steps shown. The scope of this disclosure is not limited in this respect.

[0046] The term "comprising" and its variations as used herein are open-ended, meaning "including but not limited to". The term "based on" means "at least partially based on". The term "one embodiment" means "at least one embodiment"; the term "another embodiment" means "at least one additional embodiment"; the term "some embodiments" means "at least some embodiments". Definitions of other terms will be given in the description below. It should be noted that the concepts of "first", "second", etc., used in this disclosure are only used to distinguish different devices, modules, or units, and are not intended to limit the order of functions performed by these devices, modules, or units or their interdependencies.

[0047] It should be noted that the terms "a" and "a plurality of" used in this disclosure are illustrative rather than restrictive, and those skilled in the art should understand that, unless otherwise expressly indicated in the context, they should be understood as "one or more".

[0048] The names of messages or information exchanged between multiple devices in the embodiments of this disclosure are for illustrative purposes only and are not intended to limit the scope of such messages or information.

[0049] It is understood that before using the technical solutions disclosed in the various embodiments of this disclosure, users should be informed of the types, scope of use, and usage scenarios of the personal information involved in this disclosure in an appropriate manner in accordance with relevant laws and regulations, and user authorization should be obtained.

[0050] For example, upon receiving a user's active request, a prompt message is sent to the user to explicitly inform them that the requested operation will require the acquisition and use of the user's personal information. This allows the user to independently choose whether to provide personal information to the software or hardware, such as the electronic device, application, server, or storage medium performing the operations of this disclosed technical solution, based on the prompt message.

[0051] As an optional but non-limiting implementation, in response to a user's active request, sending a prompt message to the user can be done via a pop-up window, where the prompt message can be presented in text format. Furthermore, the pop-up window can also include a selection control allowing the user to choose "agree" or "disagree" to provide personal information to the electronic device. It is understood that the above notification and user authorization process is merely illustrative and does not constitute a limitation on the implementation of this disclosure; other methods that comply with relevant laws and regulations may also be applied to the implementation of this disclosure.

[0052] This disclosure first provides a digital brake valve self-test control system, such as... Figure 1 As shown, the system includes: a control circuit 101, a power drive circuit 102, a monitoring circuit 103, and a current sensor 104; wherein, the control circuit 101 and the power drive circuit 102 are connected, the monitoring circuit 103 is disposed between the power drive circuit 102 and the digital brake valve, and the input terminal of the monitoring circuit 103 is connected to the output terminal of the power drive circuit 102, and the current sensor 104 is connected to both the power drive circuit 102 and the control circuit 101.

[0053] The current sensor 104 is used to collect the bus current of the power drive circuit 102;

[0054] The monitoring circuit 103 is used to collect the level signal information output by the output terminal of the power drive circuit 102 when the digital brake valve is in the first working state.

[0055] The control circuit 101 is used to determine whether the digital brake valve has malfunctioned based on the level signal information collected by the monitoring circuit 103; and if a malfunction is determined, to determine the fault type of the digital brake valve based on the bus current and level signal information.

[0056] In one embodiment, the power drive circuit 102 includes multiple output terminals, wherein one output terminal is used to control a digital brake valve; the monitoring circuit 103 is used to acquire the level signal information output by each output terminal; and the control circuit 101 is used to determine the faulty digital brake valve among the multiple digital brake valves based on the level signal information output by each output terminal.

[0057] In one embodiment, such as Figure 2As shown, the digital brake valve self-test control system also includes a pressure sensor 201; wherein, the pressure sensor 201 is connected to the digital brake valve and the control circuit 101 respectively; the pressure sensor 201 is used to collect the pressure data of the digital brake valve when the digital brake valve is in the second working state; the control circuit 101 determines whether the digital brake valve has a valve core stuck fault type based on the pressure data.

[0058] In one possible embodiment, such as Figure 3 As shown, Figure 3 An exemplary schematic diagram of the monitoring circuit and the power drive circuit is shown. The monitoring circuit 103 includes an input resistor R103, an optocoupler TLP281-1, and a pull-up resistor R98. The input resistor R103 is connected to the input terminal of the optocoupler TLP281-1, and the pull-up resistor R103 is connected to the output terminal of the optocoupler TLP281-1. The input terminal of the optocoupler TLP281-1 is a light-emitting diode (LED). The value of the input-connected resistor R103 needs to be selected based on the input signal value and the circuit power to control the LED. The output terminal of the optocoupler is a phototransistor, and the pull-up resistor R98 at the output terminal is used for current limiting.

[0059] In one possible embodiment, the output circuit of the power drive circuit 102 mainly consists of a MOSFET and a freewheeling diode. The MOSFET used is an AOD2810, which is an 80V N-channel MOSFET that provides the most efficient high-frequency switching performance, minimizing the conduction and switching power losses of the MOSFET. Since the digital brake valve has a large inductance, it will generate a large back electromotive force during high-speed switching. This back electromotive force may damage other devices on the circuit and generate significant electromagnetic interference. In this embodiment, a fast recovery diode FR307 is used as the freewheeling diode to release this back electromotive force.

[0060] In this embodiment, the input terminal of the access resistor R103 is connected to the input terminal of the optocoupler TLP281-1, and the output terminal of the pull-up resistor R103 is connected to the output terminal of the optocoupler TLP281-1. The optocoupler isolates the analog and digital circuits, reducing interference. Simultaneously, the monitoring circuit implements a positive voltage level design for both the input and output terminals of the optocoupler, improving the reliability of the digital brake valve self-test control system. The freewheeling diode uses a fast recovery diode FR307 as a freewheeling diode protection circuit, releasing the back electromotive force, thereby reducing electromagnetic interference and further improving the reliability of the digital brake valve self-test control system provided in this embodiment.

[0061] In one embodiment, such as Figure 4As shown, this embodiment relates to a digital brake valve self-test control method for the digital brake valve self-test control system used in any of the above embodiments. The method includes the following steps:

[0062] Step 401: Control the digital brake valve to the first working state.

[0063] In one possible embodiment, the control circuit drives the digital brake valve with a PWM wave of a first duty cycle. The PWM wave of the first duty cycle has a low duty cycle, which puts the digital brake valve in a first working state. At this time, the digital brake valve does not perform any switching action.

[0064] Step 402: When the digital brake valve is in the first working state, acquire the level signal information output by the output terminal of the power drive circuit of the digital brake valve.

[0065] In one possible embodiment, when the control circuit drives the digital brake valve with a PWM wave of a first duty cycle to put the digital brake valve into a first working state, the monitoring circuit collects the level signal information output by each output terminal of the power drive circuit; wherein, the power drive circuit includes multiple output terminals, and one output terminal is used to control one digital brake valve; based on the level signal information output by each output terminal, the faulty digital brake valve is determined among the multiple digital brake valves.

[0066] Step 403: Based on the level signal information collected by the monitoring circuit, determine whether the digital brake valve has malfunctioned;

[0067] In one possible embodiment, a faulty digital brake valve is determined by a self-test program that collects the level signal information output from each output terminal, such as... Figure 5 As shown, Figure 5 An exemplary logic diagram of the self-test program is shown. First, the GPIO ports of the control circuit corresponding to each output terminal of the monitoring circuit are initialized and a monitoring duration T is set. Then, the level of each GPIO port is monitored. The number of abnormal level detections is determined by the level signal information collected within the preset time T. When an abnormal change occurs in the level of a certain channel, the software in the self-test program module counts and records the number of abnormal level detections. If the number of abnormal detections exceeds a preset threshold N, a fault is determined in the digital brake valve, and a fault flag is set for that channel. After detecting a fault in a certain channel, the control circuit isolates that channel, preventing the control circuit of the faulty channel from outputting PWM.

[0068] Step 404: If a fault is determined to have occurred, the bus current of the power drive circuit is acquired, and the fault type of the digital brake valve is determined based on the bus current and level signal information.

[0069] After identifying the faulty digital brake valve by collecting the level signal information from each output terminal through the self-test program, the bus current of the power drive circuit is obtained, and the fault type of the digital brake valve is determined based on the bus current and the level signal information of the faulty digital brake valve.

[0070] In one possible embodiment, if a fault is determined to have occurred in the digital brake valve based on the level signal information, the correlation between the information value of the level signal information and the current value of the bus current is determined, and a preset fault type matching the correlation is determined.

[0071] When the monitoring circuit receives a fault channel level signal with a low level "0" and the bus current is less than a preset threshold, the matched preset fault type is a digital brake valve coil open circuit; when the monitoring circuit receives a fault channel level signal with a high level "1" and the bus current is greater than a preset threshold, the matched preset fault type is a digital brake valve coil short circuit; when the monitoring circuit receives a fault channel level signal with a high level "1" and the bus current is equal to a preset threshold, the matched preset fault type is a power drive circuit fault.

[0072] After determining the preset fault type that matches the association, the preset fault type is set as the fault type of the digital brake valve.

[0073] The digital brake valve self-test control method provided in this disclosure involves controlling the digital brake valve to a first operating state; when the digital brake valve is in the first operating state, acquiring the level signal information output from the power drive circuit of the digital brake valve; determining whether the digital brake valve has malfunctioned based on the level signal information acquired by the monitoring circuit; if a malfunction is determined, acquiring the bus current of the power drive circuit, and determining the malfunction type of the digital brake valve based on the bus current and the level signal information. Therefore, this embodiment first determines whether the digital brake valve has malfunctioned through the level signal information acquired by the monitoring circuit, and then determines the malfunction type of the digital brake valve through the bus current and the level signal information of the power drive circuit. The circuit structure of this embodiment is simple and highly integrated, and can accurately and reliably obtain the malfunction type of the digital brake valve.

[0074] This disclosure also provides a digital brake valve self-test control method, such as... Figure 6 As shown, the method includes the following steps:

[0075] Step 601: When the digital brake valve is in the second working state, collect the pressure data of the digital brake valve.

[0076] In one possible embodiment, when the electromagnetic brake valve is not malfunctioning, the control circuit drives the digital brake valve with a PWM wave of the second duty cycle. The PWM wave of the second duty cycle has a high duty cycle, which puts the digital brake valve in a second working state. At this time, the digital brake valve performs a switching action, and the pressure sensor acquires the pressure data of the digital brake valve.

[0077] Step 602, based on whether the digital brake valve has a valve core stuck fault type.

[0078] In one possible embodiment, after the pressure sensor acquires the pressure data of the digital brake valve, it determines whether the digital brake valve has a valve core jamming fault type based on the pressure data of the digital brake valve. When the pressure data of the digital brake valve is greater than a preset threshold, the fault type of valve core jamming of the digital brake valve is determined.

[0079] In this embodiment, a pressure sensor acquires pressure data from the digital brake valve, and the pressure data is used to determine whether the digital brake valve has a valve core jamming fault type. The digital brake valve is detected at the mechanical level, which further improves the reliability of the digital brake valve self-test control method.

[0080] This disclosure also provides an electronic device, including: at least one processor; a memory for storing processor-executable instructions; wherein the at least one processor is configured to execute the instructions to implement the methods disclosed in this disclosure.

[0081] Figure 7 This is a schematic diagram of the structure of an electronic device provided as an exemplary embodiment of this disclosure. For example... Figure 7 As shown, the electronic device 700 includes at least one processor 701 and a memory 702 coupled to the processor 701. The processor 701 can perform the corresponding steps in the methods disclosed in the embodiments of this disclosure.

[0082] The processor 701 described above can also be called a central processing unit (CPU), which can be an integrated circuit chip with signal processing capabilities. Each step in the method disclosed in this embodiment can be implemented by the integrated logic circuitry in the processor 701 or by software instructions. The processor 701 can be a general-purpose processor, a digital signal processor (DSP), an ASIC, a field-programmable gate array (FPGA), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components. The general-purpose processor can be a microprocessor or any conventional processor. The steps of the method disclosed in this embodiment can be directly implemented by a hardware decoding processor, or implemented by a combination of hardware and software modules in the decoding processor. The software modules can be located in the memory 702, such as random access memory, flash memory, read-only memory, programmable read-only memory, electrically erasable programmable memory, registers, or other mature storage media in the art. The processor 701 reads information from the memory 702 and, in conjunction with its hardware, completes the steps of the method described above.

[0083] Furthermore, various operations / processes according to this disclosure, implemented via software and / or firmware, can be transmitted from a storage medium or network to a computer system with a dedicated hardware architecture, such as... Figure 8 The computer system 800 shown is equipped with the programs that constitute the software. When various programs are installed, the computer system is able to perform various functions, including those described above. Figure 8 A block diagram of a computer system provided for an exemplary embodiment of this disclosure.

[0084] Computer system 800 is intended to represent various forms of digital electronic computer devices, such as laptop computers, desktop computers, workstations, personal digital assistants, servers, blade servers, mainframe computers, and other suitable computers. Electronic devices may also represent various forms of mobile devices, such as personal digital processors, cellular phones, smartphones, wearable devices, and other similar computing devices. The components shown herein, their connections and relationships, and their functions are merely illustrative and are not intended to limit the implementation of the present disclosure described and / or claimed herein.

[0085] like Figure 8As shown, the computer system 800 includes a computing unit 801, which can perform various appropriate actions and processes based on a computer program stored in a read-only memory (ROM) 802 or a computer program loaded from a storage unit 808 into a random access memory (RAM) 803. The RAM 803 may also store various programs and data required for the operation of the computer system 800. The computing unit 801, ROM 802, and RAM 803 are interconnected via a bus 804. An input / output (I / O) interface 805 is also connected to the bus 804.

[0086] Multiple components in the computer system 800 are connected to the I / O interface 805, including: an input unit 806, an output unit 807, a storage unit 808, and a communication unit 809. The input unit 806 can be any type of device capable of inputting information into the computer system 800. The input unit 806 can receive input numerical or character information and generate key signal inputs related to user settings and / or function control of the electronic device. The output unit 807 can be any type of device capable of presenting information and may include, but is not limited to, a monitor, speaker, video / audio output terminal, vibrator, and / or printer. The storage unit 808 may include, but is not limited to, a hard disk and an optical disk. The communication unit 809 allows the computer system 800 to exchange information / data with other devices via a network such as the Internet, and may include, but is not limited to, a modem, network card, infrared communication device, wireless communication transceiver, and / or chipset, such as Bluetooth™ device, WiFi device, WiMax device, cellular communication device, and / or the like.

[0087] The computing unit 801 can be a variety of general-purpose and / or special-purpose processing components with processing and computing capabilities. Some examples of the computing unit 801 include, but are not limited to, a central processing unit (CPU), a graphics processing unit (GPU), various special-purpose artificial intelligence (AI) computing chips, various computing units running machine learning model algorithms, a digital signal processor (DSP), and any suitable processor, controller, microcontroller, etc. The computing unit 801 performs the various methods and processes described above. For example, in some embodiments, the methods disclosed in this disclosure can be implemented as a computer software program tangibly contained in a machine-readable medium, such as storage unit 808. In some embodiments, part or all of the computer program can be loaded and / or installed on the electronic device 800 via ROM 802 and / or communication unit 809. In some embodiments, the computing unit 801 can be configured to perform the methods disclosed in this disclosure by any other suitable means (e.g., by means of firmware).

[0088] This disclosure also provides a computer-readable storage medium, wherein when the instructions in the computer-readable storage medium are executed by a processor of an electronic device, the electronic device is able to perform the methods disclosed in this disclosure.

[0089] The computer-readable storage medium in this disclosure can be a tangible medium that may contain or store a program for use by or in conjunction with an instruction execution system, apparatus, or device. The aforementioned computer-readable storage medium may include, but is not limited to, electronic, magnetic, optical, electromagnetic, infrared, or semiconductor systems, apparatus, or devices, or any suitable combination of the foregoing. More specifically, the aforementioned computer-readable storage medium may include electrical connections based on one or more wires, a portable computer disk, a hard disk, random access memory (RAM), read-only memory (ROM), erasable programmable read-only memory (EPROM or flash memory), optical fiber, portable compact disk read-only memory (CD-ROM), optical storage devices, magnetic storage devices, or any suitable combination of the foregoing.

[0090] The aforementioned computer-readable medium may be included in the aforementioned electronic device; or it may exist independently and not assembled into the electronic device.

[0091] This disclosure also provides a computer program product, including a computer program, wherein the computer program, when executed by a processor, implements the methods disclosed in the embodiments of this disclosure.

[0092] In embodiments of this disclosure, computer program code for performing the operations of this disclosure can be written in one or more programming languages ​​or a combination thereof. These programming languages ​​include, but are not limited to, object-oriented programming languages ​​such as Java, Smalltalk, and C++, as well as conventional procedural programming languages ​​such as the "C" language or similar programming languages. The program code can be executed entirely on the user's computer, partially on the user's computer, as a standalone software package, partially on the user's computer and partially on a remote computer, or entirely on a remote computer or server. In cases involving remote computers, the remote computer can be connected to the user's computer via any type of network (including a local area network (LAN) or a wide area network (WAN)), or it can be connected to an external computer.

[0093] The flowcharts and block diagrams in the accompanying drawings illustrate the architecture, functionality, and operation of possible implementations of systems, methods, and computer program products according to various embodiments of this disclosure. In this regard, each block in a flowchart or block diagram may represent a module, segment, or portion of code containing one or more executable instructions for implementing a specified logical function. It should also be noted that in some alternative implementations, the functions indicated in the blocks may occur in a different order than those indicated in the drawings. For example, two consecutively indicated blocks may actually be executed substantially in parallel, and they may sometimes be executed in reverse order, depending on the functions involved. It should also be noted that each block in the block diagrams and / or flowcharts, and combinations of blocks in the block diagrams and / or flowcharts, can be implemented using a dedicated hardware-based system that performs the specified function or operation, or using a combination of dedicated hardware and computer instructions.

[0094] The modules, components, or units described in the embodiments of this disclosure can be implemented in software or hardware. The names of the modules, components, or units do not necessarily constitute a limitation on the module, component, or unit itself.

[0095] The functions described above in this document can be performed at least in part by one or more hardware logic components. For example, without limitation, exemplary hardware logic components that can be used include: field-programmable gate arrays (FPGAs), application-specific integrated circuits (ASICs), application-specific standard products (ASSPs), system-on-a-chip (SoCs), complex programmable logic devices (CPLDs), and so on.

[0096] The above description is merely an embodiment of this disclosure and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of this disclosure is not limited to technical solutions formed by specific combinations of the above-described technical features, but should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the above-described concept. For example, technical solutions formed by substituting the above features with (but not limited to) technical features disclosed in this disclosure that have similar functions.

[0097] While specific embodiments of this disclosure have been described in detail by way of example, those skilled in the art should understand that the examples are for illustrative purposes only and not intended to limit the scope of this disclosure. Those skilled in the art should understand that modifications can be made to the above embodiments without departing from the scope and spirit of this disclosure. The scope of this disclosure is defined by the appended claims.

Claims

1. A digital brake valve self-test control system, characterized in that, The system includes: a control circuit, a power drive circuit, a monitoring circuit, and a current sensor; wherein the control circuit and the power drive circuit are connected, the monitoring circuit is disposed between the power drive circuit and the digital brake valve, and the input terminal of the monitoring circuit is connected to the output terminal of the power drive circuit, and the current sensor is connected to both the power drive circuit and the control circuit. The current sensor is used to collect the bus current of the power drive circuit; The monitoring circuit is used to collect the level signal information output by the output terminal of the power drive circuit when the digital brake valve is in the first working state. The control circuit is used to determine whether the digital brake valve has malfunctioned based on the level signal information collected by the monitoring circuit; and if a malfunction is determined, to determine the malfunction type of the digital brake valve based on the bus current and the level signal information.

2. The system according to claim 1, characterized in that, The power drive circuit includes multiple output terminals, one of which is used to control a digital brake valve; The monitoring circuit is used to collect the level signal information output by each of the output terminals; The control circuit is used to determine the faulty digital brake valve among the multiple digital brake valves based on the level signal information output by each of the output terminals.

3. The system according to claim 1, characterized in that, The system further includes a pressure sensor; wherein the pressure sensor is connected to the digital brake valve and the control circuit respectively; The pressure sensor is used to collect pressure data of the digital brake valve when the digital brake valve is in the second working state. The control circuit is used to determine, based on the pressure data, whether the digital brake valve is experiencing a valve core jamming fault.

4. The system according to claim 1, characterized in that, The monitoring circuit includes: an access resistor, an optocoupler, and a pull-up resistor; wherein the access resistor is connected to the input terminal of the optocoupler, and the pull-up resistor is connected to the output terminal of the optocoupler.

5. A self-test control method for a digital brake valve, characterized in that, The method, applied to the digital brake valve self-test control system according to any one of claims 1-4, comprises: The digital brake valve is controlled to be in the first working state; When the digital brake valve is in its first working state, the level signal information output from the output terminal of the power drive circuit of the digital brake valve is collected. Based on the level signal information collected by the monitoring circuit, it is determined whether the digital brake valve has malfunctioned; If a fault is detected, the bus current of the power drive circuit is obtained, and the fault type of the digital brake valve is determined based on the bus current and the level signal information.

6. The method according to claim 5, characterized in that, When the digital brake valve is in its first operating state, the step of acquiring the level signal information output from the power drive circuit of the digital brake valve includes: The power drive circuit acquires the level signal information output from each output terminal; wherein the power drive circuit includes multiple output terminals, and one output terminal is used to control a digital brake valve; Based on the level signal information output by each of the output terminals, the faulty digital brake valve is determined among the multiple digital brake valves.

7. The method according to claim 5, characterized in that, The process of determining whether the digital brake valve has malfunctioned based on the level signal information collected by the monitoring circuit includes: The number of abnormal level detections is determined by collecting the level signal information within a preset time period; If the number of abnormal detections exceeds a preset threshold, it is determined that the digital brake valve has malfunctioned.

8. The method according to claim 5, characterized in that, Determining the fault type of the digital brake valve based on the bus current and the level signal information includes: If it is determined that the digital brake valve has malfunctioned based on the level signal information, the correlation between the information value of the level signal information and the current value of the bus current is determined. Determine the preset fault type that matches the aforementioned association; The preset fault type is determined as the fault type of the digital brake valve.

9. The method according to claim 5, characterized in that, The method further includes: When the digital brake valve is in its second operating state, the pressure data of the digital brake valve is collected. Based on the pressure data, determine whether the digital brake valve is experiencing a valve core jamming fault.

10. A computer-readable storage medium, characterized in that, When the instructions in the computer-readable storage medium are executed by the processor of the electronic device, the electronic device is able to perform the method as described in any one of claims 5-9.

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