A serial signal matrix multiplication operation circuit for Kalman filtering
By designing a serial signal matrix multiplication circuit, the problems of excessive hardware resource consumption and difficulty in matrix multiplication were solved, achieving efficient pipelined output of Kalman filtering results and simplifying the subsequent processing flow.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- HUAZHONG UNIV OF SCI & TECH
- Filing Date
- 2023-09-19
- Publication Date
- 2026-07-07
AI Technical Summary
Existing hardware circuit methods for implementing Kalman filters suffer from excessive hardware resource consumption and difficulties in matrix multiplication operations, especially when the kg and h matrices are reduced to a single serial signal.
A serial signal matrix multiplication circuit was designed, including 2n-1 D flip-flops, 1 logic OR unit, n multiplier units and n processing units. The matrix multiplication operation is completed by stepping in serial signals and within different clock cycles, and the output results are sequential for convenient subsequent processing.
It achieves continuous pipelined output of matrix multiplication results under certain hardware circuit resource consumption, simplifies the subsequent processing of Kalman filter results, and improves computational efficiency.
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Figure CN117349582B_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of Kalman filter algorithm circuit implementation, and more specifically, relates to a serial signal matrix multiplication operation circuit for Kalman filtering. Background Technology
[0002] Kalman filtering plays a crucial role in modern filter algorithms. It combines predicted and measured values of state variables to obtain posterior estimates, with the weights of the predicted and measured values in the posterior estimate being the reciprocals of their covariances. Kalman filters are widely used, frequently employed to obtain state signal values in linear Gaussian noise, facilitating subsequent control algorithms.
[0003] The algorithm for the Kalman filter is shown below:
[0004] x prior =A*x+B*u
[0005] p prior =A*p*A T +Q
[0006] kg = p prior *H T *(h*p prior *h T +R) -1
[0007] x post =x prior +kg*(mh*x prior )
[0008] p post = (I-kg*h)*p prior
[0009] Where, x prior p is the prior estimate. prior Let x be the prior covariance, kg be the Kalman gain, and x be the a priori covariance. post p is the posterior estimate. post For the a posteriori covariance.
[0010] Regarding I-kg*h in the fifth expression, kg is an n*1 matrix, h is a 1*n matrix, and kg*h is an n*n matrix. Currently, there are two main methods for implementing Kalman filters in hardware circuits: one is a fully parallel implementation, where the kg and h matrices are split into n signals. This method consumes excessive hardware resources and port count. The other is based on a systolic array, which uses a pipelined approach to perform large-scale matrix multiplication operations. Compared to the fully parallel method, this increases the clock frequency and reduces port usage, but simplifies the kg and h matrices into a single serial signal, making matrix multiplication between them more difficult. Summary of the Invention
[0011] To address the shortcomings and improvement needs of existing technologies, this invention provides a serial signal matrix multiplication operation circuit for Kalman filtering, which achieves continuous pipeline output of matrix multiplication results with a certain amount of hardware circuit resource consumption, and the order of result output greatly facilitates the processing of subsequent Kalman filtering results.
[0012] To achieve the above objectives, according to a first aspect of the present invention, a serial signal matrix multiplication operation circuit is provided, comprising 2n-1 D flip-flops, 1 logic OR unit, n multiplier units, and n processing units;
[0013] D flip-flops 1 to 1 (n-1) are connected in sequence. The input of D flip-flop 1 receives the serial signal kg, where kg is an n*1 matrix.
[0014] D flip-flops n to D flip-flops 2n-1 are connected in sequence. The input of D flip-flop n receives a serial signal h, where h is a 1*n matrix.
[0015] The input terminal of the logic OR unit receives the serial signal h and the output terminal of the 2n-1 D flip-flop outputs the signal.
[0016] The input terminal of multiplier unit 1 receives the serial signal kg and the output terminal of the logic OR unit outputs the signal;
[0017] The input terminal of multiplier unit i receives the output signal from the output terminal of D flip-flop i-1 and the output signal from the output terminal of the logic OR unit; where i = 2, ..., n;
[0018] The input terminal of each processing unit is connected to the output terminal of the multiplier unit in a one-to-one correspondence;
[0019] Processing unit 1 is used to negate the output signal of multiplier unit 1 and then add 1;
[0020] Processing unit j is used to negate the output signal of multiplier unit j, where j = 2, ..., n.
[0021] Furthermore, in the first clock cycle clk1, the first value kg1 of the serial signal kg and the first value h1 of the serial signal h are input to multiplier unit 1;
[0022] In the second clock cycle clk2, the second value kg2 of the serial signal kg and the second value h2 of the serial signal h are input to multiplier unit 1, and the first value kg1 of the serial signal kg and the second value h2 of the serial signal h are input to multiplier unit 2.
[0023] In the x-th clock cycle clk(x), the x-th value kg(x) of the serial signal kg and the x-th value h(x) of the serial signal h are input to multiplier unit 1, the (x-1)-th value kg(x-1) of the serial signal kg and the x-th value h(x) of the serial signal h are input to multiplier unit 2, ..., the 1-th value kg(1) of the serial signal kg and the x-th value h(x) of the serial signal h are input to multiplier unit x; x = 3, ..., n.
[0024] Furthermore, in the first clock cycle clk1, the output of multiplier unit 1 is kg1*h1;
[0025] In the second clock cycle clk2, the output of multiplier unit 1 is kg2*h2, and the output of multiplier unit 2 is kg1*h2;
[0026] In the x-th clock cycle clk(x), the output of multiplier unit 1 is kg(x)*h(x), the output of multiplier unit 2 is kg(x-1)*h(x), ..., the output of multiplier unit x is kg1*h(x); x = 3, ..., n.
[0027] Furthermore, in the (y+n)th clock cycle clk(y+n), the nth value kg(n) of the serial signal kg and the yth value h(y) of the serial signal h are input to multiplier unit y+1, the (n-1)th value kg(n-1) of the serial signal kg and the yth value h(y) of the serial signal h are input to multiplier unit y+2, ..., the (y+1)th value kg(y+1) of the serial signal kg and the yth value h(y) of the serial signal h are input to multiplier unit n; y = 1, ..., n-3;
[0028] In the 2n-2nd clock cycle clk(2n-2), the nth value kg(n) of the serial signal kg and the (n-2)th value h(n-2) of the serial signal h are input to the multiplier unit n-1, and the (n-1)th value kg(n-1) of the serial signal kg and the (n-2)th value h(n-2) of the serial signal h are input to the multiplier unit n.
[0029] In the 2n-1th clock cycle clk(2n-1), the nth value kg(n) of the serial signal kg and the (n-1)th value h(n-1) of the serial signal h are input to the multiplier unit n.
[0030] Furthermore, in the (y+n)th clock cycle clk(y+n), the output of multiplier unit y+1 is kg(n)*h(y), the output of multiplier unit y+2 is kg(n-1)*h(y), ..., the output of multiplier unit n is kg(y+1)*h(y); y = 1, ..., n-3;
[0031] In the (2n-2)th clock cycle clk(2n-2), the output of multiplier unit n-1 is kg(n)*h(n-2), and the output of multiplier unit n is kg(n-1)*h(n-2);
[0032] In the 2n-1th clock cycle clk(2n-1), the output of multiplier unit n is kg(n)*h(n-1).
[0033] To achieve the above objectives, according to a second aspect of the present invention, an application of the serial signal matrix multiplication circuit as described in the first aspect is provided, wherein the serial signal matrix multiplication circuit is applied to Kalman filtering.
[0034] To achieve the above objectives, according to a third aspect of the present invention, a method for calculating the posterior covariance in Kalman filtering implemented using the serial signal matrix multiplication operation circuit described in the first aspect is provided, comprising the following steps:
[0035] The kth signals output by processing unit 1 to processing unit n are sequentially stored in RAM k, where k = 1, ..., n;
[0036] Then, take all the elements stored in RAMk as the k-th row element of matrix I-kg*h to obtain all the elements of matrix I-kg*H. Multiply these elements by the a priori covariance to obtain the posterior covariance; where I is an n*n identity matrix.
[0037] In summary, the above-described technical solutions conceived in this invention can achieve the following beneficial effects:
[0038] This invention implements a serial signal matrix multiplication circuit using digital circuitry, comprising 2n-1 D flip-flops, one logic OR unit, n multiplier units, and n processing units. The output of multiplier unit 1 is kg1*h1, kg2*h2…kg(n-1)*h(n-1), kg(n)*h(n), which are precisely the diagonal elements of the matrix multiplication result, perfectly suited for subsequent matrix (1-kg*h) operations. Each of the n multiplier units sequentially outputs the elements in the same row of the matrix multiplication result every clock cycle, facilitating subsequent systolic array matrix multiplication processing. This serial signal matrix multiplication circuit achieves continuous pipelined output of matrix multiplication results with minimal hardware resource consumption, and the order of output greatly facilitates the processing of subsequent Karl Filter results. Attached Figure Description
[0039] Figure 1 This is a hardware circuit diagram of the serial signal matrix multiplication operation circuit provided in an embodiment of the present invention;
[0040] Figure 2 This is a timing diagram of the input signals of the multiplier unit of the serial signal matrix multiplication operation circuit provided in this embodiment of the invention;
[0041] Figure 3 This is a timing diagram of the output signal of the multiplier unit of the serial signal matrix multiplication operation circuit provided in this embodiment of the invention. Detailed Implementation
[0042] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention. Furthermore, the technical features involved in the various embodiments of this invention described below can be combined with each other as long as they do not conflict with each other.
[0043] In this invention, the terms "first," "second," etc. (if present) in the invention and the accompanying drawings are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0044] This invention discloses a serial signal matrix multiplication circuit for Kalman filtering. The Kalman filtering algorithm is suitable for filtering linear Gaussian noise signals, obtaining accurate values by combining predicted and measured values. This invention implements a serial signal matrix multiplication circuit using digital circuitry, specifically including 2n-1 D flip-flops, one logic OR unit, n multiplier units, and n processing units. The serial signal matrix multiplication circuit achieves continuous pipelined output of matrix multiplication results with a certain amount of hardware circuit resource consumption, and the order of result output greatly facilitates the processing of subsequent Kalman filtering results. Specifically, this invention applies the serial signal matrix multiplication circuit to the calculation of the posterior covariance p in Kalman filtering. post In this context, it is further specifically applied in calculating the posterior covariance p. post The following describes the invention in further detail with reference to the accompanying drawings and embodiments.
[0045] Figure 1 This is a hardware circuit diagram for serial signal matrix multiplication, which includes D flip-flops 1, ..., D flip-flops n-1, D flip-flops n, D flip-flops n+1, ..., D flip-flops 2n-1, a logic OR unit, multiplier unit 1, multiplier unit 2, ..., multiplier unit n-1, multiplier unit n, processing unit 1, processing unit 2, ..., processing unit n-1, and processing unit n.
[0046] Furthermore, the input of D flip-flop 1 receives the serial signal kg, and the output of D flip-flop 2 is the signal kg_dly1; the input of D flip-flop 2 receives the output signal kg_dly1 of D flip-flop 1, and the output of D flip-flop 2 is the signal kg_dly2; ...; the input of D flip-flop n-1 receives the output signal kg_dly(n-2) of D flip-flop n-2, and the output of D flip-flop 2 is the signal kg_dly(n-1).
[0047] Furthermore, the input of D flip-flop n receives the serial signal h, and the output outputs the signal h_dly1; the input of D flip-flop n+1 receives the output signal h_dly1 of D flip-flop n, and the output outputs the signal h_dly2; ...; the input of D flip-flop 2n-2 receives the output signal h_dly(n-2) of D flip-flop 2n-3, and the output outputs the signal h_dly(n-1); the input of D flip-flop 2n-1 receives the output signal h_dly(n-1) of D flip-flop 2n-2, and the output outputs the signal h_dly(n).
[0048] Furthermore, the input terminal of the OR unit receives the serial input signal h and the output terminal of the D flip-flop 2n-1, which outputs the signal h_dly(n), and the output terminal outputs the signal hor. The input terminal of multiplier unit 1 receives the serial input signal kg and the output terminal of the OR unit, which outputs the signal hor, and the output terminal outputs the signal mul1; the input terminal of multiplier unit 2 receives the output signal kg_dly1 of D flip-flop 1 and the output terminal of the OR unit, which outputs the signal hor, and the output terminal outputs the signal mul2; ...; the input terminal of multiplier unit n-1 receives the output signal kg_dly(n-2) of D flip-flop n-2 and the output terminal of the OR unit, which outputs the signal hor, and the output terminal outputs the signal mul(n-1); the input terminal of multiplier unit n receives the output signal kg_dly(n-1) of D flip-flop n-1 and the output terminal of the OR unit, which outputs the signal hor, and the output terminal outputs the signal mul(n).
[0049] Furthermore, the input terminal of processing unit 1 receives the output signal mul1 from the output terminal of multiplier unit 1, and the output terminal outputs the signal -mul1+1; the input terminal of processing unit 2 receives the output signal mul2 from the output terminal of multiplier unit 2, and the output terminal outputs the signal -mul2; ...; the input terminal of processing unit n-1 receives the output signal mul(n-1) from the output terminal of multiplier unit n-1, and the output terminal outputs the signal -mul(n-1); the input terminal of processing unit n receives the output signal mul(n) from the output terminal of multiplier unit n, and the output terminal outputs the signal -mul(n).
[0050] Figure 2This is the timing diagram of the input signals of the multiplier unit in a serial signal matrix multiplication circuit. During the first clock cycle, clk1, the first value of serial signal kg (kg1) and the first value of serial signal h (h1) are input to multiplier unit 1. During clk2, the second value of serial signal kg (kg2) and the second value of serial signal h (h2) are input to multiplier unit 1, and the first value of serial signal kg (kg1) and the second value of serial signal h (h2) are input to multiplier unit 2. ... During clk(n), the nth value of serial signal kg (kg(n)) and the nth value of serial signal h (h(n)) are input to multiplier unit 1, the (n-1)th value of serial signal kg (kg(n-1)) and the nth value of serial signal h (h(n)) are input to multiplier unit 2, ..., the second value of serial signal kg (kg2) and the nth value of serial signal h (h(n)) are input to multiplier unit n-1, and the first value of serial signal kg (kg1) and the nth value of serial signal h (h(n)) are input to multiplier unit n. At time clk(n+1), the nth value kg(n) of the serial signal kg and the first value h1 of the serial signal h are input to multiplier unit 2, ..., the third value kg3 of the serial signal kg and the first value h1 of the serial signal h are input to multiplier unit n-1, and the second value kg2 of the serial signal kg and the first value h1 of the serial signal h are input to multiplier unit n. At time clk(n+2), ..., the fourth value kg4 of the serial signal kg and the second value h2 of the serial signal h are input to multiplier unit n-1, and the third value kg3 of the serial signal kg and the second value h2 of the serial signal h are input to multiplier unit n. ... At time clk(2n-1), the nth value kg(n) of the serial signal kg and the (n-1)th value h(n-1) of the serial signal h are input to multiplier unit n.
[0051] Figure 3This is the timing diagram of the output signals of the multiplier units in a serial signal matrix multiplication circuit. At time clk1, the output result mul1 of multiplier unit 1 is kg1*h1. At time clk2, the output result mul1 of multiplier unit 1 is kg2*h2, and the output result mul2 of multiplier unit 2 is kg1*h2. ... At time clk(n), the output result mul1 of multiplier unit 1 is kg(n)*h(n), the output result mul2 of multiplier unit 2 is kg(n-1)*h(n), ..., the output result mul(n-1) of multiplier unit n is kg2*h(n), and the output result mul(n) of multiplier unit n is kg1*h(n). At time clk(n+1), the output of multiplier unit 2, mul2, is kg(n)*h1, ..., the output of multiplier unit n-1, mul(n-1), is kg3*h1, and the output of multiplier unit n, mul(n), is kg2*h1. At time clk(n+2), ..., the output of multiplier unit n-1, mul(n-1), is kg4*h2, and the output of multiplier unit n, mul(n), is kg3*h2, ... At time clk(2n-1), the output of multiplier unit n, mul(n), is kg(n)*h(n-1).
[0052] Furthermore, during the time intervals clk1 to clk(n), the outputs mul1 of multiplier unit 1 are kg1*h1, kg2*h2, ..., kg(n-1)*h(n-1), and kg(n)*h(n), which correspond exactly to the diagonal elements of the matrix multiplication results. This facilitates the understanding of the posterior covariance p in the Kalman filtering algorithm. post The calculation of I-kg*h in the equation is performed. The elements of each row of the multiplication result matrix of the n multiplier units' output matrix are used to represent the posterior covariance p in the Kalman filter algorithm. post In the calculation equation (I-kg*h)*p prior Calculation of pulsating array.
[0053] Specifically, a method for calculating the posterior covariance in Kalman filtering implemented using the aforementioned serial signal matrix multiplication circuit includes the following steps:
[0054] The kth signals output by processing unit 1 to processing unit n are sequentially stored in RAM k, where k = 1, ..., n;
[0055] Then, take all the elements stored in RAMk as the k-th row element of matrix I-kg*h to obtain all the elements of matrix I-kg*h. Then multiply them by the a priori covariance to obtain the posterior covariance; where I is an n*n identity matrix.
[0056] Those skilled in the art will readily understand that the above description is merely a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, and improvements made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.
Claims
1. A serial signal matrix multiplication circuit, characterized in that, It includes 2n-1 D flip-flops, 1 logic OR unit, n multiplier units, and n processing units; D flip-flops 1 to 1 (n-1) are connected in sequence. The input of D flip-flop 1 receives the serial signal kg, where kg is an n*1 matrix. D flip-flops n to D flip-flops 2n-1 are connected in sequence. The input of D flip-flop n receives a serial signal h, where h is a 1*n matrix. The input terminal of the logic OR unit receives the serial signal h and the output terminal of the 2n-1 D flip-flop outputs the signal. The input terminal of multiplier unit 1 receives the serial signal kg and the output terminal of the logic OR unit outputs the signal; The input terminal of multiplier unit i receives the output signal from the output terminal of D flip-flop i-1 and the output signal from the output terminal of the logic OR unit; where i = 2, ..., n; The input terminal of each processing unit is connected to the output terminal of the multiplier unit in a one-to-one correspondence; Processing unit 1 is used to negate the output signal of multiplier unit 1 and then add 1; Processing unit j is used to negate the output signal of multiplier unit j, where j = 2, ..., n.
2. The serial signal matrix multiplication circuit according to claim 1, characterized in that, In the first clock cycle clk1, the first value kg1 of the serial signal kg and the first value h1 of the serial signal h are input to multiplier unit 1; In the second clock cycle clk2, the second value kg2 of the serial signal kg and the second value h2 of the serial signal h are input to multiplier unit 1, and the first value kg1 of the serial signal kg and the second value h2 of the serial signal h are input to multiplier unit 2. In the x-th clock cycle clk(x), the x-th value kg(x) of the serial signal kg and the x-th value h(x) of the serial signal h are input to multiplier unit 1, the (x-1)-th value kg(x-1) of the serial signal kg and the x-th value h(x) of the serial signal h are input to multiplier unit 2, ..., the 1-th value kg(1) of the serial signal kg and the x-th value h(x) of the serial signal h are input to multiplier unit x; x = 3, ..., n.
3. The serial signal matrix multiplication circuit according to claim 2, characterized in that, In the first clock cycle clk1, the output of multiplier unit 1 is kg1*h1; In the second clock cycle clk2, the output of multiplier unit 1 is kg2*h2, and the output of multiplier unit 2 is kg1*h2; In the x-th clock cycle clk(x), the output of multiplier unit 1 is kg(x)*h(x), the output of multiplier unit 2 is kg(x-1)*h(x), ..., the output of multiplier unit x is kg1*h(x); x = 3, ..., n.
4. The serial signal matrix multiplication circuit according to claim 1, characterized in that, In the (y+n)th clock cycle clk(y+n), the nth value kg(n) of the serial signal kg and the yth value h(y) of the serial signal h are input to multiplier unit y+1, the (n-1)th value kg(n-1) of the serial signal kg and the yth value h(y) of the serial signal h are input to multiplier unit y+2, ..., the (y+1)th value kg(y+1) of the serial signal kg and the yth value h(y) of the serial signal h are input to multiplier unit n; y = 1, ..., n-3; In the 2n-2nd clock cycle clk(2n-2), the nth value kg(n) of the serial signal kg and the (n-2)th value h(n-2) of the serial signal h are input to the multiplier unit n-1, and the (n-1)th value kg(n-1) of the serial signal kg and the (n-2)th value h(n-2) of the serial signal h are input to the multiplier unit n. In the 2n-1th clock cycle clk(2n-1), the nth value kg(n) of the serial signal kg and the (n-1)th value h(n-1) of the serial signal h are input to the multiplier unit n.
5. The serial signal matrix multiplication circuit according to claim 4, characterized in that, In the (y+n)th clock cycle clk(y+n), the output of multiplier unit y+1 is kg(n)*h(y), the output of multiplier unit y+2 is kg(n-1)*h(y), ..., the output of multiplier unit n is kg(y+1)*h(y); y = 1, ..., n-3; In the (2n-2)th clock cycle clk(2n-2), the output of multiplier unit n-1 is kg(n)*h(n-2), and the output of multiplier unit n is kg(n-1)*h(n-2); In the 2n-1th clock cycle clk(2n-1), the output of multiplier unit n is kg(n)*h(n-1).
6. An application of the serial signal matrix multiplication circuit as described in any one of claims 1 to 5, characterized in that, The serial signal matrix multiplication circuit is applied to Kalman filtering.
7. A method for calculating the posterior covariance in Kalman filtering using the serial signal matrix multiplication operation circuit described in any one of claims 1 to 5, characterized in that, Includes the following steps: The kth signals output by processing unit 1 to processing unit n are sequentially stored in RAM k, where k = 1, ..., n; Then, take all the elements stored in RAMk as the k-th row element of matrix I-kg*h to obtain all the elements of matrix I-kg*H. Multiply these elements by the a priori covariance to obtain the posterior covariance; where I is an n*n identity matrix.