Data receiving circuit and memory

Abstract

Embodiments of the present disclosure relate to the field of semiconductor circuit design and provide a data receiving circuit and a memory. The data receiving circuit includes: a comparison circuit configured to amplify the voltage difference between input data and an initial reference voltage and output a two-end signal as the amplification result; multiple data paths, each of which receives a two-end signal, wherein the i-th data path is configured to sample based on the i-th clock to obtain the i-th bit of data, and the i-th data path includes: an adjustment circuit configured to adjust the voltage difference between the two-end signals based on the previous 2-bit data to the previous N-bit data to generate a two-end adjustment signal; and a sampling circuit configured to compare and amplify the voltage difference between the two-end adjustment signals based on the previous 1-bit data during the effective period of the i-th clock, and output the i-th bit of data.

Description

Technical Field

[0001] The embodiments of the present disclosure relate to the field of semiconductor circuit design, and in particular to a data receiving circuit and a memory. Background Art

[0002] As signal transmission rates become faster and clock frequencies increase, input data channel loss has a greater impact on signal quality, making it more likely that intersymbol interference (ISI) will occur during memory signal transmission.

[0003] ISI refers to a phenomenon in which previously transmitted input data affects the transmission of currently transmitted input data due to bandwidth limitations of the input data channel. Currently, feedback equalization circuits are commonly used to compensate for the input data channel to reduce the adverse effects of intersymbol interference (ISI). These circuits can be CTLE (Continuous Time Linear Equalizer) or DFE (Decision Feedback Equalizer).

[0004] However, the effect of current storage devices in improving intersymbol interference still needs to be improved. Summary of the Invention

[0005] The embodiments of the present disclosure provide a data receiving circuit and a memory, which are at least beneficial to improving the inter-symbol interference problem of the memory.

[0006] An embodiment of the present disclosure provides a data receiving circuit, comprising: a comparison circuit, receiving initial input data and an initial reference voltage, configured to amplify a voltage difference between the input data and the initial reference voltage, and output a two-terminal signal as a result of the amplification; a plurality of data paths, comprising: a first data path to an Mth data path numbered in ascending order of natural numbers, the i-th data path being any one of the plurality of data paths, 1≤i≤M, M≥2; each data path receiving a two-terminal signal, wherein the i-th data path is configured to sample based on an i-th clock to obtain Taking the i-th bit of data, the i-th data path includes: an adjustment circuit, which receives the second bit of data before the i-th bit of data to the N-th bit of data, 2≤N≤M, and is configured to adjust the voltage difference between the two-end signals based on the second bit of data to the N-th bit of data to generate a two-end adjustment signal; a sampling circuit, which receives the two-end adjustment signal, the i-th clock and the first bit of data before the i-th bit of data, and is configured to compare and amplify the voltage difference between the two-end adjustment signals based on the first bit of data during the effective period of the i-th clock, and output the i-th bit of data.

[0007] The data receiving circuit adjusts the current input data based on the feedback of the previous multi-bit input data, which greatly reduces the impact of ISI on the current input data. The circuit area is relatively compressed as much as possible and does not affect the storage capacity of the memory.

[0008] In some embodiments, the sampling circuit also receives a first reference voltage and a second reference voltage, wherein the voltage value of the first reference voltage is greater than the voltage value of the second reference voltage; based on the previous first bit data, the voltage difference between the two-end adjustment signals is compared and amplified, and the i-th bit data is output, including: based on the previous first bit data, selecting to adjust the voltage value of the i-th bit data by the voltage difference between the first reference voltage and the second reference voltage to equivalently increase or equivalently decrease the voltage difference between the two-end adjustment signals, and comparing and amplifying the voltage difference between the two-end adjustment signals to output the i-th bit data.

[0009] In some embodiments, the two-end regulation signal includes a first regulation sub-signal and a second regulation sub-signal, and the sampling circuit includes: a selection adjustment circuit, configured to, during the valid period of the i-th clock, based on the value of the previous 1st bit data, select to adjust the branch current of the branch where the first regulation sub-signal is located through the first reference voltage, and adjust the branch current of the branch where the second regulation sub-signal is located through the second reference voltage; or, adjust the branch current of the branch where the second regulation sub-signal is located through the first reference voltage, and adjust the branch current of the branch where the first regulation sub-signal is located through the second reference voltage; a latch circuit, configured to sample and latch the i-th bit data based on the i-th clock.

[0010] In some embodiments, the selection and adjustment circuit includes: a first NMOS transistor, a control end for receiving a first adjustment sub-signal, and a first end connected to a latch circuit; a second NMOS transistor, a control end for receiving a second adjustment sub-signal, a first end connected to the latch circuit, and a second end connected to the second end of the first NMOS transistor; a first switch NMOS transistor, a control end for receiving a power supply voltage, and a first end connected to the second end of the first NMOS transistor; a second switch NMOS transistor, a control end for receiving an i-th clock, a first end connected to the second end of the first switch NMOS transistor, and a second end grounded; a first adjustment NMOS transistor, a control end for receiving a first reference voltage, and a first end connected to the first end of the second NMOS transistor; a second adjustment NMOS transistor, a control end for receiving a second reference voltage, a first end connected to the first end of the first NMOS transistor, and a second end connected to the second end of the first adjustment NMOS transistor; A third switch NMOS transistor, whose control end is used to receive the first bit of data before, and whose first end is connected to the second end of the second adjustment NMOS transistor; a fourth switch NMOS transistor, whose control end is used to receive the i-th clock, whose first end is connected to the second end of the third switch NMOS transistor, and whose second end is grounded; a third adjustment NMOS transistor, whose control end is used to receive the second reference voltage, whose first end is connected to the first end of the second NMOS transistor; a fourth adjustment NMOS transistor, whose control end is used to receive the first reference voltage, whose first end is connected to the first end of the first NMOS transistor, and whose second end is connected to the second end of the third adjustment NMOS transistor; a fifth switch NMOS transistor, whose control end is used to receive the inverted signal of the first bit of data before, and whose first end is connected to the second end of the fourth adjustment NMOS transistor; a sixth switch NMOS transistor, whose control end is used to receive the i-th clock, whose first end is connected to the second end of the fifth switch NMOS transistor, and whose second end is grounded.

[0011] In some embodiments, the latch circuit includes: a first PMOS transistor, a first end for receiving a power supply voltage; a second PMOS transistor, a first end for receiving a power supply voltage; a third NMOS transistor, a control end connected to the control end of the first PMOS transistor, a first end connected to the second end of the first PMOS transistor, and a second end connected to the first end of the first NMOS transistor; a fourth NMOS transistor, a control end connected to the control end of the second PMOS transistor, a first end connected to the second end of the second PMOS transistor, and a second end connected to the second end of the second NMOS transistor; the control end of the third NMOS transistor is also connected to the first end of the fourth NMOS transistor to serve as a first output end of the latch circuit, the control end of the fourth NMOS transistor is also connected to the first end of the third NMOS transistor to serve as a second output end of the latch circuit, the first output end is used to output an i-th bit of data, and the second output end is used to output an inverted signal of the i-th bit of data; a first reset PMOS transistor, a control end for receiving an i-th clock, a first end for receiving a power supply voltage, and a second end connected to the second end of the first PMOS transistor; a second reset PMOS transistor, a control end for receiving an i-th clock, a first end for receiving a power supply voltage, and a second end connected to the second end of the second PMOS transistor.

[0012] In some embodiments, the latch circuit further includes: a third reset PMOS transistor, whose control end is used to receive the i-th clock, the first end is used to receive the power supply voltage, and the second end is connected to the first end of the first NMOS transistor; a fourth reset PMOS transistor, whose control end is used to receive the i-th clock, the first end is used to receive the power supply voltage, and the second end is connected to the second end of the second NMOS transistor.

[0013] In some embodiments, the data receiving circuit also includes: a code generation circuit, configured to receive a reference voltage generation code and a tap code corresponding to the first bit of data, generate a first reference voltage generation code based on the reference voltage generation code + the tap code, and generate a second reference voltage generation code based on the reference voltage generation code - the tap code; wherein the first reference voltage generation code is used to generate a first reference voltage, the second reference voltage generation code is used to generate a second reference voltage, and the tap code is used to match the voltage adjustment step corresponding to the first bit of data.

[0014] In some embodiments, the data receiving circuit further includes: a resistor voltage divider circuit configured to generate a first reference voltage based on a first reference voltage generation code, and to generate a second reference voltage based on a second reference voltage generation code.

[0015] In some embodiments, the code generation circuit includes: a generating circuit configured to generate an initial reference voltage generation code; a control circuit configured to provide a tap code to a first processing circuit and a second processing circuit; the first processing circuit is configured to generate a first reference voltage generation code based on the initial reference voltage generation code + the tap code; the second processing circuit is configured to generate a second reference voltage generation code based on the initial reference voltage generation code - the tap code.

[0016] In some embodiments, the generation circuit is configured to generate a reference voltage generation code corresponding to a preset reference voltage, or to identify a configuration value of a mode register in a corresponding memory to generate an initial reference voltage generation code. In some embodiments, the generation circuit includes: a first sub-generation circuit configured to identify a configuration value of a mode register in a corresponding memory to generate a first reference code; a second sub-generation circuit configured to generate a second reference code corresponding to a preset reference voltage; and a selection circuit configured to select, based on a selection signal, either the first reference code or the second reference code to generate the initial reference voltage generation code.

[0017] In some embodiments, the generating circuit is configured to generate an initial reference voltage generation code based on a debugging code, wherein the debugging code is based on eye diagram data acquired from the memory in a test mode.

[0018] In some embodiments, the generating circuit includes: a first sub-generating circuit, configured to identify the configuration value of the mode register in the memory to which it belongs to generate a first reference code; a second sub-generating circuit, configured to generate a second reference code based on the debug code; and a selecting circuit, configured to select, based on a selecting signal, to generate a reference voltage generating code based on the first reference code or the second reference code.

[0019] Another embodiment of the present disclosure provides a memory, including the data receiving circuit provided by the above embodiment, which is at least beneficial to improving the inter-symbol interference problem of the memory.

[0020] In some embodiments, N and M are 4. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] One or more embodiments are exemplarily illustrated by pictures in the corresponding drawings. These exemplifications do not constitute a limitation on the embodiments. Elements with the same reference numerals in the drawings are represented as similar elements. Unless otherwise stated, the figures in the drawings do not constitute a scale limitation. In order to more clearly illustrate the embodiments of the present disclosure or the technical solutions in the traditional technology, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 A schematic structural diagram of a data receiving circuit for performing compensation based on dual reference voltages according to an embodiment of the present disclosure;

[0023] Figure 2 A schematic structural diagram of a data receiving circuit provided in one embodiment of the present disclosure;

[0024] Figure 3 A schematic diagram of a structure with multiple comparison circuits provided in one embodiment of the present disclosure;

[0025] Figure 4 A schematic diagram of the structure of a comparison circuit provided in one embodiment of the present disclosure;

[0026] Figure 5 A schematic structural diagram of an adjustment circuit provided in one embodiment of the present disclosure;

[0027] Figure 6 A schematic structural diagram of a data receiving circuit for adjusting output data based on dual reference voltages provided by an embodiment of the present disclosure;

[0028] Figure 7 An embodiment of the present disclosure provides Figure 6 A schematic diagram of the structure of the sampling circuit in the data receiving circuit shown;

[0029] Figure 8 A schematic diagram of the structure of a code generation circuit and a resistor voltage divider circuit provided in one embodiment of the present disclosure;

[0030] Figure 9 A schematic structural diagram of a first code generation circuit provided in one embodiment of the present disclosure;

[0031] Figure 10 A schematic structural diagram of a second code generation circuit provided in one embodiment of the present disclosure;

[0032] Figure 11 A schematic structural diagram of a third code generation circuit provided in an embodiment of the present disclosure;

[0033] Figure 12 This is a schematic structural diagram of a fourth code generation circuit provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0034] As can be seen from the background art, the effect of current storage devices in improving inter-symbol interference still needs to be improved.

[0035] An embodiment of the present disclosure provides a data receiving circuit, which is at least beneficial for improving the inter-symbol interference problem of a memory.

[0036] Those skilled in the art will appreciate that many technical details are provided in the various embodiments of the present disclosure to facilitate a better understanding of the present disclosure. However, even without these technical details and the various variations and modifications based on the following embodiments, the technical solutions claimed in the present disclosure can be implemented. The division of the following embodiments is for ease of description and should not constitute any limitation on the specific implementation of the present disclosure. The various embodiments may be combined and referenced with each other as long as there is no contradiction.

[0037] Figure 1 This is a schematic diagram of the structure of a data receiving circuit based on dual reference voltage compensation provided by this embodiment. Figure 2 This is a schematic diagram of the structure of the data receiving circuit provided in this embodiment. Figure 3 A schematic diagram of a structure with multiple comparison circuits provided in this embodiment, Figure 4 This is a schematic diagram of the structure of the comparison circuit provided in this embodiment, Figure 5 This is a schematic diagram of the structure of the adjustment circuit provided in this embodiment, Figure 6 This is a structural diagram of a data receiving circuit based on dual reference voltage adjustment output data provided by this embodiment. Figure 7 Provided for this embodiment Figure 6 The structural diagram of the sampling circuit in the data receiving circuit is shown in FIG. Figure 8 This is a schematic diagram of the structure of the code generation circuit and the resistor voltage divider circuit provided in this embodiment. Figure 9 This is a schematic diagram of the structure of the first code generation circuit provided in this embodiment. Figure 10 This is a schematic diagram of the structure of the second code generation circuit provided in this embodiment. Figure 11 This is a schematic diagram of the structure of the third code generation circuit provided in this embodiment. Figure 12 This is a schematic diagram of the structure of the fourth code generation circuit provided in this embodiment. The data receiving circuit provided in this embodiment is described in detail below with reference to the accompanying drawings, as follows:

[0038] The data receiving circuit can be applied to a memory, which can be a DRAM (Dynamic Random Access Memory) or an SRAM (Static Random Access Memory). In some embodiments, the data receiving circuit can be applied to an SDRAM (Synchronous Dynamic Random Access Memory), which can be a DDR (Double Data Rate) SDRAM, such as a DDR4 memory, a DDR5 memory, a DDR6 memory, a LPDDR4 memory, a LPDDR5 memory, or a LPDDR6 memory.

[0039] Depending on the number of bits of previously transmitted input data participating in the DFE, the feedback equalization circuit in the data receiving circuit can be divided into 1-tap, 2-tap, 3-tap, and 4-tap equalization circuits. In specific applications, the feedback equalization circuit can even have more taps (i.e., the number of taps can be greater than 4). A tap is a tap, and it can be understood that the feedback equalization circuit can include multiple tap adjustment circuits, each of which corresponds to a tap signal. A tap signal corresponds to a previously transmitted 1-bit input data, thereby adjusting the currently transmitted input data according to the tap signal. Specifically, a 1-tap equalization circuit adjusts the current input data based on the first 1-bit of previously transmitted input data, a 2-tap equalization circuit adjusts the current input data based on the first 2-bits of previously transmitted input data, and an n-tap equalization circuit adjusts the current input data based on the first n-bits of previously transmitted input data.

[0040] Since a four-phase clock is commonly used for data transmission in DDR5, in this embodiment, the data receiving circuit provided by this embodiment is described using an example of a 4-tap equalization circuit, which does not constitute a limitation of this embodiment. In other embodiments, the 4-tap equalization circuit can be expanded to an n-tap equalization circuit.

[0041] For the four-phase clock signal, the clock signals are CLK-0, CLK-90, CLK-180 and CLK-270, wherein the clock signal CLK-0 is used to sample and obtain the input data DQ-0. The input data previously transmitted by the input data DQ-0 are: DQ-270, DQ-180, DQ-90, DQ-0, DQ-270... The clock signal CLK-90 is used to sample and obtain the input data DQ-90. The input data previously transmitted by the input data DQ-90 are: DQ-0, DQ-270, DQ-180, DQ-90, DQ-0, DQ-270... 0, DQ-180, DQ-90, DQ-0... The clock signal CLK-180 is used to sample and obtain input data DQ-180. The input data previously transmitted by input data DQ-180 is: DQ-90, DQ-0, DQ-270, DQ-180, DQ-90... The clock signal CLK-270 is used to sample and obtain input data DQ-270. The input data previously transmitted by input data DQ-270 is: DQ-180, DQ-90, DQ-0, DQ-270, DQ-180...

[0042] The operating principle of the decision feedback equalizer (DFE) circuit can be simply understood as adjusting the reference voltage to avoid sampling errors in the data receiving circuit. Because changes in the external input data do not cause instantaneous changes in the level of the data receiving circuit (it takes time for the level change in the data receiving circuit to translate into data changes), increasing the data transmission rate or the clock signal frequency will reduce the level change time in the data receiving circuit. For example, when the external input data jumps from "0" to "1", due to the reduced change time of the level in the data receiving circuit, the level in the data receiving circuit needs to be pulled up to 0.8 under ideal conditions, but can actually only be pulled up to 0.6. At this time, by lowering the reference voltage to ensure that the actual level 0.6 is still greater than the reference voltage, the data receiving circuit can sample and obtain high-level input data; for another example, when the external input data jumps from "1" to "0", due to the reduced change time of the level in the data receiving circuit, the level in the data receiving circuit needs to be pulled down to 0.1 under ideal conditions, but can actually only be pulled down to 0.3. At this time, by increasing the reference voltage to ensure that the actual level 0.3 is still less than the reference voltage, the data receiving circuit can sample and obtain low-level input data.

[0043] In some embodiments, reference Figure 1The data receiving circuit includes a comparison circuit 10 and four data paths 20. The four data paths 20 are respectively used to sample initial input data DQ to obtain input data DQ-0, DQ-90, DQ-180, and DQ-270 (the phase difference between DQ-0 and DQ-90 is 90°, the phase difference between DQ-90 and DQ-180 is 90°, the phase difference between DQ-180 and DQ-270 is 90°, and the phase difference between DQ-270 and DQ-0 is 90°). The following description takes the data path for obtaining input data DQ-0 as an example for explanation. Those skilled in the art can replace the corresponding signals to obtain specific implementation methods of other data paths, which will not be repeated in this embodiment.

[0044] Specifically, the comparison circuit 10 is used to receive initial input data DQ and a reference voltage Vref_ADD / Vref_SUB input from the external input, and amplify the voltage difference between the initial input data DQ and the reference voltage Vref_ADD / Vref_SUB to generate a two-port signal SS1 / SS2. The two-port signal SS1 / SS2 is input to the data path 20. The data path 20 includes an adjustment circuit 21 and a sampling circuit 22. The adjustment circuit 21 is used to fine-tune the two-port signal SS1 / SS2 according to the second bit data previously transmitted and the input data previously transmitted to output two-port adjusted data SS3 / SS4. The sampling circuit 22 samples the two-port adjusted data SS3 / SS4 based on the clock signal CLK-0 to generate alternative data DQ-0-ADD / DQ-0-SUB. Then, the selector 30 selects the alternative data DQ-0-ADD or the alternative data DQ-0-SUB based on the previous first bit data DQ-270 to obtain the input data DQ-0.

[0045] More specifically, the alternative data DQ-0-ADD is generated based on the reference voltage Vref-ADD, and the alternative data DQ-0-SUB is generated based on the reference voltage Vref-SUB. The selector 30 selects different alternative data DQ-0-ADD / DQ-0-SUB based on the previous 1st bit data DQ-270 to obtain the input data DQ-0, that is, selects the sampling result based on the reference voltage Vref-ADD or the reference voltage Vref-SUB.

[0046] for Figure 1For the example data receiving circuit 10, the data receiving circuit adjusts the current input data based on the feedback of the previous multi-bit input data, which greatly reduces the impact of ISI on the current input data. However, the circuit area may be large, and in practical applications, it may occupy a large memory layout, which may affect the storage capacity of the memory. In addition, the data receiving circuit 10 samples the same input data twice based on the reference voltage Vref_ADD / Vref_SUB, resulting in high power consumption of the circuit.

[0047] In some embodiments, reference Figure 2 , the data receiving circuit includes a comparison circuit 101 and multiple data paths 102 .

[0048] The comparison circuit 101 is used to receive initial input data DQ and an initial reference voltage Vref. The comparison circuit 101 is configured to amplify the voltage difference between the initial input data DQ and the initial reference voltage Vref and output a dual-terminal signal SS1 / SS2 as the amplified result.

[0049] Regarding the amplification principle of the comparison circuit 101, in one example, refer to Figure 4 The comparison circuit 101 includes an equalization circuit 110 and a first amplifier circuit 120. The equalization circuit 110 is configured to compare the voltage difference between the initial input data DQ and the initial reference voltage Vref to increase the high-frequency gain of the initial input data DQ and output the initial differential signal pair OUT1_N / OUT1_P. The first amplifier circuit 120 is configured to amplify the voltage difference between the initial differential signal pair OUT1_N / OUT1_P and output the two-terminal signal SS1 / SS2; wherein the two-terminal signal SS1 / SS2 includes a first two-terminal signal SS1 and a second two-terminal signal SS2. It should be noted that Figure 4 The example comparison circuit 101 includes only two-stage amplification circuits (the equalization circuit 110 can also be regarded as a single-stage amplification circuit). In other embodiments, a multi-stage amplification circuit can be further connected to the input or output end of the first amplification circuit 120 to further amplify the voltage difference between the two-end signals SS1 / SS2. Through multi-stage amplification, the influence of other factors on the transmission accuracy of the initial input data DQ can be reduced or avoided.

[0050] In one example, the equalization circuit 110 includes resistors R1, R2, and R3, NMOS transistors MN1 and MN2, an equalization capacitor C, and current sources I1 and I2. Specifically, the drain of MN1 serves as a node net1 and is connected to one terminal of R1. The other terminal of R1 is used to receive a power supply voltage VDD. The source of MN1 is connected to a first terminal of I1, the second terminal of I1 is grounded, and the gate of MN1 is used to receive an initial reference voltage Vref. The drain of MN2 serves as a node net2 and is connected to one terminal of R2. The other terminal of R2 is used to receive the power supply voltage VDD. The source of MN2 is connected to a first terminal of I2, the second terminal of I2 is grounded, and the gate of MN2 is used to receive an initial input signal DQ. R3 and C are connected in parallel to the source terminals of MN1 and MN2. The parallel connection of R3 and C can provide a zero point at high frequencies for the high-frequency circuit, resulting in a boosted frequency spectrum of the equalization circuit 110 at high frequencies, thereby increasing the high-frequency gain and offsetting the frequency loss introduced in the data receiving channel.

[0051] The equalization circuit 110 can compensate the original input signal DQ in a continuous time to compensate for the frequency loss of the original input signal. In some embodiments, the equalization circuit 110 can also include a continuous time linear equalizer (CTLE). Continuous time linear equalization refers to compensating for lossy signals in a continuous time.

[0052] Regarding the input-output relationship of the equalizer circuit 110, when the voltage of the initial input signal DQ is greater than the voltage of the initial reference voltage Vref, the degree of on-state of MN2 is greater than the degree of on-state of MN1, and the node voltage of net2 decreases faster than the node voltage of net1, resulting in an output voltage OUT1_N of net2 being smaller than the output voltage OUT1_P of net1. When the voltage of the initial input signal DQ is less than the voltage of the initial reference voltage Vref, the degree of on-state of MN1 is greater than the degree of on-state of MN2, and the node voltage of net1 decreases faster than the node voltage of net2, resulting in an output voltage OUT1_P of net1 being smaller than the output voltage OUT1_N of net2.

[0053] In one example, the first amplifier circuit 120 may be a current-mode gain amplifier, and the low-frequency gain may be changed by changing the magnitude of the bias current; Figure 4The first amplifier circuit 120 includes resistors R4 and R5, NMOS transistors MN3 and MN4, and a current source I3. Specifically, the drain of MN3 serves as node net3, connected to one terminal of R4. The other terminal of R4 is used to receive the power supply voltage VDD. The source of MN3 is connected to the first terminal of I3. The second terminal of I3 is grounded. The gate of MN3 is connected to net2. The drain of MN4 serves as node net4, connected to one terminal of R5. The other terminal of R5 is used to receive the power supply voltage VDD. The source of MN4 is connected to the first terminal of I3. The gate of MN4 is connected to net1. The magnitude of current source I3 can be constant or adjustable. In specific applications, current source I3 can be composed of an NMOS transistor controlled by a bias voltage. In one example, if the low-frequency gain of the first amplifier circuit 120 does not need to be changed, the drains of MN3 and MN4 can be directly grounded.

[0054] For the two-terminal signal SS1 / SS2, the two-terminal signal SS1 / SS2 includes a first two-terminal signal sub-signal SS1 and a second two-terminal signal SS2, and the voltage magnitude relationship between the first two-terminal signal sub-signal SS1 and the second two-terminal signal SS2 is determined based on the voltage input relationship between the initial input signal DQ and the initial reference voltage Vref.

[0055] Regarding the input-output relationship of the first amplifier circuit 102, when the voltage of the initial input signal DQ is greater than the voltage of the initial reference voltage Vref, the output voltage OUT1_N of net2 is less than the output voltage OUT1_P of net1, the turn-on degree of MN4 is greater than the turn-on degree of MN3, and the node voltage drop rate of net4 is greater than the node voltage drop rate of net3, so that the voltage of the second two-terminal signal SS2 output by net4 is less than the voltage of the first two-terminal signal SS1 output by net3; when the voltage of the initial input signal DQ is less than the voltage of the initial reference voltage Vref, the output voltage OUT1_P of net1 is less than the output voltage OUT1_N of net2, the turn-on degree of MN3 is greater than the turn-on degree of MN4, and the node voltage drop rate of net3 is greater than the node voltage drop rate of net4, so that the voltage of the first two-terminal signal SS1 output by net3 is less than the voltage of the second two-terminal signal SS2 output by net4.

[0056] In some embodiments, reference Figure 3 The number of comparison circuits 101 included in the data receiving circuit is two or more, and each comparison circuit 101 is configured to amplify the voltage difference between the initial input data DQ and the initial reference voltage Vref, and output a two-terminal signal SS1 / SS2 as the amplified result.

[0057] Each comparison circuit 101 is used to provide a two-terminal signal SS1 / SS2 for at least one data path 102. Figure 3 In this example, each comparison circuit 101 is used to provide a double-ended signal SS1 / SS2 for two data paths. Figure 2 In this example, a single comparison circuit 101 is used to provide two-port signals SS1 / SS2 for four data paths, so that the load of the two-port signals SS1 / SS2 output by each comparison circuit 101 is relatively small, and the signal quality of the input data ultimately obtained by the data receiving circuit is better.

[0058] It should be noted that Figure 3 The example is only used to illustrate that two or more comparison circuits 101 can be set in the data receiving circuit, and does not limit the number of comparison circuits 101. In specific applications, those skilled in the art can reasonably set the number of comparison circuits 101 according to the number of data paths 102 to obtain input data with better quality.

[0059] Continue to refer Figure 2 The plurality of data paths 102 include data paths 1 through 2, numbered in ascending order by natural numbers. The i-th data path is any one of the plurality of data paths. Each data path 102 receives a dual-ended signal SS1 / SS2. The i-th data path is configured to sample based on the i-th clock to obtain the i-th bit of data. In the aforementioned four-phase clock example, the first data path is configured to sample based on the clock signal CLK-0 to obtain the first bit of data, i.e., DQ-0. The second data path is configured to sample based on the clock signal CLK-90 to obtain the second bit of data, i.e., DQ-90. The third data path is configured to sample based on the clock signal CLK-180 to obtain the third bit of data, i.e., DQ-180. The following description uses the data path for obtaining input data DQ-0 as an example. Those skilled in the art may replace the corresponding signals to obtain the specific implementation of other data paths, and this embodiment will not be further described.

[0060] The i-th data path 102 includes an adjustment circuit 201 and a sampling circuit 202, wherein the adjustment circuit 201 is used to receive the second-bit data before the i-th bit data to the N-bit data before the i-th bit data, 2≤N≤M, and the adjustment circuit 201 is configured to adjust the voltage difference between the two-end signals SS1 / SS2 based on the second-bit data to the N-bit data to generate the two-end adjustment signal SS3 / SS4; the sampling circuit 202 is used to receive the two-end adjustment signal SS3 / SS4, the i-th clock and the first-bit data before the i-th bit data. The sampling circuit 202 is configured to compare and amplify the voltage difference between the two-end adjustment signals SS3 / SS4 based on the first-bit data during the effective period of the i-th clock, and output the i-th bit data.

[0061] For the first data path 102, the adjustment circuit 201 is used to receive the input data from the second bit before DQ-0 to the Nth bit before DQ-270, that is, the input data before DQ-180, DQ-90, DQ-0, etc. The adjustment circuit 201 is configured to adjust the voltage difference between the two-end signals SS1 / SS2 based on the input data before DQ-270 to generate the two-end adjustment signal SS3 / SS4. The sampling circuit 202 is used to receive the two-end adjustment signal SS3 / SS4, the clock signal CLK-0, and the first bit before DQ-0, that is, DQ-270. The sampling circuit 202 is configured to compare and amplify the voltage difference between the two-end adjustment signals SS3 / SS4 based on DQ-270 during the active period of the clock signal CLK-0, and output DQ-0.

[0062] For the working principle of the adjustment circuit 201, in one example, refer to Figure 5 The adjustment circuit 201 includes a second amplifying circuit 310 and a plurality of sub-adjusting circuits 320 .

[0063] The second amplifier circuit 310 can be a current-mode gain amplifier. By changing the bias current, the low-frequency gain can be changed. Figure 5 The second amplifier circuit 310 includes resistors R6 and R7, NMOS transistors MN5 and MN6, and a current source I4. Specifically, the drain of MN5 serves as node net5, connected to one terminal of R6. The other terminal of R6 is used to receive the power supply voltage VDD. The source of MN5 is connected to the first terminal of I4, the second terminal of I4 is grounded, and the gate of MN5 is used to receive the first two-terminal signal SS1. The drain of MN6 serves as node net6, connected to one terminal of R7. The other terminal of R7 is used to receive the power supply voltage VDD. The source of MN6 is connected to the first terminal of I4, and the gate of MN6 is used to receive the second two-terminal signal SS2. Nodes net5 and net6 are used to output two-terminal regulation signals SS3 / SS4. The magnitude of current source I4 can be constant or adjustable. In specific applications, current source I4 can be a bias-voltage-controlled NMOS transistor. In one example, if the low-frequency gain of the second amplifier circuit 310 does not need to be changed, the drains of MN5 and MN6 can be directly grounded.

[0064] For the two-end regulation signal SS3 / SS4, the two-end regulation signal SS3 / SS4 includes the first regulation sub-signal SS3 and the second regulation sub-signal SS4, and the voltage magnitude relationship between the first regulation sub-signal SS3 and the second regulation sub-signal SS4 is determined based on the voltage input relationship between the first two-end signal sub-signal SS1 and the second two-end signal SS2.

[0065] As for the input-output relationship of the second amplifier circuit 310, when the voltage of the first dual-terminal signal SS1 is greater than the voltage of the second dual-terminal signal SS2, the open degree of MN5 is greater than the open degree of MN6, so that the node voltage of net5 is less than the node voltage of net6, that is, the voltage of the second regulation sub-signal SS4 is less than the voltage of the first regulation sub-signal SS3; when the voltage of the first dual-terminal signal SS1 is less than the voltage of the second dual-terminal signal SS2, the open degree of MN5 is less than the open degree of MN6, so that the node voltage of net5 is greater than the node voltage of net6, that is, the voltage of the second regulation sub-signal SS4 is greater than the voltage of the first regulation sub-signal SS3.

[0066] Each of the plurality of sub-conditioning circuits 320 is used to correspond to the previous 1-bit data, that is, for the data path 102 for outputting DQ-0, the plurality of sub-conditioning circuits 320 are used to correspond to the previous DQ-180, DQ-90 and DQ-0 respectively. Figure 5 In one example, for the leftmost sub-regulation circuit 320, the sub-regulation circuit 320 includes two branches, each branch includes two switching transistors, one of which is used to receive the first drive signal QD1, and the other is used to receive DQ-180 or its inverted signal DQ-180-.

[0067] For the first driving signal QD1, the first driving signal QD1 is used to turn on the corresponding sub-regulation circuit 320. Figure 5 For example, when the first drive signal QD1 is valid, the leftmost sub-regulation circuit 320 is turned on, and the dual-ended regulation signals SS3 / SS4 are fine-tuned based on DQ-180; similarly, the second drive signal QD2 is used to turn on the middle sub-regulation circuit 320. When the second drive signal QD2 is valid, the middle sub-regulation circuit 320 is turned on, and the dual-ended regulation signals SS3 / SS4 are fine-tuned based on DQ-90; similarly, the third drive signal QD3 is used to turn on the rightmost sub-regulation circuit 320. When the third drive signal QD3 is valid, the rightmost sub-regulation circuit 320 is turned on, and the dual-ended regulation signals SS3 / SS4 are fine-tuned based on DQ-0.

[0068] Specifically, when DQ-180 is at a low level, based on the above ISI adjustment principle, it is known that the value of the initial reference voltage Vref needs to be reduced for the current data DQ-0. Figure 5For the circuit, the branch where DQ-180- is located is turned on, which pulls down the voltage of the net5 node, thereby reducing the value of the second regulation sub-signal SS4 in disguise, which is equivalent to increasing the value of the first two-terminal signal SS1, and further equivalent to increasing the value of the initial data DQ, that is, reducing the value of the initial reference voltage Vref; when DQ-180 is high, based on the above ISI regulation principle, it is known that the value of the initial reference voltage Vref needs to be increased for the current data DQ-0, and for Figure 5 For the circuit, the branch where DQ-180 is located is turned on, pulling down the voltage of the net6 node, thereby reducing the value of the first regulation sub-signal SS3 in disguise, which is equivalent to increasing the value of the second two-terminal signal SS2, and further equivalent to increasing the value of the initial reference voltage Vref.

[0069] for Figure 5 As for the other sub-regulation circuits 320 , their working principles are the same as that of the leftmost sub-regulation circuit 320 . Those skilled in the art can replace the data stream based on the above discussion, which will not be described in detail in this embodiment.

[0070] The sampling circuit 202 samples the dual-ended conditioning signals SS3 / SS4 based on the clock CLK-0 and outputs DQ-0. During the sampling process, the sampling circuit 202 compares, amplifies, and adjusts the voltage difference between the dual-ended conditioning signals SS3 / SS4 based on the first bit of data before the sampling. This allows the circuit to consider the impact of the first bit of data on the current input data, thereby resolving the ISI problem.

[0071] for Figure 5 In the example data receiving circuit, the data receiving circuit adjusts the current input data based on the feedback of the previous multi-bit input data, which greatly reduces the impact of ISI on the current input data. In addition, the circuit area is compressed as much as possible and does not affect the storage capacity of the memory.

[0072] In some embodiments, reference Figure 6 The sampling circuit 202 also receives a first reference voltage Vref1 and a second reference voltage Vref2, wherein the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2. The sampling circuit 202 compares and amplifies the voltage difference between the two-end adjustment signals SS3 / SS4 based on the previous bit of data, and outputs the i-th bit of data, including: based on the first bit of data, selecting to equivalently increase or equivalently decrease the voltage difference between the two-end adjustment signals SS3 / SS4 by the voltage difference between the first reference voltage Vref1 and the second reference voltage Vref2, and comparing and amplifying the voltage difference between the two-end adjustment signals SS3 / SS4 to output the i-th bit of data.

[0073] Specific reference Figure 7The sampling circuit 202 includes: a selection adjustment circuit 330 and a latch circuit 340; wherein the selection adjustment circuit 330 is configured to, during the effective period of the i-th clock, based on the value of the previous i-th bit data, select to adjust the branch current of the branch where the first adjustment sub-signal SS3 is located through the first reference voltage Vref1, and adjust the branch current of the branch where the second adjustment sub-signal SS4 is located through the second reference voltage Vref2; or, adjust the branch current of the branch where the second adjustment sub-signal SS4 is located through the first reference voltage Vref1, and adjust the branch current of the branch where the first adjustment sub-signal SS3 is located through the second reference voltage Vref2, and the latch circuit 340 is configured to sample and latch the i-th bit data based on the i-th clock.

[0074] The selection adjustment circuit 330 includes: a first NMOS transistor N01, a control end for receiving the first adjustment sub-signal SS1, and a first end connected to the latch circuit 340; a second NMOS transistor N02, a control end for receiving the second adjustment sub-signal SS2, a first end connected to the latch circuit 340, and a second end connected to the second end of the first NMOS transistor N01; a first switch NMOS transistor KN01, a control end for receiving the power supply voltage VDD, and a first end connected to the second end of the first NMOS transistor N01; a second switch NMOS transistor KN02, a control end for receiving the i-th clock, a first end connected to the second end of the first switch NMOS transistor KN01, and a second end grounded; a first adjustment NMOS transistor TN01, a control end for receiving the first reference voltage Vref1, and a first end connected to the first end of the second NMOS transistor N02; a second adjustment NMOS transistor TN02, a control end for receiving the second reference voltage Vref2, a first end connected to the first end of the first NMOS transistor N01, and a second end connected to the first adjustment NMOS transistor TN a control end for receiving the first bit of data before the first bit, and a first end connected to the second end of the second adjusting NMOS transistor TN02; a control end for receiving the i-th clock signal, a first end connected to the second end of the third switch NMOS transistor KN03, and a second end connected to ground; a control end for receiving the second reference voltage Vref2, a first end connected to the first end of the second NMOS transistor N02, and a control end for receiving the first reference voltage Vref1, a first end connected to the first end of the first NMOS transistor N01, and a second end connected to the second end of the third adjusting NMOS transistor TN03; a control end for receiving the inverted signal of the first bit of data before the first bit, and a first end connected to the second end of the fourth adjusting NMOS transistor TN04; a control end for receiving the i-th clock signal, a first end connected to the second end of the fifth switch NMOS transistor KN05, and a second end connected to ground.

[0075] The latch circuit 340 includes: a first PMOS transistor P01, a first end of which is used to receive the power supply voltage VDD; a second PMOS transistor P02, a first end of which is used to receive the power supply voltage VDD; a third NMOS transistor N03, a control end of which is connected to the control end of the first PMOS transistor P01, a first end of which is connected to the second end of the first PMOS transistor P01, and a second end of which is connected to the first end of the first NMOS transistor N01; a fourth NMOS transistor N04, a control end of which is connected to the control end of the second PMOS transistor P02, a first end of which is connected to the second end of the second PMOS transistor P02, and a second end of which is connected to the first end of the second NMOS transistor N02; the control end of the third NMOS transistor N03 is also connected to the control end of the fourth NMOS transistor N04. The first end of the fourth NMOS transistor N04 serves as the first output end OUT of the latch circuit 340. The control end of the fourth NMOS transistor N04 is also connected to the first end of the third NMOS transistor N03 to serve as the second output end OUTB of the latch circuit 340. The first output end is used to output the i-th bit data, and the second output end is used to output the inverted signal of the i-th bit data. The first reset PMOS transistor FP01 has a control end for receiving the i-th clock, a first end for receiving the power supply voltage VDD, and a second end connected to the second end of the first PMOS transistor P01. The second reset PMOS transistor FP02 has a control end for receiving the i-th clock, a first end for receiving the power supply voltage VDD, and a second end connected to the second end of the second PMOS transistor P02.

[0076] The operating principle of the sampling circuit 202 is as follows: When CLK-0 is low, that is, the i-th clock is invalid, the input data DQ-0 is not currently generated, the second switch NMOS transistor KN02, the fourth switch NMOS transistor KN04, and the sixth switch NMOS transistor KN06 are all turned off, the selection adjustment circuit 330 is turned off, and the first reset PMOS transistor FP01 and the second reset PMOS transistor FP02 are turned on to reset the sampling circuit 202. When CLK-0 is high, that is, the i-th clock is valid, the input data DQ-0 needs to be generated.

[0077] If the voltage value of the initial input data DQ is greater than the voltage value of the initial reference voltage Vref, based on the foregoing content, the voltage value of the first regulation sub-signal SS3 is greater than the voltage value of the second regulation sub-signal SS4. The first switch NMOS tube KN01 is turned on based on the power supply voltage VDD, and the second switch NMOS tube KN02 is turned on based on CLK-0, so that the potential of the second terminal of the third NMOS tube N03 is less than the potential of the second terminal of the fourth NMOS tube N04. For the latch circuit 340, under ideal circumstances, the potential of the first output terminal OUT is greater than the potential of the second output terminal OUTB, and DQ-0 is at a high level.

[0078] If the previous first bit of data DQ-270 is at a high level, the third switch NMOS transistor KN03 is turned on, and the fourth switch NMOS transistor KN04 is turned on based on CLK-0. At this time, the second regulating NMOS transistor TN02 pulls down the potential of the second terminal of the third NMOS transistor N03, and the first regulating NMOS transistor TN01 pulls down the potential of the second terminal of the fourth NMOS transistor N04. In addition, the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2. The pull-down capability of the first regulating NMOS transistor TN01 is greater than the pull-down capability of the second regulating NMOS transistor TN02. As a result, the potential drop of the second terminal of the third NMOS transistor N03 is less than the potential drop of the second terminal of the fourth NMOS transistor N04. This is equivalent to increasing the value of the initial reference voltage Vref. However, since the previous bit of data DQ-270 is at a high level, DQ-0 still needs to be sampled as a high level. The change in the initial input data DQ is not significant. The increased initial reference voltage Vref does not affect the sampling of the data receiving circuit, and DQ-0 is still sampled as a low level.

[0079] If the first bit data DQ-270 is at a low level, the fifth switch NMOS transistor KN05 is turned on, and the sixth switch NMOS transistor KN06 is turned on based on CLK-0. At this time, the fourth regulating NMOS transistor TN04 pulls down the second terminal potential of the third NMOS transistor N03, and the third regulating NMOS transistor TN03 pulls down the second terminal potential of the fourth NMOS transistor N04. In addition, the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2, and the pull-down capability of the fourth regulating NMOS transistor TN04 is greater than the pull-down capability of the third regulating NMOS transistor TN03, so that the third NMOS transistor N03 is pulled down. The extent of the decrease in the potential of the second terminal of the MOS transistor N03 is greater than the extent of the decrease in the potential of the second terminal of the fourth NMOS transistor N04, which is equivalent to lowering the value of the initial reference voltage Vref. This allows the rising initial input data DQ to rise to a voltage value greater than the initial reference voltage Vref within a relatively short change time. This ensures that the potential of the second terminal of the third NMOS transistor N03 is lower than the potential of the second terminal of the fourth NMOS transistor N04 in actual circumstances. For the latch circuit 340, the potential of the first output terminal OUT is greater than the potential of the second output terminal OUTB, and DQ-0 is at a high level.

[0080] If the voltage value of the initial input data DQ is less than the voltage value of the initial reference voltage Vref, based on the foregoing content, the voltage value of the first regulation sub-signal SS3 is less than the voltage value of the second regulation sub-signal SS4. The first switch NMOS tube KN01 is turned on based on the power supply voltage VDD, and the second switch NMOS tube KN02 is turned on based on CLK-0, so that the potential of the second terminal of the third NMOS tube N03 is greater than the potential of the second terminal of the fourth NMOS tube N04. For the latch circuit 340, under ideal circumstances, the potential of the first output terminal OUT is less than the potential of the second output terminal OUTB, and DQ-0 is at a low level.

[0081] If the first bit data DQ-270 is at a high level, the third switch NMOS transistor KN03 is turned on, and the fourth switch NMOS transistor KN04 is turned on based on CLK-0. At this time, the second regulating NMOS transistor TN02 pulls down the second terminal potential of the third NMOS transistor N03, and the first regulating NMOS transistor TN01 pulls down the second terminal potential of the fourth NMOS transistor N04. In addition, the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2, and the pull-down capability of the first regulating NMOS transistor TN01 is greater than the pull-down capability of the second regulating NMOS transistor TN02, so that the third NMOS transistor TN02 is turned on. The extent of the decrease in the potential of the second terminal of the MOS transistor N03 is less than the extent of the decrease in the potential of the second terminal of the fourth NMOS transistor N04, which is equivalent to increasing the value of the initial reference voltage Vref. This allows the decreasing initial input data DQ to decrease to a voltage value less than the initial reference voltage Vref within a relatively short change time. This ensures that the potential of the second terminal of the third NMOS transistor N03 is greater than the potential of the second terminal of the fourth NMOS transistor N04 in actual circumstances. For the latch circuit 340, the potential of the first output terminal OUT is less than the potential of the second output terminal OUTB, and DQ-0 is at a low level.

[0082] If the previous bit of data DQ-270 is at a low level, the fifth switch NMOS transistor KN05 is turned on, and the sixth switch NMOS transistor KN06 is turned on based on CLK-0. At this time, the fourth regulating NMOS transistor TN04 pulls down the potential of the second terminal of the third NMOS transistor N03, and the third regulating NMOS transistor TN03 pulls down the potential of the second terminal of the fourth NMOS transistor N04. Furthermore, the voltage value of the first reference voltage Vref1 is greater than the voltage value of the second reference voltage Vref2, and the pull-down capability of the fourth regulating NMOS transistor TN04 is greater than the pull-down capability of the third regulating NMOS transistor TN03. As a result, the potential of the second terminal of the third NMOS transistor N03 drops more than the potential of the second terminal of the fourth NMOS transistor N04, which is equivalent to reducing the value of the initial reference voltage Vref. However, since the previous bit of data DQ-270 is at a low level, DQ-0 still needs to be sampled as a low level. The change in the initial input data DQ is not significant, and the reduced initial reference voltage Vref does not affect the sampling of the data receiving circuit, so DQ-0 is still sampled as a low level.

[0083] It should be noted that for Figure 7 The circuit shown only samples the same input data once, so that the power consumption of the data receiving circuit using the circuit is also reduced accordingly.

[0084] Continue to refer Figure 7 In some embodiments, the latch circuit 340 further includes: a third reset transistor FP03, having a control end for receiving the i-th clock, a first end for receiving the power supply voltage VDD, and a second end connected to the first end of the first NMOS transistor N01; a fourth reset transistor FP04, having a control end for receiving the i-th clock, a first end for receiving the power supply voltage VDD, and a second end connected to the second end of the second NMOS transistor N02; the third reset transistor FP03 and the fourth reset transistor FP04 are used to further reset the latch circuit 340 when no input data is generated, that is, when the i-th clock is invalid.

[0085] In some embodiments, reference Figure 8 The data receiving circuit also includes: a code generation circuit 103, which is configured to receive a reference voltage generation code and a tap code BM corresponding to the first bit of data, generate a first reference voltage generation code code1 based on the reference voltage generation code + the tap code BM, and generate a second reference voltage generation code code2 based on the reference voltage generation code - the tap code BM; wherein the first reference voltage generation code code1 is used to generate a first reference voltage Vref1, the second reference voltage generation code code2 is used to generate a second reference voltage Vref2, and the tap code BM is used to match the voltage adjustment step corresponding to the first bit of data DQ-C.

[0086] The reference voltage generation code can be the configuration value MR10 OP<7:0> of the mode register in the memory, or can be configured by the memory manufacturer. The code generation circuit 103 is used to identify the configuration value MR10 OP<7:0> in the mode register to obtain the reference voltage generation code. The value of the tap code BM corresponds to the influence of the previous bit of data, that is, it controls the degree of adjustment of the previous bit of data on the current data to better solve the problem of ISI in the memory.

[0087] In some embodiments, a plurality of tap codes BM are stored in a register of the memory. The memory controls the register to output different tap codes BM based on the strength of inter-code interference to generate a tap code BM corresponding to the first bit of data, wherein the strength of the inter-code interference of the memory depends on the frequency of the transmitted data and the channel quality of the data transmission channel.

[0088] Continue to refer Figure 8 In some embodiments, the data receiving circuit further includes: a resistor voltage divider circuit 104, wherein the resistor voltage divider circuit 104 is configured to generate a first reference voltage Vref1 based on a first reference voltage generation code code1, and to generate a second reference voltage Vref2 based on a second reference voltage generation code code2.

[0089] Specifically, the resistor divider circuit 104 is a voltage divider circuit with multiple resistors connected in series between the power supply voltage VDD and ground. Different voltage generation codes are used to instruct different output nodes in the resistor divider circuit 104 to output a first reference voltage Vref1 and a second reference voltage Vref2 with voltage values ​​between 0 and VDD.

[0090] For the code generation circuit 103, refer to Figure 9 The code generation circuit 103 includes a generation circuit 401, an identification circuit 402, a first processing circuit 403, and a second processing circuit 404. The generation circuit 401 is configured to identify a reference voltage generation code to generate an initial reference voltage generation code code. The control circuit 402 is configured to provide a tap code BM to the first processing circuit 403 and the second processing circuit 404. The first processing circuit 403 is configured to generate a first reference voltage generation code code1 based on the initial reference voltage generation code code + the tap code BM. The second processing circuit 404 is configured to generate a second reference voltage generation code code2 based on the initial reference voltage generation code code - the tap code BM.

[0091] In some embodiments, the reference voltage generation code may be the configuration value MR10OP<7:0> of the mode register in the corresponding memory. In this example, the generation circuit 401 reuses the existing reference voltage generation logic to save the area of ​​the code generation circuit.

[0092] In an example, assuming that the initial reference voltage generation code code is used to generate 0.6VDD, the adjustment range of the first reference voltage generation code code1 and the second reference voltage generation code is 0 to ±0.2VDD, then the voltage range of the first reference voltage Vref1 generated by the resistor divider circuit 104 is 0.6VDD to 0.8VDD, and the voltage range of the second reference voltage Vref2 is 0.4VDD to 0.6VDD.

[0093] In some embodiments, the code generation circuit 103 is further configured to generate a fixed reference voltage to increase the flexibility of the resistor divider circuit 104. Figure 10 The generating circuit 601 is further configured to generate a reference voltage generation code corresponding to a preset reference voltage, or identify a configuration value MR10 OP<7:0> of a mode register in a corresponding memory to generate an initial reference voltage generation code.

[0094] In an example, assuming that the initial reference voltage generation code generated by the configuration value MR10 OP<7:0> of the mode register in the corresponding memory is used to generate 0.6VDD, the initial reference voltage generation code generated by the fixed value reference voltage is used to generate 0.5VDD, and the adjustment range of the first reference voltage generation code code1 and the second reference voltage generation code is 0 to ±0.2VDD. At this time, the voltage range of the first reference voltage Vref1 generated by the resistor voltage divider circuit 104 is 0.5VDD to 0.8VDD, and the voltage range of the second reference voltage Vref2 is 0.3VDD to 0.6VDD. The voltage range of the first reference voltage Vref1 and the voltage range of the second reference voltage Vref2 generated by the resistor voltage divider circuit 104 are larger and more flexible.

[0095] Specifically, the generation circuit 601 includes a first sub-generation circuit 610, a second sub-generation circuit 620, and a selection circuit 630. The first sub-generation circuit 601 is configured to identify the configuration value MR10OP<7:0> of the mode register in the memory to generate a first reference code. The second sub-generation circuit 620 is configured to generate a second reference code corresponding to a preset reference voltage, wherein the second reference code corresponding to the preset reference voltage is achieved by receiving code A. The selection circuit 630 is configured to select, based on a selection signal Sel, whether to generate an initial reference voltage code based on the first reference code or the second reference code.

[0096] It should be noted that Figure 10 The control circuit 602, the first processing circuit 603 and the second processing circuit 604 in the example correspond to Figure 9The identification circuit 402, the first processing circuit 403 and the second processing circuit 404 in the example are described with reference to Figure 9 The description of the example will not be repeated in this embodiment.

[0097] In some embodiments, reference Figure 11 Generating circuit 701 is configured to generate an initial reference voltage generation code (code) based on debug code 4, wherein debug code 4 is based on eye diagram data acquired by the memory in test mode, and uses an initial reference voltage Vref that is optimal for the memory eye diagram. In this example, because generating circuit 701 generates the initial reference voltage generation code (code) based on debug code 4, which is based on eye diagram data acquired by the memory in test mode, the memory ISI protection effect is optimal, and a better data eye diagram can be obtained.

[0098] It should be noted that Figure 11 The control circuit 702, the first processing circuit 703 and the second processing circuit 704 in the example correspond to Figure 9 The identification circuit 402, the first processing circuit 403 and the second processing circuit 404 in the example are described with reference to Figure 9 The description of the example will not be repeated in this embodiment.

[0099] In some embodiments, reference Figure 12 , the code generation circuit 103 is also used to combine Figure 9 and Figure 11 For example, the initial reference voltage generation code code is generated based on the configuration value MR10 OP<7:0> of the mode register in the memory or the debug code code4.

[0100] Specifically, the generation circuit 801 includes a first sub-generation circuit 810, a second sub-generation circuit 802, and a selection circuit 830. The first sub-generation circuit 810 is configured to identify the configuration value MR10OP<7:0> of the mode register in the memory to generate a first reference code. The second sub-generation circuit 802 is configured to generate a second reference code based on the debug code code4. The selection circuit 830 is configured to select, based on a selection signal Sel, whether to generate an initial reference voltage generation code code based on the first reference code or the second reference code.

[0101] It should be noted that Figure 12 The control circuit 802, the first processing circuit 803 and the second processing circuit 804 in the example correspond to Figure 9 The identification circuit 402, the first processing circuit 403 and the second processing circuit 404 in the example are described with reference to Figure 9 The description of the example will not be repeated in this embodiment.

[0102] The data receiving circuit provided in this embodiment uses feedback from previous multi-bit input data to adjust current input data, significantly reducing the impact of ISI on current input data. Furthermore, the circuit area is minimized and does not affect the storage capacity of the memory. Furthermore, the data receiving circuit samples the same input data only once, thereby reducing circuit power consumption.

[0103] It should be noted that the features disclosed in the data receiving circuits provided in the above embodiments can be arbitrarily combined without conflict to obtain new data receiving circuit embodiments.

[0104] Another embodiment of the present disclosure provides a memory, including the data receiving circuit provided by the above embodiment, which is at least beneficial to improving the inter-symbol interference problem of the memory.

[0105] The memory device may be a storage unit or device based on a semiconductor device or component. For example, the memory device may be a volatile memory, such as dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), double data rate synchronous dynamic random access memory (DDR SDRAM), low power double data rate synchronous dynamic random access memory (LPDDR SDRAM), graphics double data rate synchronous dynamic random access memory (GDDR SDRAM), double data rate type dual synchronous dynamic random access memory (DDR2 SDRAM), double data rate type triple synchronous dynamic random access memory (DDR3 SDRAM), double data rate fourth generation synchronous dynamic random access memory (DDR4 SDRAM), thyristor random access memory (TRAM), etc.; or it may be a non-volatile memory, such as phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), etc.

[0106] In some examples, N and M can be 4.

[0107] From the above analysis, it can be seen that while the memory improves the inter-symbol interference problem, the area of ​​the data receiving circuit is relatively compressed as much as possible without affecting the storage capacity of the memory; in addition, the data receiving circuit only samples the same input data once, which reduces the power consumption of the circuit accordingly.

[0108] Those skilled in the art will appreciate that the above-described embodiments are specific examples for implementing the present disclosure, and that in actual applications, various changes may be made to the embodiments in form and detail without departing from the spirit and scope of the embodiments of the present disclosure. Any person skilled in the art may make changes and modifications without departing from the spirit and scope of the embodiments of the present disclosure. Therefore, the scope of protection of the embodiments of the present disclosure shall be based on the scope defined in the claims.

Claims

1. A data receiving circuit, characterized in that: include: a comparison circuit receiving initial input data and an initial reference voltage, configured to amplify a voltage difference between the input data and the initial reference voltage, and output a two-terminal signal as a result of the amplification; A plurality of data paths, including: a 1st data path to an Mth data path numbered in ascending order of natural numbers, the i-th data path being any one of the plurality of data paths, 1≤i≤M, M≥2; Each of the data paths receives the two-terminal signal, wherein the i-th data path is configured to obtain i-th bit data based on i-th clock sampling, and the i-th data path includes: an adjustment circuit, receiving data from the second bit before the i-th bit to data from the N-th bit before the i-th bit, where 2≤N≤M, and configured to adjust a voltage difference between the two-end signals based on the data from the second bit before the N-th bit before the i-th bit to generate a two-end adjustment signal; The sampling circuit receives the double-ended adjustment signal, the i-th clock, and the first bit of data before the i-th bit data, and is configured to compare and amplify the voltage difference between the double-ended adjustment signals based on the first bit of data during the effective period of the i-th clock, and output the i-th bit data.

2. The data receiving circuit according to claim 1, wherein: include: The sampling circuit further receives a first reference voltage and a second reference voltage, wherein the voltage value of the first reference voltage is greater than the voltage value of the second reference voltage; The comparing and amplifying the voltage difference between the two-end adjustment signals based on the first bit data and outputting the i-th bit data includes: based on the first bit data, selecting to equivalently increase or equivalently reduce the voltage difference between the two-end adjustment signals through the voltage difference between the first reference voltage and the second reference voltage, and comparing and amplifying the voltage difference between the two-end adjustment signals to output the i-th bit data.

3. The data receiving circuit according to claim 2, wherein: The two-terminal regulation signal includes a first regulation sub-signal and a second regulation sub-signal, and the sampling circuit includes: a selection adjustment circuit configured to, during an effective period of the i-th clock, based on a value of the first bit of data, select to adjust the branch current of the branch where the first adjustment sub-signal is located using the first reference voltage, and to adjust the branch current of the branch where the second adjustment sub-signal is located using the second reference voltage; Or, adjusting the branch current of the branch where the second regulation sub-signal is located by using the first reference voltage, and adjusting the branch current of the branch where the first regulation sub-signal is located by using the second reference voltage; The latch circuit is configured to sample and latch the i-th bit data based on the i-th clock.

4. The data receiving circuit according to claim 3, wherein: The selection adjustment circuit includes: A first NMOS transistor, a control end of which is used to receive the first regulator signal, and a first end of which is connected to the latch circuit; A second NMOS transistor, whose control end is used to receive the second regulator signal, whose first end is connected to the latch circuit, and whose second end is connected to the second end of the first NMOS transistor; A first switch NMOS transistor, a control end of which is used to receive a power supply voltage, and a first end of which is connected to the second end of the first NMOS transistor; A second switch NMOS transistor, whose control end is used to receive the i-th clock, whose first end is connected to the second end of the first switch NMOS transistor, and whose second end is grounded; a first adjustment NMOS transistor, a control end of which is used to receive the first reference voltage, and a first end of which is connected to the first end of the second NMOS transistor; a second adjusting NMOS transistor, whose control end is used to receive the second reference voltage, whose first end is connected to the first end of the first NMOS transistor, and whose second end is connected to the second end of the first adjusting NMOS transistor; A third switch NMOS transistor, a control end of which is used to receive the first bit of data, and a first end of which is connected to the second end of the second adjustment NMOS transistor; a fourth switch NMOS transistor, whose control end is used to receive the i-th clock, whose first end is connected to the second end of the third switch NMOS transistor, and whose second end is grounded; a third adjusting NMOS transistor, having a control end for receiving the second reference voltage and a first end connected to the first end of the second NMOS transistor; a fourth adjusting NMOS transistor, whose control end is used to receive the first reference voltage, whose first end is connected to the first end of the first NMOS transistor, and whose second end is connected to the second end of the third adjusting NMOS transistor; a fifth switch NMOS transistor, whose control end is used to receive the inverted signal of the first bit of data, and whose first end is connected to the second end of the fourth adjustment NMOS transistor; The sixth switch NMOS transistor has a control end for receiving the i-th clock, a first end connected to the second end of the fifth switch NMOS transistor, and a second end grounded.

5. The data receiving circuit according to claim 4, wherein: The latch circuit comprises: A first PMOS tube, a first end of which is used to receive a power supply voltage; A second PMOS tube, a first end of which is used to receive a power supply voltage; a third NMOS transistor, having a control end connected to the control end of the first PMOS transistor, a first end connected to the second end of the first PMOS transistor, and a second end connected to the first end of the first NMOS transistor; a fourth NMOS transistor, having a control end connected to the control end of the second PMOS transistor, a first end connected to the second end of the second PMOS transistor, and a second end connected to the second end of the second NMOS transistor; The control end of the third NMOS transistor is further connected to the first end of the fourth NMOS transistor to serve as the first output end of the latch circuit. The control end of the fourth NMOS transistor is further connected to the first end of the third NMOS transistor to serve as the second output end of the latch circuit. The first output end is used to output the i-th bit of data, and the second output end is used to output an inverted signal of the i-th bit of data. a first reset PMOS transistor, whose control end is used to receive the i-th clock, a first end is used to receive a power supply voltage, and a second end is connected to the second end of the first PMOS transistor; The second reset PMOS tube has a control end for receiving the i-th clock, a first end for receiving a power supply voltage, and a second end connected to the second end of the second PMOS tube.

6. The data receiving circuit according to claim 5, wherein: The latch circuit further includes: a third reset PMOS transistor, whose control end is used to receive the i-th clock, a first end is used to receive a power supply voltage, and a second end is connected to the first end of the first NMOS transistor; A fourth reset PMOS transistor has a control end for receiving the i-th clock, a first end for receiving a power supply voltage, and a second end connected to the second end of the second NMOS transistor.

7. The data receiving circuit according to claim 1, wherein: Also includes: The code generation circuit is configured to receive a reference voltage generation code and a tap code corresponding to the first bit of data, generate a first reference voltage generation code based on the reference voltage generation code + the tap code, and generate a second reference voltage generation code based on the reference voltage generation code - the tap code; wherein the first reference voltage generation code is used to generate a first reference voltage, the second reference voltage generation code is used to generate a second reference voltage, and the tap code is used to match the voltage adjustment step corresponding to the first bit of data.

8. The data receiving circuit according to claim 7, wherein: Also includes: The resistor voltage divider circuit is configured to generate a first reference voltage based on the first reference voltage generation code, and to generate a second reference voltage based on the second reference voltage generation code.

9. The data receiving circuit according to claim 7, wherein: The code generation circuit comprises: A generating circuit configured to generate the initial reference voltage generation code; A control circuit configured to provide the tap code to the first processing circuit and the second processing circuit; The first processing circuit is configured to generate the first reference voltage generation code based on the initial reference voltage generation code and the tap code; The second processing circuit is configured to generate the second reference voltage generation code based on the initial reference voltage generation code minus the tap code.

10. The data receiving circuit according to claim 9, wherein: The generating circuit is configured to generate the reference voltage generation code corresponding to a reference voltage of a preset value, or to identify a configuration value of a mode register in a corresponding memory to generate the initial reference voltage generation code.

11. The data receiving circuit according to claim 10, wherein: The generating circuit comprises: A first sub-generating circuit is configured to identify a configuration value of a mode register in a corresponding memory to generate a first reference code; The second sub-generating circuit is configured to generate a second reference code corresponding to a reference voltage of a preset value; The selection circuit is configured to select, based on a selection signal, whether to generate the initial reference voltage code based on the first reference code or the second reference code.

12. The data receiving circuit according to claim 9, wherein: The generating circuit is configured to generate the initial reference voltage generation code based on a debugging code, wherein the debugging code is obtained based on eye diagram data of the memory in a test mode.

13. The data receiving circuit according to claim 12, wherein: The generating circuit comprises: A first sub-generating circuit is configured to identify a configuration value of a mode register in a corresponding memory to generate a first reference code; A second sub-generating circuit is configured to generate a second reference code based on the debugging code; The selection circuit is configured to select, based on a selection signal, whether to generate the reference voltage code based on the first reference code or the second reference code.

14. A memory, characterized in that: The data receiving circuit comprises the data receiving circuit according to any one of claims 1 to 13.

15. The memory according to claim 14, wherein: The N and M are 4.

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