Chip packaging auxiliary mold, chip packaging method and packaged chip

Abstract

The chip packaging auxiliary mold, chip packaging method and packaged chip provided in the embodiment of the present application relate to the field of chip packaging technology. In the chip packaging auxiliary mold, the first mold bar and the second mold bar enclose a grid through hole, and the grid through hole cooperates with the packaging carrier to form a limiting groove for limiting the chip, thereby improving the problem of chip displacement during the packaging process, thereby reducing the difficulty of subsequent process technology and improving the yield of chip packaging.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to a chip packaging auxiliary mold, a chip packaging method and a packaged chip. Background Art

[0002] Chip packaging is the back-end processing technology of semiconductor chips, which provides physical protection, signal interconnection, heat dissipation and fixation for the chip core structure (chip bare die). Especially when semiconductors enter the post-Moore era, the role of advanced packaging technology on chip bare dies is becoming more and more important. Panel Level Package (PLP) uses a large-size packaging substrate, and a single process can realize the packaging of a large number of chips, especially for larger-sized chips and system in package (SiP), which has obvious advantages in cutting rate. Summary of the invention

[0003] The embodiments of the present application provide a chip packaging auxiliary mold, a chip packaging method and a packaged chip.

[0004] In a first aspect of the present application, a chip packaging auxiliary mold is provided, wherein the chip packaging auxiliary mold comprises:

[0005] The mold body is in a grid shape, and the grid through holes in the mold body cooperate with the packaging carrier to form a limiting groove for limiting the chip.

[0006] In a possible implementation manner of the present application, the mold body includes a plurality of first mold bars arranged along a first direction and a plurality of second mold bars arranged along a second direction, and the first mold bars and the second mold bars enclose the grid through holes;

[0007] Preferably, the first direction and the second direction are perpendicular to each other.

[0008] In a possible implementation manner of the present application, a plurality of the first mold bars are arranged at equal intervals along the first direction, and a plurality of the second mold bars are arranged at equal intervals along the second direction;

[0009] Preferably, the first mold strip and the second mold strip are made of the same material;

[0010] Preferably, the mold body is an integrally formed structure.

[0011] In a possible implementation manner of the present application, the average linear expansion coefficient of the material of the mold body at a temperature of 20 to 300° C. is less than 5.5*10-6 / ° C.;

[0012] Preferably, the elastic modulus of the material of the mold body is greater than 105Mpa, the tensile strength is greater than 480Mpa, and the hardness is greater than 120HV;

[0013] Preferably, the material of the mold body includes Invar alloy.

[0014] In a possible implementation manner of the present application, in a direction passing through the grid through hole, the mold body includes a first side and a second side opposite to each other, and the mold body is further provided with an introduction structure facing the grid through hole on the first side enclosing the grid through hole;

[0015] Preferably, the lead-in structure comprises a chamfer.

[0016] In a possible implementation manner of the present application, the chip packaging auxiliary mold further includes an isolation layer, the isolation layer is located on the surface of the mold body, and the isolation layer is used to separate the chip packaging auxiliary mold from the packaging layer that encapsulates the chip;

[0017] Preferably, the isolation layer has a different thermal expansion coefficient from the packaging layer used to package the chip;

[0018] Preferably, the isolation layer comprises a graphene layer;

[0019] Preferably, the thickness of the isolation layer ranges from greater than or equal to 1 nm to less than or equal to 10 nm;

[0020] Preferably, in the connection direction of adjacent grid through holes, the width of the mold body between adjacent grid through holes ranges from greater than or equal to 10 um to less than or equal to 1000 um.

[0021] In a second aspect of the present application, a chip packaging method is further provided, the method comprising:

[0022] Provide a loading plate and a chip packaging auxiliary mold as described in any possible implementation manner of the first aspect;

[0023] The chip packaging auxiliary mold is attached to the packaging carrier, and the grid through holes of the chip packaging auxiliary mold and the packaging carrier cooperate to form a limiting groove;

[0024] Placing the chip in the limiting groove;

[0025] Performing a plastic encapsulation process on the chip to form an encapsulation layer for encapsulating the chip located in the limiting groove;

[0026] removing the packaging carrier;

[0027] Making a redistribution layer electrically connected to the pins of the chip;

[0028] The chip packaging auxiliary mold is removed to obtain a packaged chip.

[0029] In a possible implementation manner of the present application, in a direction passing through the grid through-holes, the mold body includes a first side and a second side opposite to each other, and the step of attaching the chip packaging auxiliary mold to a packaging carrier, wherein the chip packaging auxiliary grid through-holes and the packaging carrier cooperate to form a limiting groove includes:

[0030] The second side of the mold body is attached to the packaging carrier, and the grid through holes of the mold body and the packaging carrier cooperate to form a limiting groove;

[0031] The step of placing the chip in the limiting groove comprises:

[0032] The chip is placed in the limiting groove with one side of the chip arrangement pins facing away from the packaging carrier.

[0033] In a possible implementation manner of the present application, an isolation layer is further provided on the surface of the mold body, and the step of making a redistribution layer electrically connected to the pins of the chip includes:

[0034] Making a redistribution layer connected to the pins on one side of the chip where the pins are arranged;

[0035] The step of removing the chip packaging auxiliary mold to obtain the packaged chip includes:

[0036] The packaging structure after the redistribution layer is made is subjected to low-temperature treatment to separate the isolation layer from the packaging layer, remove the chip packaging auxiliary mold and obtain the packaged chip, wherein the temperature range of the low-temperature treatment is greater than or equal to -20°C to less than or equal to 10°C.

[0037] A third aspect of the present application provides a packaged chip, wherein the packaged chip is manufactured using a chip packaging method in any possible implementation manner of the second aspect.

[0038] The embodiments of the present application provide a chip packaging auxiliary mold, a chip packaging method and a packaged chip. In the chip packaging auxiliary mold, the grid through holes of the mold body cooperate with the packaging carrier to form a limiting groove for limiting the chip, thereby improving the problem of chip displacement during the packaging process, thereby reducing the difficulty of subsequent process technology and improving the yield of chip packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. It should be understood that the following drawings only show certain embodiments of the present application and therefore should not be regarded as limiting the scope. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0040] Figure 1 A schematic diagram of the structure of the chip packaging auxiliary mold provided in this embodiment;

[0041] Figure 2 Example Figure 1 One of the cross-sectional views of the chip packaging auxiliary mold in the A1A2 direction;

[0042] Figure 3 A schematic diagram of the structure of the cooperation between the chip packaging auxiliary mold and the packaging carrier provided in this embodiment;

[0043] Figure 4 Example Figure 1 A top view of the chip packaging auxiliary mold;

[0044] Figure 5 Example Figure 1 The second cross-sectional view of the chip packaging auxiliary mold in the A1A2 direction;

[0045] Figure 6 A schematic diagram of the steps of the chip packaging method provided in this embodiment;

[0046] Figure 7 and Figure 8 for Figure 6 The corresponding process diagram;

[0047] Icon: 10-chip packaging auxiliary mold; 110-mold body; 110A-first side; 110B-second side; 1101-first mold bar; 1102-second mold bar; 1103-introduction structure; 120-isolation layer; 130-grid through hole; 140-limiting groove; 20-packaging carrier; 30-chip; 310-pin; 40-packaging layer; 50-rewiring layer. DETAILED DESCRIPTION

[0048] In order to make the purpose, technical solution and advantages of the embodiments of the present application clearer, the technical solution in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are part of the embodiments of the present application, rather than all the embodiments. The components of the embodiments of the present application described and shown in the drawings here can be arranged and designed in various different configurations.

[0049] In the description of the present application, it should be noted that the terms "upper", "lower", etc. indicate orientations or positional relationships based on the orientations or positional relationships shown in the accompanying drawings, or are the orientations or positional relationships in which the product of the application is usually placed when in use. They are only for the convenience of describing the present application and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be understood as a limitation on the present application.

[0050] However, in the process of board-level packaging, the chip transfer position accuracy is very high and the chip will be displaced to a certain extent during the plastic packaging process, which will affect the production difficulty of subsequent process technology (for example, making a redistribution layer), thereby reducing the yield of chip packaging. In order to solve this technical problem, the inventor innovatively designed the following technical solution, and the specific implementation solution of this application will be described in detail in conjunction with the accompanying drawings.

[0051] Please refer to Figure 1 , Figure 2 and Figure 3 , Figure 1 The schematic diagram of the structure of the chip packaging auxiliary mold provided in this embodiment is illustrated. Figure 2 Example Figure 1 The cross-sectional view of the chip packaging auxiliary mold in the A1A2 direction. Figure 3 The schematic diagram of the structure of the cooperation between the chip packaging auxiliary mold and the packaging carrier is illustrated. In this embodiment, the chip packaging auxiliary mold 10 includes a mold body 110, the mold body 110 is in a grid shape, and the mold body 110 includes a plurality of grid through holes 130. The grid through holes 130 in the mold body 110 cooperate with the packaging carrier 20 to form a limiting groove 140 for limiting the chip 30.

[0052] In the above structure, on the one hand, the grid through holes 130 of the mold body 110 cooperate with the packaging carrier 20 to form a limiting groove 140 for limiting the chip, thereby improving the problem of chip displacement during the packaging process, thereby reducing the difficulty of subsequent process technology and improving the yield of chip packaging.

[0053] For further information, please refer to Figure 4 The mold body 110 includes a plurality of first mold bars 1101 arranged along a first direction (the Y direction in the figure) and a plurality of second mold bars 1102 arranged along a second direction (the X direction in the figure). The first direction and the second direction intersect. At the position where the first mold bars 1101 and the second mold bars 1102 intersect, the first mold bars 1101 and the second mold bars 1102 share an intersecting portion. For example, Figure 1 As shown, the mold bar L1 and the mold bar L2 share the intersection portion M, that is, the intersection portion M can be regarded as a part of the mold bar L1, and can also be regarded as a part of the mold bar L2.

[0054] A plurality of first mold bars 1101 and a plurality of second mold bars 1102 are crisscrossed to form a grid pattern, in which each grid corresponds to a grid through hole 130 formed by the first mold bars 1101 and the second mold bars 1102. In this embodiment, the first direction and the second direction can be set according to the shape of the chip, for example Figure 4 As shown, when the chip is rectangular, the first direction and the second direction are perpendicular to each other, and the first mold bar 1101 and the second mold bar 1102 enclose a rectangular grid of through holes. When the chip is rhombus-shaped, the first direction and the second direction intersect, and the first mold bar 1101 and the second mold bar 1102 enclose a rhombus-shaped grid of through holes. Preferably, the first direction and the second direction are perpendicular to each other.

[0055] Please refer again Figure 3 The grid through hole can cooperate with the packaging carrier 20 to form a limiting groove 140 for limiting the chip 30, wherein the side wall of the grid through hole forms the side wall of the limiting groove 140, and the packaging carrier 20 forms the groove bottom of the limiting groove 140.

[0056] Furthermore, when performing chip packaging, multiple chips of the same size are generally packaged simultaneously. To this end, the grid holes formed by the first mold bar 1101 and the second mold bar 1102 are required to have the same size, that is, multiple first mold bars 1101 are arranged at equal intervals along the first direction, and multiple second mold bars 1102 are arranged at equal intervals along the second direction, wherein the spacing between two adjacent first mold bars 1101 and the spacing between two adjacent second mold bars 1102 may be the same or different, and may be specifically set accordingly according to the size of the packaged chip.

[0057] In order to improve the structural stability of the chip packaging auxiliary mold 10, the mold body 110 can be an integrally formed structure. For example, the mold body 110 can be made by plate forming. In this embodiment, the first mold bar 1101 and the second mold bar 1102 are made of the same material.

[0058] The inventors further discovered that, during the chip packaging process, due to the difference in thermal expansion coefficients between different materials, the packaging structure may be warped and displaced due to the difference in thermal expansion, which may seriously affect the yield of chip packaging. In order to solve the above technical problems, the chip packaging auxiliary mold 10 provided in this embodiment has the characteristics of high strength and low expansion coefficient.

[0059] For example, the material of the mold body 110 provided in this embodiment meets the following conditions: when the temperature is within the range of 20 to 300° C., the average linear expansion coefficient of the material of the mold body 110 is less than 5.5*10 -6 / ℃; the elastic modulus of the material of the mold body 110 is greater than 10 5 Mpa, tensile strength greater than 480Mpa, and hardness greater than 120HV. In this embodiment, the material of the mold body 110 includes Invar alloy, in which nickel accounts for 36% by mass, iron accounts for 63.8% by mass, and carbon accounts for 0.2% by mass. The mold body 110 made of materials meeting the above conditions can ensure that the chip packaging auxiliary mold 10 has the characteristics of high strength and small thermal expansion coefficient.

[0060] For further information, please refer to Figure 5 In this embodiment, in the direction of penetrating the grid through hole 130 (Z direction in the figure), the mold body 110 has a first side 110A and a second side 110B opposite to each other. The mold body 110 is also provided with an introduction structure 1103 facing the grid through hole 130 on the first side 110A enclosing the grid through hole 130. When performing chip packaging, the second side 110B of the mold body 110 is attached to the packaging carrier, and the introduction structure 1103 located on the first side of the mold body 110 can accelerate the plastic packaging material to enter the limiting groove formed by the grid through hole 130 and the packaging carrier, and quickly fill the gap between the chip and the limiting groove, thereby improving the packaging efficiency.

[0061] Exemplarily, in this embodiment, the introduction structure 1103 includes a chamfer, which may be a round chamfer or an oblique chamfer.

[0062] In this embodiment, please refer to Figure 3 and Figure 5 The chip packaging auxiliary mold 10 also includes an isolation layer 120, which is located on the surface of the mold body 110. The isolation layer 120 is used to separate the chip packaging auxiliary mold 10 from the packaging layer of the packaged chip, wherein the packaging layer made on the isolation layer 120 will form an obvious film layer stratification phenomenon with the isolation layer 120, that is, there is basically no interaction force between the isolation layer 120 and the packaging layer, so it is convenient to separate the chip packaging auxiliary mold 10 from the packaging layer after the chip packaging is completed.

[0063] An isolation layer 120 is disposed on the surface of the mold body 110. The isolation layer 120 and the packaging layer for packaging the chip have different thermal expansion coefficients. After the chip is packaged, the chip packaging auxiliary mold 10 is taken out by separating the isolation layer 120 from the packaging layer, which facilitates the reuse of the chip packaging auxiliary mold 10 and reduces the manufacturing cost of chip packaging.

[0064] Further, the isolation layer 120 may include a graphene layer, and a dense graphene layer is covered on the surface of the mold body 110, which can ensure that when the plastic encapsulation material is formed on it, there will be obvious stratification between the two, that is, the inter-film force between the graphene layer and the encapsulation layer formed by the plastic encapsulation material is very small, which is convenient for separating the chip encapsulation auxiliary mold 10 and the chip encapsulation structure through the separation between the two. Exemplarily, the encapsulation layer can be shrunk relative to the graphene layer by low temperature treatment to achieve separation between the two, wherein the temperature range of the low temperature treatment is greater than or equal to -20°C to less than or equal to 10°C, and exemplary, the temperature of the low temperature treatment includes -20°C, -18.5°C, -15°C, -13°C, -11.5°C, -9°C, -6.4°C, -5°C, -3°C, -0°C, 2°C, 5°C, 8°C and 10°C, etc.

[0065] In this embodiment, the film thickness of the isolation layer 120 ranges from greater than or equal to 1 nm to less than or equal to 10 nm. Exemplarily, the film thickness of the isolation layer 120 includes 1 nm, 1.2 nm, 1.8 nm, 2.5 nm, 3.7 nm, 5.4 nm, 6.2 nm, 7.8 nm, 8.5 nm, 9.7 nm and 10 nm, etc.

[0066] Further, please refer again to Figure 5 In the continuous direction of the adjacent grid through holes 130, the width D of the mold body 110 between the adjacent grid through holes 130 is equivalent to the width of the cutting road. That is, the width D of the mold body 110 between the adjacent grid through holes 130 ranges from greater than or equal to 10um to less than or equal to 1000um. For example, the width D of the mold body 110 between the adjacent grid through holes 130 includes 10um, 13um, 28um, 80um, 120um, 240um, 380um, 495um, 572um, 682um, 745um, 812um, 922um and 1000um.

[0067] Based on the same inventive concept, this embodiment also provides a chip packaging method, please refer to Figure 6 , Figure 7 and Figure 8 , Figure 6 The schematic diagram of the chip packaging method provided in this embodiment is illustrated. Figure 7 and Figure 8 Example Figure 6 The corresponding process diagram is combined with the following Figure 6 , Figure 7 and Figure 8 , the chip packaging method provided in this embodiment is described in detail.

[0068] Step S11 , providing a packaging loading plate 20 and a chip packaging auxiliary mold 10 .

[0069] The chip packaging auxiliary mold 10 is the chip packaging auxiliary mold described in the previous embodiment, and the packaging carrier 20 is a glass carrier or a copper plate with a low thermal expansion coefficient.

[0070] Step S12 , attaching the chip packaging auxiliary mold 10 to the packaging carrier 20 , and the grid through holes of the chip packaging auxiliary mold 10 and the packaging carrier 20 cooperate to form a limiting groove 140 .

[0071] In this embodiment, in the direction of penetrating the grid through holes, the mold body 110 includes a first side and a second side opposite to each other, and the mold body 110 is further provided with a lead-in structure 1103 facing the grid through holes 130 on the first side enclosing the grid through holes. In this step, the second side of the mold body 110 is attached to the package carrier 20, and the grid through holes in the mold body 110 and the package carrier 20 cooperate to form a limiting groove.

[0072] In this step, a temporary bonding layer (not shown in the figure) may be further provided on the packaging carrier 20 , and the chip packaging auxiliary mold 10 is attached to the side of the packaging carrier 20 where the temporary bonding layer is provided.

[0073] Step S13 , placing the chip 30 in the limiting groove 140 .

[0074] The chip 30 and the package carrier 20 corresponding to the limiting groove 140 can be bonded together by an adhesive layer. Specifically, the chip 30 can be placed in the limiting groove 140 with the side where the pins 310 are arranged facing away from the package carrier 20 .

[0075] Step S14 , performing a plastic encapsulation process on the chip 30 to form a packaging layer 40 for encapsulating the chip 30 located in the limiting groove 140 .

[0076] Step S15 , removing the packaging carrier 20 .

[0077] In this step, the temporary bonding layer is removed by laser irradiation or heating treatment, so that the packaging carrier 20 is separated from the chip packaging auxiliary mold 10, the chip 30 and the packaging layer 40, so as to facilitate the removal of the packaging carrier 20.

[0078] Step S16 , manufacturing a redistribution layer 50 electrically connected to the pins 310 of the chip 30 .

[0079] A redistribution layer 50 electrically connected to the pins 310 of the chip is fabricated on the side where the chip pins 310 are located.

[0080] Step S17, removing the chip packaging auxiliary mold 10 and obtaining the packaged chip.

[0081] In this embodiment, an isolation layer 120 is further provided on the surface of the mold body 110, and the packaging structure after the redistribution layer is made is subjected to low temperature treatment to separate the isolation layer 120 from the packaging layer 40, remove the chip packaging auxiliary mold 10 and obtain the packaged chip. The temperature range of the low temperature treatment is greater than or equal to -20°C to less than or equal to 10°C. For example, the temperature of the low temperature treatment includes -20°C, -18.5°C, -15°C, -13°C, -11.5°C, -9°C, -6.4°C, -5°C, -3°C, -0°C, 2°C, 5°C, 8°C and 10°C.

[0082] In this embodiment, after step S17 , the packaged chips may be cut into packaged chips including only a single chip.

[0083] The above chip packaging method uses the grid through hole 130 to cooperate with the packaging carrier 20 to form a limiting groove 140 for limiting the chip 30, thereby improving the problem of displacement of the chip 30 during the packaging process, thereby reducing the difficulty of subsequent process technology and improving the yield of chip packaging. On the other hand, the chip packaging auxiliary mold 10 can be reused, which can reduce the manufacturing cost of chip packaging.

[0084] This embodiment also provides a packaged chip manufactured by the above-mentioned chip packaging method. The packaging process adopted by the packaged chip can reduce the production cost while ensuring the yield, so that the packaged chip has a certain price advantage, thereby improving its market competitiveness.

[0085] The embodiment of the present application provides a chip packaging auxiliary mold, a chip packaging method and a packaged chip. In the chip packaging auxiliary mold, the grid through holes of the mold body cooperate with the packaging carrier to form a limiting groove for limiting the chip, thereby improving the problem of chip displacement during the packaging process, thereby reducing the difficulty of subsequent process technology and improving the yield of chip packaging. On the other hand, an isolation layer is set on the surface of the mold body, and after the chip is packaged, the chip packaging auxiliary mold can be taken out by separating the isolation layer and the packaging layer, which is convenient for the reuse of the chip packaging auxiliary mold and reduces the manufacturing cost of chip packaging.

[0086] The above description is only the preferred embodiment of the present application and is not intended to limit the present application. For those skilled in the art, the present application may have various modifications and variations. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip packaging auxiliary mold, characterized in that: The chip packaging auxiliary mold comprises: A mold body, wherein the mold body is in a grid shape, and the grid through holes in the mold body cooperate with the packaging carrier to form a limiting groove for limiting the chip; The chip packaging auxiliary mold further includes an isolation layer, which is located on the surface of the mold body and includes a graphene layer, wherein the isolation layer has a different thermal expansion coefficient from the packaging layer of the packaging chip.

2. The chip packaging auxiliary mold according to claim 1, characterized in that: The mold body includes a plurality of first mold bars arranged along a first direction and a plurality of second mold bars arranged along a second direction, and the first mold bars and the second mold bars enclose the grid through holes.

3. The chip packaging auxiliary mold according to claim 2, characterized in that: The first direction and the second direction are perpendicular to each other.

4. The chip packaging auxiliary mold according to claim 2, characterized in that: A plurality of the first mold bars are arranged at equal intervals along the first direction, and a plurality of the second mold bars are arranged at equal intervals along the second direction.

5. The chip packaging auxiliary mold according to claim 2, characterized in that: The first mold bar and the second mold bar are made of the same material.

6. The chip packaging auxiliary mold according to claim 1, characterized in that: The mold body is an integrally formed structure.

7. The chip packaging auxiliary mold according to any one of claims 1 to 6, characterized in that: The average linear expansion coefficient of the material of the mold body at a temperature of 20-300°C is less than 5.5*10 -6 / ℃.

8. The chip packaging auxiliary mold according to any one of claims 1 to 6, characterized in that: The elastic modulus of the material of the mold body is greater than 10 5 Mpa, the tensile strength of the mold body is greater than 480Mpa, and the hardness of the mold body is greater than 120HV.

9. The chip packaging auxiliary mold according to any one of claims 1 to 6, characterized in that: The material of the mold body includes Invar alloy.

10. The chip packaging auxiliary mold according to any one of claims 1 to 6, characterized in that: In the direction of penetrating the grid through hole, the mold body includes a first side and a second side opposite to each other, and the mold body is further provided with an introduction structure facing the grid through hole on the first side enclosing the grid through hole.

11. The chip packaging auxiliary mold according to claim 10, characterized in that: The lead-in structure includes a chamfer.

12. The chip packaging auxiliary mold according to claim 10, characterized in that: The thickness of the isolation layer ranges from greater than or equal to 1 nm to less than or equal to 10 nm.

13. The chip packaging auxiliary mold according to claim 10, characterized in that: In the connection direction of adjacent grid through holes, the width of the mold body between adjacent grid through holes ranges from greater than or equal to 10 um to less than or equal to 1000 um.

14. A chip packaging method, characterized in that: The method comprises: Provide a packaging loading plate and a chip packaging auxiliary mold as described in any one of claims 1 to 13; The chip packaging auxiliary mold is attached to the packaging carrier, and the grid through holes of the chip packaging auxiliary mold and the packaging carrier cooperate to form a limiting groove; Placing the chip in the limiting groove; Performing a plastic encapsulation process on the chip to form an encapsulation layer for encapsulating the chip located in the limiting groove; removing the packaging carrier; Making a redistribution layer electrically connected to the pins of the chip; The chip packaging auxiliary mold is removed to obtain a packaged chip.

15. The chip packaging method according to claim 14, characterized in that: In the direction of penetrating the grid through holes, the mold body includes a first side and a second side opposite to each other, and the step of attaching the chip packaging auxiliary mold to the packaging carrier, wherein the chip packaging auxiliary grid through holes and the packaging carrier cooperate to form a limiting groove includes: The second side of the mold body is attached to the packaging carrier, and the grid through holes of the mold body and the packaging carrier cooperate to form a limiting groove; The step of placing the chip in the limiting groove comprises: The chip is placed in the limiting groove with one side of the chip arrangement pins facing away from the packaging carrier.

16. The chip packaging method according to claim 15, characterized in that: An isolation layer is also provided on the surface of the mold body, and the step of making a redistribution layer electrically connected to the pins of the chip comprises: Making a redistribution layer connected to the pins on one side of the chip where the pins are arranged; The step of removing the chip packaging auxiliary mold to obtain the packaged chip includes: The packaging structure after the redistribution layer is made is subjected to low-temperature treatment to separate the isolation layer from the packaging layer, remove the chip packaging auxiliary mold and obtain the packaged chip, wherein the temperature range of the low-temperature treatment is greater than or equal to -20°C to less than or equal to 10°C.

17. A packaged chip, characterized in that: The packaged chip is manufactured using the chip packaging method described in any one of claims 14-16.

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