Systems and methods for adaptive temperature protection of memory controllers

Abstract

This application relates to adaptive temperature protection for memory controllers. In some cases, the memory system may include a set of temperature sensors distributed across the memory system. The set of temperature sensors can be used to monitor or model the temperature of one or more segments of the memory system. After determining that the temperature of a segment exceeds a threshold, the memory system may employ one or more mitigation techniques to reduce the temperature of that segment or the rate of temperature change. For example, the memory system may reduce the clock frequency corresponding to that segment while maintaining a separate clock frequency for other segments of the memory system. Alternatively, the memory system may transfer data or other information from the segment to separate segments.

Description

[0001] Cross-reference

[0002] This patent application claims priority to U.S. Patent Application No. 17 / 929,963, filed September 6, 2022, entitled “Adaptive Temperature Protection for a Memory Controller”, which is assigned to its assignee and is expressly incorporated herein by reference. Technical Field

[0003] The technical field relates to adaptive temperature protection for memory controllers. Background Technology

[0004] Memory devices are widely used to store information in various electronic devices such as computers, user devices, wireless communication devices, cameras, digital displays, and the like. Information is stored by programming memory cells within the memory device into various states. For example, a binary memory cell can be programmed into one of two supported states, typically represented by logic 1 or logic 0. In some instances, a single memory cell can support more than two states, any of which can be stored. To access the stored information, components can read (e.g., sense, detect, retrieve, identify, determine, evaluate) the states stored in the memory device. To store information, components can write (e.g., program, set, assign) the states in the memory device.

[0005] Various types of memory devices exist, including magnetic hard disks, random access memory (RAM), read-only memory (ROM), dynamic RAM (DRAM), synchronous dynamic RAM (SDRAM), static RAM (SRAM), ferroelectric RAM (FeRAM), magnetic RAM (MRAM), resistive RAM (RRAM), flash memory, phase-change memory (PCM), autoselect memory, chalcogenide memory technology, NOR and NAND memory devices, and others. Memory cells can be described according to volatile or non-volatile configurations. Memory cells configured in a non-volatile configuration can maintain their stored logic state for a long time even without external power. Memory cells configured in a volatile configuration may lose their stored state when disconnected from external power. Summary of the Invention

[0006] Describe a system. The system may include: a substrate comprising: a first circuit configured to transmit signaling indicating a first command and first data according to a first protocol; a plurality of second circuits, each configured to couple to one or more memory devices and to transmit signaling indicating a second command and second data according to a second protocol, wherein each of a plurality of segments of the substrate includes at least one of the plurality of second circuits; a plurality of sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; a second circuit configured to generate a plurality of clock signals, each clock signal associated with a corresponding segment of the plurality of segments of the substrate; and logic configured to: determine, at least in part, whether the temperature of a first segment of the plurality of segments of the substrate exceeds a threshold based on the corresponding temperature sensed by the plurality of sensors; modify, at least in part, the frequency of the first clock signal associated with the first segment relative to the frequency of a second clock signal associated with a second segment among the plurality of clock signals, based at least in part on the temperature of the first segment exceeding the threshold; and operate the system at least in part based on the modified frequency of the first clock signal and the frequency of the second clock signal.

[0007] Describe a system. The system may include: a substrate comprising: a first circuit configured to transmit signaling indicating a first command and first data according to a first protocol; a plurality of second circuits, each configured to couple to one or more memory devices and to transmit signaling indicating a second command and second data according to a second protocol, wherein each of a plurality of segments of the substrate includes at least one of the plurality of second circuits; a plurality of caches; a first logic configured to access the plurality of caches; a plurality of sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; and a second logic configured to: determine, at least in part, based on the corresponding temperature sensed by the plurality of sensors, whether the temperature of a first segment of the plurality of segments of the substrate exceeds a threshold; and modify, at least in part, based on the temperature of the first segment exceeding the threshold, a corresponding parameter among a plurality of parameters associated with an indication to write to one or more physical addresses of the caches in the plurality of caches.

[0008] Describe a system. The system may include: a substrate comprising: a first circuit configured to transmit signaling indicating a first command and first data according to a first protocol; a plurality of second circuits, each configured to couple to one or more memory devices and to transmit signaling indicating a second command and second data according to a second protocol, wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits; a plurality of caches; a first logic configured to access the plurality of caches; a plurality of sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; a second circuit configured to generate a plurality of clock signals, each clock signal associated with a corresponding segment of the plurality of segments of the substrate; and a second logic configured to: determine whether the rate of change of temperature of a first segment of the plurality of segments of the substrate exceeds a first threshold and whether the temperature of the first segment exceeds a second threshold; modify a parameter among a plurality of parameters associated with an indication of writing to one or more physical addresses of the caches in the plurality of caches, based at least in part on the rate of change of temperature of the first segment and the temperature of the first segment; and operate the system based at least in part on the modified parameter.

[0009] Describe a method. The method may include: using first circuitry on a substrate to convey first signaling indicating a first command and first data according to a first protocol; writing at least a subset of the first data using a plurality of caches according to a physical address associated with a corresponding command in the first command; using a plurality of second circuitry on the substrate and together with a plurality of memory devices to convey second signaling indicating a second command and second data according to a second protocol, wherein conveying the second signaling includes reading at least a portion of the subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuitry; sensing a corresponding temperature at the corresponding location of the substrate using a plurality of sensors located at the corresponding location; at a logic location on the substrate, determining whether the temperature of a first segment of the plurality of segments of the substrate satisfies a threshold condition based at least in part on the corresponding temperature sensed at the corresponding location; and modifying a corresponding parameter among a plurality of parameters associated with an indication to write to one or more of the physical addresses of the caches in the plurality of caches, based at least in part on the determination that the temperature of the first segment satisfies the threshold condition.

[0010] Describe a method. The method may include: using first circuitry on a substrate to convey first signaling indicating a first command and first data according to a first protocol; writing at least a subset of the first data using a plurality of caches according to a physical address associated with a corresponding command in the first command; using a plurality of second circuitry on the substrate and together with a plurality of memory devices to convey second signaling indicating a second command and second data according to a second protocol, wherein conveying the second signaling includes reading at least a portion of the subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuitry; using a cache located at the corresponding location on the substrate. Multiple sensors sense corresponding temperatures at corresponding locations on the substrate; at a logic location on the substrate, it is determined, at least in part, whether the temperature of a first segment of the plurality of segments of the substrate meets a threshold based on the corresponding temperature sensed at the corresponding location; at a second circuit configured to generate a plurality of clock signals, each of the plurality of clock signals being associated with a segment of the plurality of segments of the substrate, the frequency of a first clock signal associated with the first segment is modified relative to the frequency of a second clock signal associated with a second segment, at least in part based on the determination that the temperature of the first segment meets the threshold; and the plurality of second circuits are operated at least in part based on the frequency of the first clock signal and the frequency of the second clock signal. Attached Figure Description

[0011] Figure 1 This document describes an example of a system that supports adaptive temperature protection for memory controllers, based on the examples disclosed herein.

[0012] Figure 2 This document describes an example of a system that supports adaptive temperature protection for memory controllers, based on the examples disclosed herein.

[0013] Figure 3 This document describes an example of a timing diagram supporting adaptive temperature protection for a memory controller, based on the examples disclosed herein.

[0014] Figure 4 A block diagram is shown illustrating a memory expander that supports adaptive temperature protection for a memory controller, based on examples disclosed herein.

[0015] Figure 5 and 6 The flowchart illustrates one or more methods for adaptive temperature protection for memory controllers, based on the examples disclosed herein. Detailed Implementation

[0016] Some memory systems may include interfaces (e.g., compute fast link (CXL) interfaces) designed for use between a host system and multiple memory devices (e.g., multiple memory dies) of the memory system. For example, a host system can store and access large amounts of data across multiple memory devices at high data transfer rates via these interfaces. Therefore, the temperature of components of the interface associated with a first memory device receiving a relatively large number of access operations (e.g., a first cache or memory controller for the first memory device) can increase more rapidly than the temperature of components of the interface associated with a second memory device receiving a relatively small number of access operations (e.g., a second cache or memory controller for the second device). In some cases, if the memory system detects a high temperature in the components of the interface, the memory system may implement one or more mitigation techniques to reduce or alleviate the temperature across the entire interface, such as suppressing the clock frequency or clock speed of the memory system. However, this mitigation technique may reduce the processing speed of other memory devices or components of the system that may not experience high temperatures (e.g., due to uneven distribution of access operations). Therefore, methods to improve the efficiency of mitigation techniques are desired.

[0017] As described herein, a memory system (e.g., a CXL memory system) may include a set of temperature sensors distributed across the substrate of the memory system. This set of temperature sensors can be used to monitor or model the temperature of one or more segments of the interface. Upon determining that the temperature of a segment exceeds a threshold, the memory system may employ one or more mitigation techniques to reduce the temperature of the segment or the rate of temperature change. For example, the memory system may reduce the clock frequency corresponding to the segment while maintaining a separate clock frequency for other segments of the memory system. Alternatively, the memory system may transfer data or other information (e.g., control information, such as an indication of the physical address of the data) from the segment to a separate segment. Therefore, the memory system can efficiently manage high-temperature segments without adversely affecting other segments.

[0018] First, refer to Figure 1 The features of this disclosure are described in the context of the system and the bare die. (See references...) Figures 2 to 3 The features of this disclosure are described in the context of the memory system and timing diagrams. (See references...) Figures 4 to 6 The device diagrams and flowcharts described in relation to adaptive temperature protection for memory controllers further illustrate and describe these and other features of this disclosure, and are referred to in connection with the device diagrams and flowcharts.

[0019] Figure 1This document describes an example of a system 100 supporting adaptive temperature protection for a memory controller, based on the examples disclosed herein. System 100 may include a host device 105, a memory device 110, and multiple channels 115 coupling the host device 105 and the memory device 110. System 100 may include one or more memory devices 110, but aspects of the one or more memory devices 110 may be described in the context of a single memory device (e.g., memory device 110).

[0020] System 100 may include portions of an electronic device, such as a computing device, mobile computing device, wireless device, graphics processing device, vehicle, or other system. For example, system 100 may describe aspects of a computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, or the like. Memory device 110 may be a component of system 100 operable to store data for use by one or more other components of system 100.

[0021] A portion of system 100 may be an example of host device 105. Host device 105 may be an example of a processor (e.g., circuitry, processing circuitry, processing component) within a device that uses memory to execute processes (e.g., within a computing device, mobile computing device, wireless device, graphics processing device, computer, laptop computer, tablet computer, smartphone, cellular phone, wearable device, internet-connected device, vehicle controller, system-on-a-chip (SoC), or some other fixed or portable electronic device, and other examples). In some examples, host device 105 may refer to the hardware, firmware, software, or any combination thereof that implements the functions of external memory controller 120. In some examples, external memory controller 120 may be referred to as a host (e.g., host device 105).

[0022] Memory device 110 may be a separate device or component operable to provide physical memory address / space that can be used or referenced by system 100. In some instances, memory device 110 may be configured to work with one or more different types of host devices. Signaling between host device 105 and memory device 110 may be operable to support one or more of the following: modulation schemes for modulated signals, various pin configurations for transmitting signals, various form factors of the physical packages of host device 105 and memory device 110, clock signaling and synchronization, timing conventions, or other functions between host device 105 and memory device 110.

[0023] Memory device 110 is operable to store data for components of host device 105. In some instances, memory device 110 (e.g., operating as an auxiliary device to host device 105, or as a slave device to host device 105) can respond to and execute commands provided by host device 105 via external memory controller 120. Such commands may include one or more of the following: write commands for write operations, read commands for read operations, refresh commands for refresh operations, or other commands.

[0024] The host device 105 may include an external memory controller 120, a processor 125, a basic input / output system (BIOS) component 130, or one or more other components such as one or more peripheral components or one or more input / output controllers. The components of the host device 105 may be coupled to each other via bus 135.

[0025] Processor 125 is operable to provide functionality (e.g., control functionality) to system 100 or host device 105. Processor 125 may be a general-purpose processor, digital signal processor (DSP), application-specific integrated circuit (ASIC), field-programmable gate array (FPGA) or other programmable logic device, discrete gate or transistor logic, discrete hardware components, or any combination of these components. In such instances, processor 125 may be an instance of a central processing unit (CPU), graphics processing unit (GPU), general-purpose GPU (GPGPU), or SoC, and other instances. In some instances, external memory controller 120 may be implemented by or be part of processor 125.

[0026] BIOS component 130 may be a software component containing a BIOS operating as firmware, which can initialize and run various hardware components of system 100 or host device 105. BIOS component 130 may also manage data flow between processor 125 and various components of system 100 or host device 105. BIOS component 130 may contain instructions (e.g., programs, software) stored in one or more of read-only memory (ROM), flash memory, or other non-volatile memory.

[0027] Memory device 110 may include a device memory controller 155 and one or more memory dies 160 (e.g., memory chips) for supporting data storage capacity (e.g., desired capacity, specified capacity). Each memory die 160 (e.g., memory die 160-a, memory die 160-b, memory die 160-N) may include a local memory controller 165 (e.g., local memory controller 165-a, local memory controller 165-b, local memory controller 165-N) and a memory array 170 (e.g., memory array 170-a, memory array 170-b, memory array 170-N). Memory array 170 may be a collection of memory cells (e.g., one or more grids, one or more banks, one or more dies, one or more segments), wherein each memory cell is operable to store one or more data bits. Memory device 110 including two or more memory dies 160 may be referred to as a multi-die memory, a multi-die package, a multi-chip memory, or a multi-chip package.

[0028] The memory die 160 may be an example of a two-dimensional (2D) memory cell array or an example of a three-dimensional (3D) memory cell array. In some instances, the 2D memory die 160 may contain a single memory array 170. In some instances, the 3D memory die 160 may contain two or more memory arrays 170, which may be stacked one on top of the other or positioned close to each other (e.g., relative to a substrate). In some instances, the memory arrays 170 in the 3D memory die 160 may be referred to as or otherwise comprise different groups (e.g., layers, hierarchies, stacks, dies). The 3D memory die 160 may contain any number of stacked memory arrays 170 (e.g., two heights, three heights, four heights, five heights, six heights, seven heights, eight heights). In some 3D memory dies 160, different layers may share common access lines, such that some layers may share one or more of word lines, digital lines, or board lines.

[0029] The device memory controller 155 may include components (e.g., circuitry, logic) operable to control the operation of the memory device 110. The device memory controller 155 may include hardware, firmware, or instructions that enable the memory device 110 to perform various operations, and is operable to receive, transmit, or execute commands, data, or control information associated with components of the memory device 110. The device memory controller 155 is operable to communicate with one or more of an external memory controller 120, one or more memory dies 160, or a processor 125. In some instances, the device memory controller 155 may be used in conjunction with a local memory controller 165 of the memory die 160 to control the operation of the memory device 110 described herein.

[0030] In some instances, memory device 110 may communicate with host device 105 information (e.g., data, commands, or both). For example, memory device 110 may receive a write command instructing memory device 110 to store data received from host device 105, or a read command instructing memory device 110 to provide data stored in memory die 160 to host device 105, and perform other types of information communication.

[0031] Local memory controller 165 (e.g., local to memory die 160) may include components (e.g., circuitry, logic) operable to control the operation of memory die 160. In some instances, local memory controller 165 is operable to communicate with device memory controller 155 (e.g., to receive or transmit data or commands, or both). In some instances, memory device 110 may not include device memory controller 155, and local memory controller 165 or external memory controller 120 may perform the various functions described herein. Thus, local memory controller 165 is operable to communicate with device memory controller 155, with other local memory controllers 165, or directly with external memory controller 120 or processor 125, or any combination thereof. Examples of components that may be included in device memory controller 155 or local memory controller 165 or both may include a receiver for receiving signals (e.g., from external memory controller 120), a transmitter for transmitting signals (e.g., to external memory controller 120), a decoder for decoding or demodulating received signals, an encoder for encoding or modulating signals to be transmitted, or various other components operable to support the described operation of device memory controller 155 or local memory controller 165 or both.

[0032] External memory controller 120 is operable to enable communication of information (e.g., data, commands, or both) between components of system 100 (e.g., between components of host device 105, such as processor 125, and memory device 110). External memory controller 120 can process (e.g., translate, transpose) the communication exchanged between components of host device 105 and memory device 110. In some instances, the external memory controller 120, or other components of system 100 or host device 105, or its functionality as described herein, may be implemented by processor 125. For example, external memory controller 120 may be hardware, firmware, or software, or some combination thereof, implemented by processor 125, system 100, or other components of host device 105. Although external memory controller 120 is depicted as external to memory device 110, in some instances, external memory controller 120, or its functionality as described herein, may be implemented by one or more components of memory device 110 (e.g., device memory controller 155, local memory controller 165), or vice versa.

[0033] Components of host device 105 may exchange information with memory device 110 using one or more channels 115. Channels 115 are operable to support communication between external memory controller 120 and memory device 110. Each channel 115 may be an example of a transmission medium carrying information between host device 105 and memory device 110. Each channel 115 may include one or more signal paths (e.g., transmission medium, conductors) between terminals associated with components of system 100. Signal paths may be examples of conductive paths operable to carry signals. For example, channel 115 may be associated with a first terminal (e.g., including one or more pins, including one or more pads) at host device 105 and a second terminal at memory device 110. Terminals may be examples of conductive input or output points of devices of system 100, and terminals are operable to serve as portions of channels.

[0034] Channel 115 (and associated signal paths and terminals) can be used to convey information using one or more interfaces. For example, channel 115 may contain channel links, such as CXL links, Peripheral Component Interconnect Fast (PCIe) links, or other PCIe-based interface links. In some cases, channel 115 may contain one or more serial data paths (e.g., differential signaling pairs).

[0035] In some cases, the memory system 110 may include a set of temperature sensors distributed across the memory system 110. This set of temperature sensors can be used to monitor or model the temperature of one or more segments of the memory system 110 (e.g., one or more memory dies 160 or an interface of the memory system 110 for communicating with one or more memory dies 160). After determining that the temperature of a segment exceeds a threshold, the memory system 110 may employ one or more mitigation techniques to reduce the temperature of the segment or the rate of temperature change. For example, the memory system 110 may reduce the clock frequency corresponding to the segment while maintaining a separate clock frequency for other segments of the memory system 110. Alternatively or additionally, the memory system 110 may transfer data or other information (e.g., control information, such as an indication of the physical address of the data) from the segment to a separate segment. Therefore, the memory system 110 can efficiently manage high-temperature segments without adversely affecting other segments. Although Figure 1 Memory devices with DRAM architectures can be described, but the techniques described herein can be applied to other memory systems, such as memory systems using other types of volatile or non-volatile memory cells.

[0036] Figure 2 This document describes an example of a system 200 that supports adaptive temperature protection for a memory controller, based on the examples disclosed herein. System 200 may be an example of a CXL memory device that can use interface 210 to communicate commands and data to a host system (e.g., see reference 1). Figure 1The host system 105 described herein. Interface 210 can transmit data to the host device via interface 215 according to a protocol (e.g., the CXL protocol). System 200 may be disposed on substrate 205 and may include a set of caches 220, each cache 220 coupled to cache controller 225. The system may further include a set of memory controllers 265, each memory controller 265 coupled to a corresponding memory device (not shown) via a corresponding memory interface 270. In some instances, interface 210 may be configured to use cache controller 225, the set of memory controllers 265, or both to process commands, data, or both to store data in cache 220, memory device, or any combination thereof. For example, interface 210 may receive a command to retrieve data associated with a logical address in a logical address space. In some cases, system 200 may store data at a physical address (e.g., device physical address (DPA)) of the memory device corresponding to the logical address. Interface 210 may determine the DPA of the data associated with the logical address of the command being executed. Interface 210 can communicate with memory controller 265, which is coupled to a memory device associated with the DPA. Memory controller 265 can retrieve data and send the data to interface 210 (e.g., via cache 220). Alternatively, the data can be stored in cache 220 (e.g., the system 200 may have previously cached the data). Therefore, cache controller 225 can retrieve data from cache 220 and transfer the data to interface 210.

[0037] System 200 may include a set of segments 230 distributed across substrate 205. Segments 230 may correspond to regions of substrate 205, such as... Figure 2 As depicted herein, and may include one or more components of system 200. For example, segment 230 may include one or more caches 220, one or more memory controllers 265, or any combination thereof. Although Figure 2 An example is depicted in which segment 230 includes both a cache 220 and a set of memory controllers 265, but this arrangement is exemplary because other arrangements (e.g., segment 230 without cache 220 or without memory controllers 265) are possible.

[0038] Segment 230, or a portion thereof, may operate according to a corresponding clock among a plurality of clocks of system 200. For example, operations performed by components of segment 230 may be synchronized with or controlled by the clock frequency (e.g., speed) corresponding to the clock of segment 230. In some cases, a first clock corresponding to a first segment 230 may operate according to a frequency different from a second clock of a second segment 230. For example, the frequency of the second clock may be lower than the frequency of the first clock. Therefore, the operation of components in the second segment 230 may be slower than the operation of components in the first segment 230.

[0039] In some cases, system 200 may include clock distribution circuitry 235 configured to control and distribute clock groups within system 200. For example, clock distribution circuitry 235 may manage the frequency or other timing aspects of each clock in the clock group and may supply corresponding clock signals to each segment 230 (e.g., to each component in each segment 230). In some instances, clock distribution circuitry may be configured to modify clocks in the clock group, for example, by decreasing or increasing the clock frequency (e.g., speed). In such examples, clock distribution circuitry may supply modified clock signals to segments 230 corresponding to the modified clocks.

[0040] System 200 may include a set of temperature sensors 240 distributed across substrate 205. Each temperature sensor 240 may be configured to determine (e.g., measure) the temperature of a region of substrate 205 surrounding the temperature sensor 240. In some cases, the temperature sensor 240 may be associated with segment 230 such that the temperature sensed by the temperature sensor provides an indication of the temperature of the associated segment 230.

[0041] Segment 230 may include multiple temperature sensors 240, and the temperature of segment 230 may be determined using multiple temperature sensors. Alternatively, segment 230 may not include any temperature sensors. In such cases, system 200 may determine the temperature of segment 230 using the temperatures of nearby segments 230 or nearby temperature sensors 240 (e.g., temperature sensors corresponding to different segments 230). For example, system 200 may generate a thermal map indicating the temperature of each segment. In some instances, temperature sensors 240 may report the measured corresponding temperature to components of system 200 (e.g., firmware stored in controller 275).

[0042] In some cases, the system can monitor the temperature of segment 230 and determine whether the temperature of segment 230 exceeds a threshold (e.g., whether segment 230 may be overheating). If system 200 determines that the temperature of the segment exceeds the threshold, then system 200 can perform one or more operations to reduce the temperature of the segment or mitigate potential damage or corruption to the stored data. For example, system 200 can modify the clock frequency of segment 230, modify a set of operating parameters of components of segment 230, transfer data or other information from segment 230, or any combination thereof.

[0043] To modify the clock frequency of segment 230, clock distribution circuitry 235 may reduce (e.g., suppress) the clock frequency of a first clock associated with segment 230 (e.g., the clock associated with cache 220 of segment 230, the clock associated with memory controller 265 of segment 230, or both) relative to a second clock associated with segment 230 (e.g., the clock associated with cache 220 of segment 230, the clock associated with memory controller 265 of segment 230, or both). Therefore, system 200 may operate segment 230 according to the first clock frequency and may operate the second segment 230 according to the second clock frequency. In some cases, suppressing the clock frequency of segment 230 may reduce the temperature of segment 230.

[0044] Alternatively, system 200 may modify one or more parameters corresponding to segment 230 having a temperature above a threshold. For example, cache 220 of segment 230 may store data associated with a set of DPAs corresponding to physical addresses of a memory device coupled to a memory controller 265 associated with cache 220. In some cases, cache 220 may additionally store a set of parameters associated with each DPA, such as reserved bits, refresh bits, bypass bits, or any combination thereof. To modify the parameters of segment 230, system 200 may set (e.g., assert) one or more of the reserved bits, refresh bits, or bypass bits for each DPA of cache 220.

[0045] In some cases, setting the refresh bit of DPA can indicate that data associated with DPA can be transferred (e.g., refreshed) from cache 220 to the memory device associated with DPA. Therefore, after setting the refresh bit of DPA, system 200 can transfer the data associated with DPA to the corresponding physical address of the memory device.

[0046] In some cases, setting the reserved bit of DPA can indicate that the data associated with DPA can be retained in cache 220 (e.g., the data can be excluded from being evicted from cache 220). Therefore, after setting the reserved bit of DPA, system 200 can avoid (e.g., suppress) transferring the data associated with DPA to the corresponding physical address of the memory device. Thus, if system 200 receives a command to access the data associated with DPA (e.g., via interface 210), then system 200 can retrieve the data from cache 220 instead of from the physical address of the memory device.

[0047] In some cases, setting the bypass bit of DPA can instruct bypassing cache 220 and retrieving data associated with DPA directly from the corresponding physical address of the memory device coupled to memory controller 265. For example, upon receiving a command for data associated with DPA (e.g., via interface 210), system 200 can retrieve the data from the memory device and subsequently transfer the data.

[0048] In some instances, after determining that the temperature of the first segment 230 exceeds a threshold, the system 200 may transfer data or DPA associated with the first segment 230 to a second segment 230 (e.g., a segment 230 with a temperature below the threshold). For example, the system 200 may reassign DPAs from one or more caches 220 of the first segment 230 to one or more caches 220 of the second segment 230. In such examples, the system 200 (e.g., via cache controller 225) may retrieve DPAs from one or more caches 220 of the first segment 230 and write the DPAs to one or more caches 220 of the second segment. In some cases, the system 200 may additionally transfer data associated with DPAs from a memory device coupled to a memory controller 265 of the first segment 230 to a memory device coupled to a memory controller 265 of the second segment. Alternatively, after determining that the temperature of the first segment 230 exceeds a threshold, the system 200 may bypass the cache of one or more caches 220 of the first segment 230.

[0049] Figure 3 This document describes an example of timing diagram 300 supporting adaptive temperature protection for a memory controller, based on the examples disclosed herein. Timing diagram 300 may illustrate various segments of the memory system (e.g., segment 230 of system 200, as shown in the reference). Figure 2 (Description) Temperature 305 during time 310 during memory system operation. For example, timing diagram 300 may illustrate the temperature of the first segment 320, the temperature of the second segment 325, and the temperature of the third segment 330.

[0050] Referring to the temperature of the first segment 320, the memory system can measure or determine (e.g., using temperature sensor group 240 or the resulting thermal mapping, such as reference) Figure 2 (Description) Temperature of the first segment 320 during the first interval 335. In some cases, the memory system may determine that the temperature of the first segment 320 does not exceed a temperature threshold 315 during the first interval 335.

[0051] However, based on the rate of temperature change of the first segment 320 during the first interval 335, the memory system can determine or calculate a prediction or estimate of the temperature of the first segment 320 after the first interval 335. For example, the memory system can use the same or similar rate of temperature change of the first segment 320 during the first interval 335 to calculate a predicted temperature trend 350. In some cases, the calculated temperature trend 350 may exceed a temperature threshold 315. Therefore, to prevent or mitigate damage to the memory system associated with the temperature of the first segment 320 exceeding the temperature threshold 315, the memory system may perform one or more mitigation techniques to mitigate the temperature of the first segment 320 before the temperature of the first segment 320 exceeds the threshold 315. In some cases, the degree of mitigation techniques may be commensurate with the calculated temperature trend 350. That is, the memory system may combine mitigation techniques, such as those mentioned above. Figure 2 Description. For example, if the calculated temperature trend 350 greatly exceeds the temperature threshold 315 or the calculated temperature trend 350 is predicted to exceed the temperature threshold within a relatively short time, then the memory system may bypass the first segment (e.g., using reserved bits, bypass bits, or both), or may transfer data, DPA, or both to a segment with a lower temperature.

[0052] Alternatively, if the predicted temperature trend of the calculated segment exceeds the threshold 315 over a relatively long period of time (e.g., compared to the calculated temperature trend 350), the memory system may perform a relatively mild mitigation technique. For example, referring to the temperature of the second segment 325, the memory system may measure or determine (e.g., using the temperature sensor group 240 or the generated thermal map, such as reference) Figure 2 (Description) Temperature of the second segment 325 during the second interval 340. In some cases, the memory system may determine that the temperature of the second segment 325 does not exceed a temperature threshold 315 during the second interval 340. However, the memory system may use the same or similar rate of change of the temperature of the second segment 325 during the second interval 340 to calculate a predicted temperature trend 355. Based on the temperature trend 355, the memory system may suppress the clock frequency of the second segment (e.g., to a second clock frequency). For example, the memory system may operate the second segment according to the second clock frequency, which may mitigate the temperature of the second segment 325 or the rate of change of the temperature of the second segment 325.

[0053] In some instances, both the temperature of a segment and the rate of change of that temperature can determine the mitigation techniques to be performed by the memory system. For example, the temperature of the third segment 330 may be lower than the temperatures of the first segment 320 and the second segment 325, and may have a higher rate of change during the third interval 345. Therefore, the calculated temperature trend 360 can be predicted to exceed the threshold 315 for a relatively short time compared to temperature trend 355 and a relatively long time compared to temperature trend 350. Therefore, the memory system can suppress the clock frequency of the third segment to a lower frequency compared to the second segment (e.g., to a third clock frequency lower than the second clock frequency). For example, the memory system can operate the third segment according to the third clock frequency, which can mitigate the temperature of the third segment 330 or the rate of change of that temperature. Alternatively or concurrently, the memory system can combine mitigation techniques based on the temperature trend 360. For example, after suppressing the clock frequency of the third segment, the memory system can measure the temperature of the third segment 330 and calculate a second predicted temperature trend to determine whether suppressing the clock frequency will alleviate the temperature of the third segment 330. If the second predicted temperature trend will exceed the threshold of 315, then the memory system can apply additional mitigation techniques, such as setting bypass bits or reserved bits in the third segment.

[0054] Figure 4 A block diagram 400 illustrates a memory expander 420 supporting adaptive temperature protection for a memory controller, based on an example disclosed herein. The memory expander 420 may be used as a reference. Figures 1 to 3 Examples of aspects of the described memory expander. Memory expander 420 or its various components may be examples of components for performing various aspects of adaptive temperature protection for a memory controller, as described herein. For example, memory expander 420 may include command communication component 425, data writing component 430, temperature sensing component 435, temperature processing component 440, parameter adjustment component 445, circuit operation component 450, data transmission component 455, data retrieval component 460, or any combination thereof. Each of these components may communicate directly or indirectly with each other (e.g., via one or more buses).

[0055] Command communication component 425 may be configured or otherwise supported to support means for communicating first signaling indicating a first command and first data using first circuitry on the substrate according to a first protocol. Data writing component 430 may be configured or otherwise supported to support means for writing at least a subset of the first data using a plurality of caches according to a physical address associated with a corresponding command in the first command. In some instances, command communication component 425 may be configured or otherwise supported to support means for communicating second signaling indicating a second command and second data using a plurality of second circuitry on the substrate according to a second protocol and together with a plurality of memory devices, wherein communicating the second signaling includes reading at least a subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of a plurality of segments of the substrate includes at least one of the plurality of second circuitry. Temperature sensing component 435 may be configured or otherwise supported to support means for sensing a corresponding temperature at a corresponding location on the substrate using a plurality of sensors located at corresponding locations on the substrate. Temperature processing component 440 may be configured or otherwise supported for determining, at least in part, at a logic location on the substrate whether the temperature of a first segment of a plurality of segments of the substrate meets a threshold based on a corresponding temperature sensed at a corresponding location. Parameter adjustment component 445 may be configured or otherwise supported for modifying, at least in part, a corresponding parameter of a plurality of parameters associated with an indication of one or more physical addresses of caches written into a plurality of caches, based on the determination that the temperature of the first segment meets the threshold.

[0056] In some instances, parameter adjustment component 445 may be configured or otherwise supported to modify corresponding parameters associated with a first subset of one or more physical addresses to indicate the transfer of corresponding data associated with each physical address of the first subset. In some instances, data writing component 430 may be configured or otherwise supported to transfer data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in a plurality of memory devices.

[0057] In some instances, parameter tuning component 445 may be configured or otherwise supported to support means for modifying a second parameter associated with a second subset of one or more physical addresses to indicate that data associated with the physical addresses is written to the cache. In some instances, data writing component 430 may be configured or otherwise supported to support means for suppressing the transfer of data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in a plurality of memory devices.

[0058] In some instances, parameter tuning component 445 may be configured or otherwise supported for modifying parameters associated with an indication of a physical address to indicate that data associated with the physical address is written to a component of a memory device coupled to a second circuit, wherein access operations associated with said data bypass a cache.

[0059] In some instances, command delivery component 425 may be configured or otherwise supported to support means for receiving signaling from the first circuitry indicating access to data associated with a physical address. In some instances, data retrieval component 460 may be configured or otherwise supported to support means for retrieving data directly from a second circuitry coupled to a memory device according to a second protocol, at least in part based on parameters, wherein the retrieved data is contained by bypassing a cache. In some instances, data transfer component 455 may be configured or otherwise supported to support means for transferring data to the first circuitry, at least in part based on data retrieved from the second circuitry.

[0060] In some instances, data transfer component 455 may be configured or otherwise supported for transferring data representing physical addresses from a first cache of the first segment to a second cache associated with a second segment of a plurality of segments, based at least in part on the temperature of the first segment and the temperature of the second segment.

[0061] In some instances, command communication component 425 may be configured or otherwise supported to support means for communicating first signaling indicating a first command and first data using first circuitry on the substrate according to a first protocol. In some instances, data writing component 430 may be configured or otherwise supported to support means for writing at least a subset of the first data using multiple caches according to a physical address associated with a corresponding command in the first command. In some instances, command communication component 425 may be configured or otherwise supported to support means for communicating second signaling indicating a second command and second data using multiple second circuitry on the substrate according to a second protocol, together with multiple memory devices, wherein communicating the second signaling includes reading at least a subset of the first data to obtain the second data and writing the second data to one or more of the multiple memory devices, and wherein each of the multiple segments of the substrate includes at least one of the multiple second circuitry. In some instances, temperature sensing component 435 may be configured or otherwise supported to support means for sensing a corresponding temperature at a corresponding location on the substrate using multiple sensors located at corresponding locations on the substrate. In some instances, temperature processing component 440 may be configured or otherwise supported to support means for determining, at least in part, at logic on the substrate whether the temperature of a first segment of a plurality of segments of the substrate meets a threshold based on a corresponding temperature sensed at a corresponding location. In some instances, parameter adjustment component 445 may be configured or otherwise supported to support means for modifying, at least in part, the frequency of a first clock signal associated with a second segment at a second circuit configured to generate a plurality of clock signals (each of the plurality of clock signals associated with a segment of the plurality of segments of the substrate) relative to the frequency of a second clock signal associated with a second segment, based at least in part on the determination that the temperature of the first segment meets a threshold. Circuit operation component 450 may be configured or otherwise supported to support means for operating a plurality of second circuits at least in part based on the frequencies of the first clock signal and the second clock signal.

[0062] In some instances, circuit operation component 450 may be configured or otherwise support components for operating a first cache among a plurality of caches associated with a first segment according to the frequency of a first clock signal. In some instances, circuit operation component 450 may be configured or otherwise support components for operating a second cache among a plurality of caches associated with a second segment according to the frequency of a second clock signal, wherein operating the plurality of second circuits is at least in part based on operating the first cache and the second cache.

[0063] In some instances, circuit operation component 450 may be configured or otherwise support components for operating a first portion of a third circuit at a modified frequency according to a first clock signal. In some instances, circuit operation component 450 may be configured or otherwise support components for operating a second portion of a third circuit at a frequency according to a second clock signal, wherein operating a plurality of second circuits is at least partially based on operating the first segment and the second segment.

[0064] In some instances, the modified frequency of the first clock signal is lower than the frequency of the second clock signal.

[0065] Figure 5 The flowchart illustrates a method 500 for adaptive temperature protection for a memory controller, based on examples disclosed herein. Operation of method 500 can be implemented by a memory expander or its components described herein. For example, operation of method 500 can be achieved by referring to... Figures 1 to 4 The described memory expander performs the function. In some instances, the memory expander can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory expander may use dedicated hardware to perform aspects of the described function.

[0066] At 505, the method may include using first circuitry on the substrate to convey first signaling indicating a first command and first data according to a first protocol. Operation 505 may be performed according to the examples disclosed herein. In some examples, aspects of operation 505 may be derived from references... Figure 4 The command described is executed by component 425.

[0067] At 510, the method may include writing at least a subset of the first data using multiple caches according to the physical address associated with the corresponding command in the first command. Operation 510 may be performed according to the examples disclosed herein. In some instances, aspects of operation 510 may be derived from references. Figure 4 The described data is written to component 430 for execution.

[0068] At 515, the method may include using a plurality of second circuits on the substrate according to a second protocol and communicating second signaling indicating a second command and second data together with a plurality of memory devices, wherein communicating the second signaling includes reading at least a subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits. Operation 515 may be performed according to the examples disclosed herein. In some examples, aspects of operation 515 may be provided by reference to Figure 4 The command described is executed by component 425.

[0069] At 520, the method may include sensing a corresponding temperature at a corresponding location on the substrate using multiple sensors positioned at corresponding locations on the substrate. Operation 520 may be performed according to the examples disclosed herein. In some examples, aspects of operation 520 may be derived from references. Figure 4 The temperature sensing component 435 described is implemented.

[0070] At 525, the method may include, at least in part, a logic on the substrate determining whether the temperature of a first segment of a plurality of segments of the substrate satisfies a threshold based on a corresponding temperature sensed at a corresponding location. Operation 525 may be performed according to the examples disclosed herein. In some examples, aspects of operation 525 may be referenced from... Figure 4 The temperature processing component 440 described is executed.

[0071] At 530, the method may include modifying a corresponding parameter among a plurality of parameters associated with an indication of one or more physical addresses of caches written to a plurality of caches, based at least in part on determining that the temperature of the first segment meets a threshold. Operation 530 may be performed according to the examples disclosed herein. In some instances, aspects of operation 530 may be derived from references. Figure 4 The parameter adjustment component 445 described is executed.

[0072] In some instances, the device described herein may perform one or more methods, such as method 500. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0073] Aspect 1: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: conveying first signaling indicating a first command and first data using first circuitry on a substrate according to a first protocol; writing at least a subset of the first data using a plurality of caches according to a physical address associated with a corresponding command in the first command; and conveying second signaling indicating a second command and second data using a plurality of second circuitry on the substrate, together with a plurality of memory devices, according to a second protocol, wherein conveying the second signaling includes reading at least a portion of the subset of the first data to obtain the second data and writing the second data... The data is written to one or more of the plurality of memory devices, and each of the plurality of segments of the substrate includes at least one of the plurality of second circuits; a plurality of sensors located at the respective locations on the substrate are used to sense a corresponding temperature at the respective locations on the substrate; at a logic location on the substrate, it is determined, at least in part, based on the corresponding temperature sensed at the respective locations, whether the temperature of a first segment of the plurality of segments of the substrate meets a threshold; and at least in part based on the determination that the temperature of the first segment meets the threshold, a corresponding parameter of a plurality of parameters associated with an indication of one or more of the physical addresses of the caches written to the plurality of caches is modified.

[0074] Aspect 2: The method, apparatus, or non-transitory computer-readable medium according to Aspect 1 further includes operations, features, circuitry, logic, components, or instructions or any combination thereof for: modifying the corresponding parameters associated with a first subset of the one or more physical addresses to indicate the transfer of corresponding data associated with each physical address of the first subset; and transferring the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the plurality of memory devices.

[0075] Aspect 3: The method, apparatus, or non-transitory computer-readable medium according to Aspect 2 further includes operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: modifying a second parameter associated with a second subset of the one or more physical addresses to indicate that data associated with the physical addresses is written to the cache; and suppressing the transfer of the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the plurality of memory devices.

[0076] Aspect 4: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 3 further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for: modifying the parameter associated with the indication of the physical address to indicate that data associated with the physical address is written to a memory device coupled to a second circuit, wherein the access operation associated with the data bypasses the cache.

[0077] Aspect 5: The method, apparatus, or non-transitory computer-readable medium according to aspect 4 further comprises operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: receiving from the first circuitry a signaling instruction indicating access to data associated with the physical address; retrieving the data directly from the second circuitry coupled to the memory device according to the second protocol, at least in part based on the parameters, wherein bypassing the cache includes retrieving the data; and transferring the data to the first circuitry, at least in part based on the retrieval of the data from the second circuitry.

[0078] Aspect 6: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 1 to 5 further comprises an operation, feature, circuit system, logic, component, or instruction or any combination thereof for transferring data representing a physical address from a first cache of the first segment to a second cache associated with a second segment of the plurality of segments, based at least in part on the temperature of the first segment and the temperature of the second segment.

[0079] Figure 6 The flowchart illustrates a method 600 for adaptive temperature protection for a memory controller, based on examples disclosed herein. Operation of method 600 can be implemented by a memory expander or its components described herein. For example, operation of method 600 can be achieved by referring to... Figures 1 to 4 The described memory expander performs the function. In some instances, the memory expander can execute a set of instructions to control the functional elements of the device to perform the described function. Alternatively, the memory expander may use dedicated hardware to perform aspects of the described function.

[0080] At 605, the method may include using first circuitry on a substrate to convey first signaling indicating a first command and first data according to a first protocol. Operation 605 may be performed according to the examples disclosed herein. In some examples, aspects of operation 605 may be derived from references... Figure 4 The command described is executed by component 425.

[0081] At 610, the method may include writing at least a subset of the first data using multiple caches according to the physical address associated with the corresponding command in the first command. Operation 610 may be performed according to the examples disclosed herein. In some instances, aspects of operation 610 may be derived from references. Figure 4 The described data is written to component 430 for execution.

[0082] At 615, the method may include using a plurality of second circuits on the substrate according to a second protocol and communicating second signaling indicating a second command and second data together with a plurality of memory devices, wherein communicating the second signaling includes reading at least a subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits. Operation 615 may be performed according to the examples disclosed herein. In some examples, aspects of operation 615 may be provided by reference to Figure 4 The command described is executed by component 425.

[0083] At 620, the method may include sensing a corresponding temperature at a corresponding location on the substrate using multiple sensors positioned at corresponding locations on the substrate. Operation 620 may be performed according to the examples disclosed herein. In some examples, aspects of operation 620 may be provided by reference. Figure 4 The temperature sensing component 435 described is implemented.

[0084] At 625, the method may include, at least in part, a logic location on the substrate, determining whether the temperature of a first segment of a plurality of segments of the substrate satisfies a threshold based on a corresponding temperature sensed at a corresponding location. Operation 625 may be performed according to the examples disclosed herein. In some examples, aspects of operation 625 may be referenced from... Figure 4 The temperature processing component 440 described is executed.

[0085] At 630, the method may include, at a second circuit configured to generate a plurality of clock signals (each of the plurality of clock signals associated with a segment of a plurality of segments of a substrate), modifying the frequency of a first clock signal associated with the first segment relative to the frequency of a second clock signal associated with the second segment, at least in part based on determining that the temperature of the first segment meets a threshold. Operation 630 may be performed according to the examples disclosed herein. In some examples, aspects of operation 630 may be provided by reference to... Figure 4 The parameter adjustment component 445 described is executed.

[0086] At 635, the method may include operating a plurality of second circuits at least partially based on the frequency of a first clock signal and the frequency of a second clock signal. Operation 635 may be performed according to the examples disclosed herein. In some examples, aspects of operation 635 may be derived from references... Figure 4The circuit operation component 450 described is executed.

[0087] In some instances, the device described herein may perform one or more methods, such as method 600. The device may include features, circuitry, logic, components, or instructions (e.g., a non-transitory computer-readable medium storing instructions executable by a processor) or any combination thereof for performing aspects of this disclosure:

[0088] Aspect 7: A method, apparatus, or non-transitory computer-readable medium comprising operations, features, circuitry, logic, components, or instructions, or any combination thereof, for: conveying first signaling indicating a first command and first data using first circuitry on a substrate according to a first protocol; writing at least a subset of the first data using a plurality of caches according to a physical address associated with a corresponding command in the first command; and conveying second signaling indicating a second command and second data using a plurality of second circuitry on the substrate, together with a plurality of memory devices, according to a second protocol, wherein conveying the second signaling includes reading at least a portion of the subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of the plurality of segments of the substrate includes the plurality of second circuitry. At least one of the following: using a plurality of sensors located at the respective locations on the substrate to sense the respective temperatures at the respective locations on the substrate; at a logic location on the substrate, determining, at least in part based on the respective temperatures sensed at the respective locations, whether the temperature of a first segment of the plurality of segments of the substrate meets a threshold; at a second circuit configured to generate a plurality of clock signals (each of the plurality of clock signals associated with a segment of the plurality of segments of the substrate), modifying, at least in part based on the determination that the temperature of the first segment meets the threshold, the frequency of a first clock signal associated with the first segment relative to the frequency of a second clock signal associated with the second segment; and operating the plurality of second circuits, at least in part based on the frequency of the first clock signal and the frequency of the second clock signal.

[0089] Aspect 8: The method, apparatus, or non-transitory computer-readable medium according to aspect 7 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for: operating a first cache of the plurality of caches associated with the first segment according to the frequency of the first clock signal; and operating a second cache of the plurality of caches associated with the second segment according to the frequency of the second clock signal, wherein operating the plurality of second circuits is at least partially based on operating the first cache and the second cache.

[0090] Aspect 9: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 7 to 8 further comprises an operation, feature, circuit system, logic, component, or instruction, or any combination thereof, for operating a first portion of a third circuit according to the modified frequency of the first clock signal; and operating a second portion of the third circuit according to the frequency of the second clock signal, wherein operating the plurality of second circuits is at least partially based on operating the first segment and the second segment.

[0091] Aspect 10: The method, apparatus, or non-transitory computer-readable medium according to any one of aspects 7 to 9, wherein the modified frequency of the first clock signal is less than the frequency of the second clock signal.

[0092] It should be noted that the methods described herein describe possible implementations, and the operations and steps may be rearranged or otherwise modified, and other implementations are possible. Furthermore, portions of two or more of the methods may be combined.

[0093] This describes a device. An overview of aspects of the device described herein is provided below:

[0094] Aspect 11: A system comprising: a substrate including: a first circuit configured to transmit signaling indicating a first command and first data according to a first protocol; a plurality of second circuits, each configured to couple to one or more memory devices and to transmit signaling indicating a second command and second data according to a second protocol, wherein each of a plurality of segments of the substrate includes at least one of the plurality of second circuits; a plurality of sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; a second circuit configured to generate a plurality of clock signals, each clock signal associated with a corresponding segment of the plurality of segments of the substrate; and logic configured to: determine, at least in part, whether the temperature of a first segment of the plurality of segments of the substrate exceeds a threshold based on the corresponding temperature sensed by the plurality of sensors; modify, at least in part, the frequency of the first clock signal associated with the first segment relative to the frequency of a second clock signal associated with a second segment among the plurality of clock signals, based at least in part on the temperature of the first segment exceeding the threshold; and operate the system at least in part based on the modified frequency of the first clock signal and the frequency of the second clock signal.

[0095] Aspect 12: The system according to aspect 11, wherein the substrate further comprises a plurality of caches, and wherein the logic is configured to: operate a first cache of the plurality of caches associated with the first segment according to the modified frequency of the first clock signal; and operate a second cache associated with the second segment according to the frequency of the second clock signal, wherein operating the system is at least partially based on operating the first cache and the second cache.

[0096] Aspect 13: The system according to aspect 12, wherein each of the plurality of segments comprises a corresponding subset of the plurality of caches or a corresponding subset of the plurality of second circuits or any combination thereof.

[0097] Aspect 14: The system according to any one of aspects 12 to 13, wherein the substrate further includes a third circuit, and wherein the logic is further configured to: operate a first portion of the third circuit according to the modified frequency of the first clock signal; and operate a second portion of the third circuit according to the frequency of the second clock signal.

[0098] Aspect 15: The system according to any one of aspects 11 to 14, wherein the modified frequency of the first clock signal is less than the frequency of the second clock signal.

[0099] Aspect 16: A system according to any one of aspects 11 to 15, wherein the logic is further configured to: modify a corresponding parameter among a plurality of parameters associated with an indication of writing to a first subset of one or more physical addresses of a cache in a plurality of caches to indicate the transfer of corresponding data associated with each physical address of the first subset; and transfer the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

[0100] Aspect 17: The system according to aspect 16, wherein the logic is further configured to: modify a second parameter associated with a second subset of the one or more physical addresses to indicate that data associated with the corresponding physical address of the second subset is written to the cache; and suppress the transfer of the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

[0101] Aspect 18: A system according to any one of aspects 16 to 17, wherein the logic is further configured to: modify a parameter associated with the indication of the physical address to indicate that data associated with the physical address is written to a memory device coupled to one of the plurality of second circuits, wherein access operations associated with the data bypass the cache.

[0102] Aspect 19: The system according to aspect 18, wherein the logic is further configured to: receive from the first circuit a signaling instruction indicating access to data associated with the physical address; retrieve the data directly from the second circuit coupled to the memory device, at least in part based on the parameters, wherein bypassing the cache includes retrieving the data; and transfer the data to the first circuit, at least in part based on retrieving the data from the second circuit.

[0103] Aspect 20: A system according to any one of aspects 16 to 19, wherein the logic is further configured to: transfer data representing a physical address from a first cache associated with the first segment to a second cache associated with the second segment of the plurality of segments, based at least in part on the temperature of the first segment and the temperature of the second segment.

[0104] This describes a device. An overview of aspects of the device described herein is provided below:

[0105] Aspect 21: A system comprising: a substrate including: a first circuit configured to transmit signaling indicating a first command and first data according to a first protocol; a plurality of second circuits, each configured to couple to one or more memory devices and to transmit signaling indicating a second command and second data according to a second protocol, wherein each of a plurality of segments of the substrate includes at least one of the plurality of second circuits; a plurality of caches; a first logic configured to access the plurality of caches; a plurality of sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; and a second logic configured to: determine, at least in part, based on the corresponding temperature sensed by the plurality of sensors, whether the temperature of a first segment of the plurality of segments of the substrate exceeds a threshold; and modify, at least in part, based on the temperature of the first segment exceeding the threshold, a corresponding parameter among a plurality of parameters associated with an indication to write to one or more physical addresses of the caches in the plurality of caches.

[0106] Aspect 22: The system according to aspect 21, wherein the second logic is further configured to: modify the corresponding parameters associated with a first subset of the one or more physical addresses to indicate the transfer of corresponding data associated with each physical address of the first subset; and transfer the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

[0107] Aspect 23: The system according to aspect 22, wherein the second logic is further configured to: modify a second parameter associated with a second subset of the one or more physical addresses to indicate that data associated with the physical addresses is written to the cache; and suppress the transfer of the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

[0108] Aspect 24: A system according to any one of aspects 21 to 23, wherein the second logic is further configured to: modify the parameter associated with the indication of the physical address to indicate that data associated with the physical address is written to a memory device coupled to a second circuit in one of the plurality of second circuits, wherein access operations associated with the data bypass the cache.

[0109] Aspect 25: The system according to aspect 24, wherein the second logic is further configured to: receive from the first circuit a signaling instruction indicating access to data associated with the physical address; retrieve the data directly from the second circuit coupled to the memory device, at least in part based on the parameters, wherein bypassing the cache includes retrieving the data; and transfer the data to the first circuit, at least in part based on retrieving the data from the second circuit.

[0110] Aspect 26: The system according to any one of aspects 21 to 25, wherein the second logic is further configured to: transfer data representing a physical address from a first cache of the first segment to a second cache associated with a second segment of the plurality of segments, based at least in part on the temperature of the first segment and the temperature of the second segment.

[0111] Aspect 27: In a system according to any one of aspects 21 to 26, the substrate further includes a third circuit configured to generate a plurality of clock signals, each of the plurality of clock signals being associated with a corresponding segment of the plurality of segments of the substrate, wherein the second logic is further configured to: modify the frequency of a first clock signal associated with the first segment relative to the frequency of a second clock signal associated with the second segment, at least in part based on determining that the temperature of the first segment exceeds the threshold; and operate the system at least in part based on the frequency of the first clock signal and the frequency of the second clock signal.

[0112] Aspect 28: The system according to aspect 27, wherein the second logic is further configured to: operate a first cache of the plurality of caches associated with the first segment according to the modified frequency of the first clock signal; and operate a second cache associated with the second segment according to the frequency of the second clock signal, wherein operating the system is at least partially based on operating the first cache and the second cache.

[0113] Aspect 29: The system according to any one of aspects 27 to 28, wherein the second logic is further configured to: operate a first portion of the third circuit according to the modified frequency of the first clock signal; and operate a second portion of the third circuit according to the frequency of the second clock signal.

[0114] Aspect 30: The system according to any one of aspects 27 to 29, wherein the modified frequency of the first clock signal is less than the frequency of the second clock signal.

[0115] Aspect 31: A system according to any one of aspects 27 to 30, wherein each of the plurality of segments comprises a corresponding subset of the plurality of caches or a corresponding subset of the plurality of second circuits or any combination thereof.

[0116] This describes a device. An overview of aspects of the device described herein is provided below:

[0117] Aspect 32: A system comprising: a substrate including: a first circuit configured to transmit signaling indicating a first command and first data according to a first protocol; a plurality of second circuits, each configured to be coupled to one or more memory devices and to transmit signaling indicating a second command and second data according to a second protocol, wherein each of a plurality of segments of the substrate includes at least one of the plurality of second circuits; a plurality of caches; a first logic configured to access the plurality of caches; a plurality of sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; and a second circuit configured to... The system is configured to generate multiple clock signals, each clock signal associated with a corresponding segment of the plurality of segments of the substrate; and a second logic configured to: determine whether the rate of temperature change of a first segment of the plurality of segments of the substrate exceeds a first threshold and whether the temperature of the first segment exceeds a second threshold; modify a parameter of a plurality of parameters associated with an indication of writing to one or more physical addresses of caches in the plurality of caches, based at least in part on the rate of temperature change of the first segment and the temperature of the first segment; and operate the system based at least in part on the modified parameters.

[0118] Aspect 33: The system according to aspect 32, wherein the second logic is further configured to: modify the frequency of a first clock signal associated with the first segment relative to the frequency of a second clock signal associated with the second segment, at least in part based on determining that the predicted temperature of the first segment exceeds a threshold, wherein the parameter includes the frequency of the first clock signal; and operate the system at least in part based on the frequency of the first clock signal and the frequency of the second clock signal.

[0119] Aspect 34: A system according to any one of aspects 32 to 33, wherein the second logic is further configured to: modify a corresponding parameter associated with a first subset of the one or more physical addresses to indicate the transfer of corresponding data associated with each physical address of the first subset; and transfer the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

[0120] Aspect 35: The system according to aspect 34, wherein the second logic is further configured to: modify a second parameter associated with a second subset of the one or more physical addresses to indicate that data associated with the physical addresses is written to the cache; and suppress the transfer of the data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

[0121] The information and signals described herein can be represented using any of a variety of different technologies and techniques. For example, data, instructions, commands, information, signals, bits, symbols, and chips that may be referenced throughout the foregoing description may be represented by voltage, current, electromagnetic waves, magnetic fields or magnetic particles, light fields or optical particles, or any combination thereof. Some diagrams may illustrate a signal as a single signal; however, a signal may represent a signal bus, where the bus may have various bit widths.

[0122] The terms "electronic communication," "conductive contact," "connection," and "coupling" can refer to a relationship between components that supports the flow of signals between them. Components are considered to be in electronic communication (e.g., conductive contact, connection, coupling) if there is any electrical path (e.g., conductive path) between them that allows the flow of signals (e.g., charge, current, voltage) between them at any given time. At any given time, the conductive path between components in electronic communication (e.g., conductive contact, connection, coupling) can be open or closed, depending on the operation of the device containing the connected components. The conductive path between connected components can be a direct conductive path between the components, or it can be an indirect conductive path that may include intermediate components (e.g., switches, transistors, or other components). In some instances, the signal flow between connected components can be interrupted for a period of time, for example, using one or more intermediate components (e.g., switches or transistors).

[0123] The term "isolation" refers to the relationship between components in which signals cannot currently flow between them. If there is an open circuit between components, then the components are isolated from each other. For example, when a switch positioned between two components is opened, the components separated by the switch are isolated from each other. When a controller isolates two components, the controller causes a change that prevents signals from flowing between the components using previously permitted conductive paths.

[0124] The devices discussed herein (including memory arrays) can be formed on semiconductor substrates such as silicon, germanium, silicon-germanium alloys, gallium arsenide, gallium nitride, etc. In some cases, the substrate is a semiconductor wafer. In other instances, the substrate can be a silicon-on-insulator (SOI) substrate (e.g., silicon-on-glass (SOG) or silicon-on-sapphire (SOP)) or an epitaxial layer of semiconductor material on another substrate. The conductivity of the substrate or subregions of the substrate can be controlled by doping with various chemical species, including (but not limited to) phosphorus, boron, or arsenic. Doping can be performed during the initial formation or growth of the substrate by ion implantation or by any other doping method.

[0125] The switching components (e.g., transistors) discussed herein may represent field-effect transistors (FETs) and may include three-terminal components comprising a source (e.g., a source terminal), a drain (e.g., a drain terminal), and a gate (e.g., a gate terminal). The terminals may be connected to other electronic components via a conductive material (e.g., a metal, an alloy). The source and drain may be conductive and may include doped (e.g., heavily doped, degenerate) semiconductor regions. The source and drain may be separated by doped (e.g., lightly doped) semiconductor regions or a channel. If the channel is n-type (e.g., the majority carriers are electrons), then the FET may be called an n-type FET. If the channel is p-type (e.g., the majority carriers are holes), then the FET may be called a p-type FET. The channel may be covered by an insulating gate oxide. Channel conductivity can be controlled by applying a voltage to the gate. For example, applying a positive or negative voltage to an n-type FET or a p-type FET, respectively, can cause the channel to become conductive. When a voltage greater than or equal to the transistor's threshold voltage is applied to the transistor's gate, the transistor may be "on" or "activated." When a voltage less than the transistor's threshold voltage is applied to the transistor's gate, the transistor can be "disconnected" or "deactivated".

[0126] The descriptions herein, presented in conjunction with the accompanying drawings, depict exemplary configurations and do not represent all implementable or within the scope of the claims. The term "exemplary" as used herein means "serving as an example, illustration, or description" rather than "preferred" or "superior to other examples." The detailed description includes specific details used to provide an understanding of the described techniques. However, these techniques may be practiced without these specific details. In some instances, well-known structures and devices are shown in block diagram form to avoid obscuring the concepts of the described examples.

[0127] In the accompanying drawings, similar components or features may have the same reference numerals. Furthermore, various components of the same type can be distinguished by a dash following the reference numeral and a second numeral to differentiate similar components. If only the first reference numeral is used in the specification, the description applies to any of the similar components having the same first reference numeral and is independent of the second reference numeral.

[0128] The functions described herein can be implemented in hardware, software executed by a processor, firmware, or any combination thereof. If implemented in software executed by a processor, the functions can be stored as one or more instructions (e.g., code) on or transmitted via a computer-readable medium. Other examples and embodiments are within the scope of this disclosure and the appended claims. For example, due to the nature of software, the functions described herein can be implemented using software executed by a processor, hardware, firmware, hardwired, or any combination thereof. Features implementing the functions can also be physically located at various locations, including distribution such that portions of the functions are implemented at different physical locations.

[0129] For example, the various specification boxes and modules described in connection with this disclosure may be implemented or performed by a processor (e.g., a DSP, ASIC, FPGA, discrete gate logic, discrete transistor logic, discrete hardware component, other programmable logic device, or any combination thereof) designed to perform the functions described herein. The processor may be a microprocessor, controller, microcontroller, state machine, or an instance of any type of processor. The processor may also be implemented as a combination of computing devices (e.g., a combination of a DSP and a microprocessor, multiple microprocessors, one or more microprocessors incorporating a DSP core, or any other such configuration).

[0130] As used herein (included in the claims), the word "or" in a list of items (e.g., a list of items beginning with a phrase such as "at least one of..." or "one or more of...") indicates an inclusive list, such that (e.g.) a list of at least one of A, B, or C means A or B or C or AB or AC or BC or ABC (i.e., A and B and C). Furthermore, as used herein, the phrase "based on" should not be construed as referring to a closed set of conditions. For example, without departing from the scope of this disclosure, an exemplary step described as "based on condition A" may be based on both condition A and condition B. In other words, as used herein, the phrase "based on" should be interpreted in the same manner as the phrase "at least partially based on".

[0131] Computer-readable media includes both non-transitory computer storage media and communication media, encompassing any media that facilitates the transfer of a computer program from one location to another. Non-transitory storage media can be any usable media accessible by a computer. For example, but not limited to, non-transitory computer-readable media may include RAM, ROM, electrically erasable programmable read-only memory (EEPROM), optical disc (CD) ROM or other optical disc storage devices, magnetic disk storage devices or other magnetic storage devices, or any other non-transitory media that can be used to carry or store desired program code elements in the form of instructions or data structures and is accessible by a computer or processor. Furthermore, any connection is appropriately referred to as computer-readable media. For example, if software is transmitted from a website, server, or other remote source using coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave), then coaxial cable, fiber optic cable, twisted pair, digital subscriber line (DSL), or wireless technology (such as infrared, radio, and microwave) is included in the definition of media. As used herein, disks and optical discs include CDs, laser discs, optical discs, digital multifunction optical discs (DVDs), floppy disks, and Blu-ray discs, wherein disks typically reproduce data magnetically, while optical discs reproduce data optically using lasers. Combinations of the above are also included within the scope of computer-readable media.

[0132] The description herein is provided to enable those skilled in the art to make or use this disclosure. Those skilled in the art will understand various modifications to this disclosure and that the general principles defined herein can be applied to other variations without departing from the scope of this disclosure. Therefore, this disclosure is not limited to the examples and designs described herein, but should be given the broadest scope consistent with the principles and novel features disclosed herein.

Claims

1. A system comprising: Substrate, comprising: A first circuit configured to transmit signaling indicating a first command and first data in accordance with a first protocol; A plurality of second circuits, each configured to be coupled to one or more memory devices and to transmit signaling instructing second commands and second data according to a second protocol, wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits; Multiple sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; A second circuit is configured to generate a plurality of clock signals, each clock signal being associated with a corresponding segment of the plurality of segments of the substrate; and A logic device configured to: Whether the temperature of a first segment of the plurality of segments of the substrate exceeds a threshold is determined at least in part based on the corresponding temperatures sensed by the plurality of sensors; At least in part based on the temperature of the first segment exceeding the threshold, the frequency of the first clock signal associated with the first segment among the plurality of clock signals is modified relative to the frequency of the second clock signal associated with the second segment among the plurality of clock signals; and The system operates at least in part based on the modified frequency of the first clock signal and the frequency of the second clock signal.

2. The system of claim 1, wherein the substrate further comprises a plurality of caches, and wherein the logic device is configured to: The first cache among the plurality of caches associated with the first segment according to the modified frequency operation of the first clock signal; and The second cache associated with the second segment is operated according to the frequency of the second clock signal, wherein the operation of the system is at least partially based on the operation of the first cache and the second cache.

3. The system of claim 2, wherein each of the plurality of segments comprises a corresponding subset of the plurality of caches or a corresponding subset of the plurality of second circuits or any combination thereof.

4. The system of claim 2, wherein the substrate further includes a third circuit, and wherein the logic device is further configured to: The first part of the third circuit operates at the modified frequency according to the first clock signal; and The second part of the third circuit operates according to the frequency of the second clock signal.

5. The system of claim 1, wherein the modified frequency of the first clock signal is less than the frequency of the second clock signal.

6. The system of claim 1, wherein the logic device is further configured to: Modify the corresponding parameter among a plurality of parameters associated with an indication to write to a first subset of one or more physical addresses in multiple caches to indicate the transfer of the corresponding data associated with each physical address of the first subset; and The data associated with each physical address of the first subset is transferred from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

7. The system of claim 6, wherein the logic device is further configured to: Modify a second parameter associated with a second subset of the one or more physical addresses to indicate that data associated with the corresponding physical addresses of the second subset is written to the cache; and Suppress the transfer of data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

8. The system of claim 6, wherein the logic device is further configured to: The parameters associated with the indication of the physical address are modified to indicate that the data associated with the physical address is written to a memory device coupled to one of the plurality of second circuits, wherein the access operation associated with the data bypasses the cache.

9. The system of claim 8, wherein the logic device is further configured to: Receive signaling from the first circuit indicating a command to access the data associated with the physical address; Retrieving the data directly from the second circuitry coupled to the memory device, at least in part based on the parameters, wherein bypassing the cache includes retrieving the data; and The data is transmitted to the first circuit based at least in part on data retrieved from the second circuit.

10. The system of claim 6, wherein the logic device is further configured to: Data representing physical addresses is transferred from a first cache associated with the first segment to a second cache associated with the second segment, based at least in part on the temperature of the first segment and the temperature of the second segment.

11. A system comprising: Substrate, comprising: A first circuit configured to transmit signaling indicating a first command and first data in accordance with a first protocol; A plurality of second circuits, each configured to be coupled to one or more memory devices and to transmit signaling instructing second commands and second data according to a second protocol, wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits; Multiple caches; A first logic device configured to access the plurality of caches; Multiple sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; and A second logic device, configured to: The temperature of a first segment of the plurality of segments of the substrate is determined, at least in part, based on the corresponding temperatures sensed by the plurality of sensors; and Based at least in part on the fact that the temperature of the first segment exceeds the threshold, the corresponding parameter in a plurality of parameters associated with an indication of writing to one or more physical addresses of the caches in the plurality of caches is modified.

12. The system of claim 11, wherein the second logic device is further configured to: Modify the corresponding parameters associated with a first subset of the one or more physical addresses to indicate the transmission of corresponding data associated with each physical address of the first subset; and The data associated with each physical address of the first subset is transferred from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

13. The system of claim 12, wherein the second logic device is further configured to: Modify the second parameter associated with the second subset of the one or more physical addresses to indicate that data associated with the physical addresses is written to the cache; and Suppress the transfer of data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

14. The system of claim 11, wherein the second logic device is further configured to: The parameter associated with the indication of the physical address is modified to indicate that data associated with the physical address is written to a memory device coupled to a second circuit in one of the plurality of second circuits, wherein access operations associated with the data bypass the cache.

15. The system of claim 14, wherein the second logic device is further configured to: Receive signaling from the first circuit indicating a command to access the data associated with the physical address; Retrieving the data directly from the second circuitry coupled to the memory device, at least in part based on the parameters, wherein bypassing the cache includes retrieving the data; and The data is transmitted to the first circuit based at least in part on data retrieved from the second circuit.

16. The system of claim 11, wherein the second logic device is further configured to: Data representing physical addresses is transferred from a first cache of the first segment to a second cache associated with the second segment of the plurality of segments, based at least in part on the temperature of the first segment and the temperature of the second segment.

17. The system of claim 11, wherein the substrate further includes a third circuit configured to generate a plurality of clock signals, each of the plurality of clock signals being associated with a corresponding segment of the plurality of segments of the substrate, wherein the second logic device is further configured to: Based at least in part on determining that the temperature of the first segment exceeds the threshold, the frequency of the first clock signal associated with the first segment is modified relative to the frequency of the second clock signal associated with the second segment; and The system operates at least in part based on the frequency of the first clock signal and the frequency of the second clock signal.

18. The system of claim 17, wherein the second logic device is further configured to: The first cache among the plurality of caches associated with the first segment according to the modified frequency operation of the first clock signal; and The second cache associated with the second segment is operated according to the frequency of the second clock signal, wherein the operation of the system is at least partially based on the operation of the first cache and the second cache.

19. The system of claim 17, wherein the second logic device is further configured to: The first part of the third circuit operates at the modified frequency according to the first clock signal; and The second part of the third circuit operates according to the frequency of the second clock signal.

20. The system of claim 17, wherein the modified frequency of the first clock signal is less than the frequency of the second clock signal.

21. The system of claim 17, wherein each of the plurality of segments comprises a corresponding subset of the plurality of caches or a corresponding subset of the plurality of second circuits or any combination thereof.

22. A system comprising: Substrate, comprising: A first circuit configured to transmit signaling indicating a first command and first data in accordance with a first protocol; A plurality of second circuits, each configured to be coupled to one or more memory devices and to transmit signaling instructing second commands and second data according to a second protocol, wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits; Multiple caches; A first logic device configured to access the plurality of caches; Multiple sensors, each configured to sense a corresponding temperature at a corresponding location on the substrate; A second circuit is configured to generate a plurality of clock signals, each clock signal being associated with a corresponding segment of the plurality of segments of the substrate; and A second logic device, configured to: Determine whether the rate of temperature change of a first segment among the plurality of segments of the substrate exceeds a first threshold and whether the temperature of the first segment exceeds a second threshold; Based at least in part on the rate of change of the temperature of the first segment and the temperature of the first segment, modify a parameter among a plurality of parameters associated with an indication to write to one or more physical addresses of the caches in the plurality of caches; and The system operates at least in part based on the modified parameters.

23. The system of claim 22, wherein the second logic device is further configured to: At least in part based on determining that the predicted temperature of the first segment exceeds a threshold, the frequency of the first clock signal associated with the first segment is modified relative to the frequency of the second clock signal associated with the second segment, wherein the parameter includes the frequency of the first clock signal; and The system operates at least in part based on the frequency of the first clock signal and the frequency of the second clock signal.

24. The system of claim 22, wherein the second logic device is further configured to: Modify the corresponding parameters associated with a first subset of the one or more physical addresses to indicate the transmission of corresponding data associated with each physical address of the first subset; and The data associated with each physical address of the first subset is transferred from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

25. The system of claim 24, wherein the second logic device is further configured to: Modify the second parameter associated with the second subset of the one or more physical addresses to indicate that data associated with the physical addresses is written to the cache; and Suppress the transfer of data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the one or more memory devices.

26. A method comprising: According to the first protocol, a first circuit on the substrate is used to transmit a first signaling instruction indicating a first command and first data; At least a subset of the first data is written using multiple caches based on the physical address associated with the corresponding command in the first command; According to the second protocol, a plurality of second circuits on the substrate are used together with a plurality of memory devices to convey a second signaling indicating a second command and second data, wherein conveying the second signaling includes reading at least a subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits. The temperature at the corresponding location on the substrate is sensed using multiple sensors positioned at corresponding locations on the substrate. At the logic device on the substrate, it is determined, at least in part, based on the corresponding temperature sensed at the corresponding location, whether the temperature of a first segment of the plurality of segments of the substrate meets a threshold. and Based at least in part on determining that the temperature of the first segment meets the threshold, the corresponding parameter among a plurality of parameters associated with an indication of one or more of the physical addresses of the caches written into the plurality of caches is modified.

27. The method of claim 26, further comprising: Modify the corresponding parameters associated with a first subset of the one or more physical addresses to indicate the transmission of corresponding data associated with each physical address of the first subset; and The data associated with each physical address of the first subset is transferred from the cache of the first segment to the corresponding physical address of the corresponding memory device in the plurality of memory devices.

28. The method of claim 27, further comprising: Modify a second parameter associated with a second subset of the one or more physical addresses to indicate that data associated with the physical addresses is written to the cache; and Suppress the transfer of data associated with each physical address of the first subset from the cache of the first segment to the corresponding physical address of the corresponding memory device in the plurality of memory devices.

29. The method of claim 26, further comprising: The parameter associated with the indication of the physical address is modified to indicate that data associated with the physical address is written to a memory device coupled to a second circuit, wherein access operations associated with the data bypass the cache.

30. The method of claim 29, further comprising: Receive signaling from the first circuit indicating a command to access the data associated with the physical address; The data is retrieved directly from the second circuit coupled to the memory device according to the second protocol, at least in part based on the parameters, wherein bypassing the cache includes retrieving the data; and The data is transmitted to the first circuit based at least in part on data retrieved from the second circuit.

31. The method of claim 26, further comprising: Data representing physical addresses is transferred from a first cache of the first segment to a second cache associated with the second segment of the plurality of segments, based at least in part on the temperature of the first segment and the temperature of the second segment.

32. A method comprising: According to the first protocol, a first circuit on the substrate is used to transmit a first signaling instruction indicating a first command and first data; At least a subset of the first data is written using multiple caches based on the physical address associated with the corresponding command in the first command; According to the second protocol, a plurality of second circuits on the substrate are used together with a plurality of memory devices to convey a second signaling indicating a second command and second data, wherein conveying the second signaling includes reading at least a subset of the first data to obtain the second data and writing the second data to one or more of the plurality of memory devices, and wherein each of the plurality of segments of the substrate includes at least one of the plurality of second circuits. The temperature at the corresponding location on the substrate is sensed using multiple sensors positioned at corresponding locations on the substrate. At the logic device on the substrate, it is determined, at least in part, based on the corresponding temperature sensed at the corresponding location, whether the temperature of a first segment of the plurality of segments of the substrate meets a threshold. At a second circuit configured to generate a plurality of clock signals, each of the plurality of clock signals is associated with a segment of the plurality of segments of the substrate, and the frequency of a first clock signal associated with the first segment is modified relative to the frequency of a second clock signal associated with the second segment, based at least in part on determining that the temperature of the first segment meets the threshold. and The plurality of second circuits are operated at least in part based on the frequency of the first clock signal and the frequency of the second clock signal.

33. The method of claim 32, further comprising: The first cache of the plurality of caches associated with the first segment is operated according to the frequency of the first clock signal; and Operate the second cache of the plurality of caches associated with the second segment according to the frequency of the second clock signal, wherein the operation of the plurality of second circuits is at least partially based on the operation of the first cache and the second cache.

34. The method of claim 32, further comprising: The first part of the third circuit operates according to the modified frequency of the first clock signal; and The second portion of the third circuit is operated according to the frequency of the second clock signal, wherein the operation of the plurality of second circuits is at least partially based on the operation of the first segment and the second segment.

35. The method of claim 32, wherein the modified frequency of the first clock signal is less than the frequency of the second clock signal.

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