Power converter with multi-slope compensation mechanism

Abstract

This invention discloses a power converter with a multi-slope compensation mechanism. The multi-slope compensation circuit of the power converter includes multiple first capacitors, a comparator, and multiple first resistors. An inductor is connected to the node between the first terminals of the multiple first capacitors and the second terminal of the upper bridge switch and the first terminal of the lower bridge switch. Multiple first input terminals of the comparator are respectively connected to the second terminals of the multiple first capacitors and to the first terminals of the multiple first resistors. The second terminals of the multiple first resistors are coupled to a second reference voltage. The second input terminal of the comparator is coupled to a first reference voltage. The output terminal of the comparator is connected to the input terminal of a drive circuit.

Description

Technical Field

[0001] This invention relates to power converters, and more specifically to a power converter with a multi-slope compensation mechanism. Background Technology

[0002] A power converter is used to transform input voltage to provide an output voltage to the load connected to the power converter as the power required for the load to operate. However, when the load suddenly changes from a light load to a heavy load, the current drawn by the load from the power converter increases instantaneously, causing the output voltage of the power converter to undershoot to an excessively low value. This can damage the circuit components of the power converter and prevent it from providing sufficient current to the load. Summary of the Invention

[0003] The technical problem to be solved by this invention is to provide a power converter with a multi-slope compensation mechanism, addressing the shortcomings of existing technologies. The power converter includes an upper bridge switch, a lower bridge switch, a multi-slope compensation circuit, and a drive circuit. A first terminal of the upper bridge switch is coupled to an input voltage. A first terminal of the lower bridge switch is connected to a second terminal of the upper bridge switch. The second terminal of the lower bridge switch is grounded. A node between the first terminal of the lower bridge switch and the second terminal of the upper bridge switch is connected to a first terminal of an inductor. The second terminal of the inductor is connected to a first terminal of an output capacitor. The second terminal of the output capacitor is grounded. The multi-slope compensation circuit includes multiple first capacitors, a comparator, multiple first resistors, and a second resistor. Each first capacitor has a first terminal and a second terminal. Multiple first input terminals of the comparator are respectively connected to the second terminals of the multiple first capacitors. The second input terminal of the comparator is coupled to a first reference voltage. The first terminals of the multiple first resistors are respectively connected to the multiple first input terminals of the comparator and to the second terminals of the multiple first capacitors. The second terminals of the multiple first resistors are coupled to a second reference voltage. The first terminal of the second resistor is connected to the first terminal of the inductor. The second terminal of the second resistor is connected to the first terminal of each first capacitor. The input terminal of the drive circuit is connected to the output terminal of the comparator. The output of the drive circuit is connected to the control terminals of the upper bridge switch and the lower bridge switch.

[0004] In one embodiment, the multi-slope compensation circuit further includes a second capacitor. A first terminal of the second capacitor is connected to a second terminal of an inductor. A second terminal of the second capacitor is connected to a first terminal of each of the first capacitors.

[0005] In this embodiment, the multi-slope compensation circuit further includes an error amplifier. The first input terminal of the error amplifier is connected to the second terminal of an inductor. The second input terminal of the error amplifier is coupled to a third reference voltage. The output terminal of the error amplifier is connected to the second input terminal of a comparator. The voltage at the output terminal of the error amplifier is the first reference voltage.

[0006] In one embodiment, the power converter with a multi-slope compensation mechanism further includes a voltage divider circuit. The input of the voltage divider circuit is connected to the second terminal of an inductor. The output of the voltage divider circuit is connected to the first input of an error amplifier.

[0007] In this embodiment, the voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. A first terminal of the first voltage divider resistor is connected to a second terminal of an inductor. A second terminal of the first voltage divider resistor is connected to a first terminal of the second voltage divider resistor. The node between the second terminal of the first voltage divider resistor and the first terminal of the second voltage divider resistor is connected to a first input terminal of an error amplifier. The second terminal of the second voltage divider resistor is grounded.

[0008] In this embodiment, the second terminal of each first resistor is connected to the second terminal of an inductor. The voltage at the second terminal of the inductor is a second reference voltage.

[0009] In one embodiment, the power converter with a multi-slope compensation mechanism further includes a voltage divider circuit. The input terminal of the voltage divider circuit is connected to the second terminal of an inductor. The output terminal of the voltage divider circuit is connected to the second terminal of each of the first resistors.

[0010] In this embodiment, the voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. A first terminal of the first voltage divider resistor is connected to a second terminal of an inductor. A second terminal of the first voltage divider resistor is connected to a first terminal of the second voltage divider resistor. A node between the second terminals of the first and second voltage divider resistors is connected to the second terminals of each of the first resistors. The second terminal of the second voltage divider resistor is grounded. The voltage at the first terminal of the second voltage divider resistor is a second reference voltage.

[0011] In this embodiment, the second input terminal of the comparator is connected to the second terminal of the inductor. The voltage at the second terminal of the inductor is a first reference voltage.

[0012] In one embodiment, the power converter with a multi-slope compensation mechanism further includes a voltage divider circuit. The input terminal of the voltage divider circuit is connected to the second terminal of an inductor. The output terminal of the voltage divider circuit is connected to the second input terminal of a comparator.

[0013] In this embodiment, the voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. A first terminal of the first voltage divider resistor is connected to a second terminal of an inductor. A second terminal of the first voltage divider resistor is connected to a first terminal of the second voltage divider resistor. The node between the second terminal of the first voltage divider resistor and the first terminal of the second voltage divider resistor is connected to a second input terminal of a comparator. The second terminal of the second voltage divider resistor is grounded. The voltage at the first terminal of the second voltage divider resistor is a first reference voltage.

[0014] In this embodiment, the driving circuit includes a turn-on signal generator. The turn-on signal generator is connected to the output of the comparator, the control terminal of the upper bridge switch, and the control terminal of the lower bridge switch. The turn-on signal generator is configured to output an upper bridge turn-on signal to the control terminal of the upper bridge switch and an lower bridge turn-on signal to the control terminal of the lower bridge switch based on the comparison signal output by the comparator.

[0015] In this embodiment, the driving circuit further includes logic circuitry. The logic circuitry is connected to the conduction signal generator, the control terminal of the upper bridge switch, and the control terminal of the lower bridge switch. The logic circuitry is configured to output a first logic signal to the control terminal of the upper bridge switch based on the upper bridge conduction signal, and to output a second logic signal to the control terminal of the lower bridge switch based on the lower bridge conduction signal.

[0016] In this embodiment, the driving circuit further includes a first buffer circuit. The input of the first buffer circuit is connected to the output of the logic circuit. The output of the first buffer circuit is connected to the control terminal of the upper bridge switch.

[0017] In this embodiment, the driving circuit further includes a second buffer circuit. The input of the second buffer circuit is connected to the output of the logic circuit. The output of the second buffer circuit is connected to the control terminal of the lower bridge switch.

[0018] Furthermore, this invention provides a power converter with a multi-slope compensation mechanism, comprising an upper bridge switch, a lower bridge switch, a multi-slope compensation circuit, and a drive circuit. The first terminal of the upper bridge switch is coupled to an input voltage. The first terminal of the lower bridge switch is connected to the second terminal of the upper bridge switch. The second terminal of the lower bridge switch is grounded. The node between the first terminal of the lower bridge switch and the second terminal of the upper bridge switch is connected to the first terminal of an inductor. The second terminal of the inductor is connected to the first terminal of an output capacitor. The second terminal of the output capacitor is grounded. The multi-slope compensation circuit includes a first capacitor, a comparator, multiple first resistors, and a second resistor. The first capacitor has a first terminal and a second terminal. The comparator has multiple first input terminals and a second input terminal. The second input terminal of the comparator is coupled to a first reference voltage. The multiple first resistors are connected in series. The first terminal of one of the first resistors is further connected to the second terminal of the first capacitor. The second terminal of another first resistor is coupled to a second reference voltage. The second terminals of each of the other first resistors (excluding the other first resistor) are connected to the first terminals of adjacent first resistors. The first terminal of the second resistor is connected to the first terminal of the inductor, and the second terminal of the second resistor is connected to the first terminal of the first capacitor. The input terminal of the drive circuit is connected to the output terminal of the comparator. The output of the drive circuit is connected to the control terminals of the upper bridge switch and the lower bridge switch.

[0019] In one embodiment, the multi-slope compensation circuit further includes a second capacitor. A first terminal of the second capacitor is connected to a second terminal of the inductor. A second terminal of the second capacitor is connected to a first terminal of the first capacitor.

[0020] In this embodiment, the multi-slope compensation circuit further includes an error amplifier. The first input terminal of the error amplifier is connected to the second terminal of an inductor. The second input terminal of the error amplifier is coupled to a third reference voltage. The output terminal of the error amplifier is connected to the second input terminal of a comparator. The voltage at the output terminal of the error amplifier is the first reference voltage.

[0021] In one embodiment, the power converter with a multi-slope compensation mechanism further includes a voltage divider circuit. The input of the voltage divider circuit is connected to the second terminal of an inductor. The output of the voltage divider circuit is connected to the first input of an error amplifier.

[0022] In this embodiment, the voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. A first terminal of the first voltage divider resistor is connected to a second terminal of an inductor. A second terminal of the first voltage divider resistor is connected to a first terminal of the second voltage divider resistor. The node between the second terminal of the first voltage divider resistor and the first terminal of the second voltage divider resistor is connected to a first input terminal of an error amplifier. The second terminal of the second voltage divider resistor is grounded.

[0023] As described above, this invention provides a power converter with a multi-slope compensation mechanism. It provides multiple slope voltages and, under different instantaneous load changes, selects a suitable slope voltage and compares it with the sensed voltage of the power converter to enable the power converter to provide an optimal instantaneous load response. Specifically, when the instantaneous load change is large and the instantaneous power requirement is high, a slope voltage with a smaller amplitude is selected and compared with the sensed voltage of the power converter to quickly activate the upper bridge switch. In this way, the power converter can provide sufficient power to the load while preventing the output voltage of the power converter from momentarily dropping to an excessively low value, which could damage the circuit components of the power converter.

[0024] To further understand the features and technical content of the present invention, please refer to the following detailed description and drawings of the present invention. However, the drawings provided are for reference and illustration only and are not intended to limit the present invention. Attached Figure Description

[0025] Figure 1 This is a circuit diagram of a power converter with a multi-slope compensation mechanism according to the first embodiment of the present invention.

[0026] Figure 2 This is a circuit diagram of a multi-slope compensation circuit for a power converter with a multi-slope compensation mechanism according to a second embodiment of the present invention.

[0027] Figure 3 This is a circuit diagram of a multi-slope compensation circuit for a power converter with a multi-slope compensation mechanism according to a third embodiment of the present invention.

[0028] Figure 4The waveform diagram is shown for the power converter with a multi-slope compensation mechanism according to the first embodiment of the present invention.

[0029] Figure 5 The waveform diagram is shown for the power converter with a multi-slope compensation mechanism according to the first embodiment of the present invention.

[0030] Figure 6 This is a circuit diagram of a multi-slope compensation circuit for a power converter with a multi-slope compensation mechanism according to the fourth embodiment of the present invention. Detailed Implementation

[0031] The following specific embodiments illustrate the implementation of the present invention. Those skilled in the art can understand the advantages and effects of the present invention from the content disclosed in this specification. The present invention can be implemented or applied through other different specific embodiments, and various details in this specification can also be modified and changed based on different viewpoints and applications without departing from the concept of the present invention. Furthermore, the accompanying drawings of the present invention are for simple illustrative purposes only and are not depictions of actual dimensions, as stated in advance. The following embodiments will further describe the relevant technical content of the present invention in detail, but the disclosed content is not intended to limit the scope of protection of the present invention. In addition, the term "or" as used herein may, depending on the actual situation, include any combination of any one or more of the associated listed items.

[0032] Please see Figure 1 and Figure 4 ,in Figure 1 This is a block diagram of a power converter with a multi-slope compensation mechanism according to a first embodiment of the present invention. Figure 4 This is a waveform diagram of the power converter with a multi-slope compensation mechanism according to the first embodiment of the present invention. Figure 5 The waveform diagram is shown for the power converter with a multi-slope compensation mechanism according to the first embodiment of the present invention.

[0033] The power converter in this embodiment of the invention may include an upper bridge switch HS, a lower bridge switch LS, a drive circuit DRV, an inductor L1, and an output capacitor Cout. In particular, the power converter in this embodiment of the invention also includes a multi-slope compensation circuit CPN1. If necessary, the power converter in this embodiment may further include a voltage divider circuit RDV.

[0034] The first terminal of the upper bridge switch HS is coupled to the input voltage VIN. The second terminal of the upper bridge switch HS is connected to the first terminal of the lower bridge switch LS. The second terminal of the lower bridge switch LS is grounded. The node between the first terminal of the lower bridge switch LS and the second terminal of the upper bridge switch HS is connected to the first terminal of the inductor L1. The second terminal of the inductor L1 is connected to the first terminal of the output capacitor Cout (equivalent series resistance ESR).

[0035] The second terminal of the output capacitor Cout is grounded. The node between the second terminal of inductor L1 (and the equivalent series resistance ESR of the output capacitor Cout) is the output terminal of the power converter. The voltage at the output terminal of the power converter is the output voltage VOUT.

[0036] The input terminal of the multi-slope compensation circuit CPN1 can be directly connected or as follows: Figure 1 The voltage divider circuit RDV is connected to the second terminal of inductor L1. The output of the multi-slope compensation circuit CPN1 can be connected to the input of the drive circuit DRV. The output of the drive circuit DRV is connected to the control terminals of the upper bridge switch HS and the lower bridge switch LS.

[0037] The multi-slope compensation circuit CPN1 can output a compensation signal to the drive circuit DRV based on the received output voltage VOUT or the voltage divider voltage generated by the voltage divider circuit RDV after dividing the output voltage VOUT. The drive circuit DRV can drive the upper bridge switch HS and the lower bridge switch LS based on the compensation signal received from the multi-slope compensation circuit CPN1.

[0038] It is worth noting that the multi-slope compensation circuit of the power converter of the present invention, for example... Figure 1 The multi-slope compensation circuit CPN1 shown may include multiple first capacitors C11 to C1n, a comparator CMP, multiple first resistors R11 to R1n, a second resistor R2, and a second capacitor C2, but the present invention is not limited thereto.

[0039] The first terminals of each of the first capacitors C11 to C1n are connected to the second terminals of the second resistor R2 and the second capacitor C2. The first terminal of the second resistor R2 is connected to the first terminal of the inductor L1, and can be connected to the node SW between the second terminal of the upper bridge switch HS and the lower bridge switch LS. The first terminal of the second capacitor C2 is connected to the second terminal of the inductor L1.

[0040] The comparator CMP has multiple first input terminals, such as the inverting input terminal, connected to the second terminals of multiple first capacitors C11 to C1n and the first terminals of multiple first resistors R11 to R1n, respectively. The second terminals of the multiple first resistors R11 to R1n are coupled to a second reference voltage VREF2.

[0041] The second input of the comparator CMP, such as the non-inverting input, can be coupled to a first reference voltage. If necessary, such as... Figure 1 As shown, the multi-slope compensation circuit CPN1 may further include an error amplifier GMA. The second input terminal of the comparator CMP, for example, the non-inverting input terminal, is connected to the output terminal of the error amplifier GMA. The voltage at the output terminal of the error amplifier GMA is the aforementioned first reference voltage.

[0042] The first input terminal of the error amplifier GMA, such as the inverting input terminal, can be directly connected or, as... Figure 1 As shown, the voltage divider circuit RDV is connected to the second terminal of inductor L1. That is, the input terminal of the voltage divider circuit RDV is connected to the second terminal of inductor L1, and the output terminal of the voltage divider circuit RDV is connected to the first input terminal of error amplifier GMA.

[0043] For example, such as Figure 1 As shown, the voltage divider circuit RDV may include a first voltage divider resistor RFB1 and a second voltage divider resistor RFB2. The first terminal of the first voltage divider resistor RFB1 is connected to the second terminal of the inductor L1. The second terminal of the first voltage divider resistor RFB1 is connected to the first terminal of the second voltage divider resistor RFB2. The second terminal of the second voltage divider resistor RFB2 is grounded. The node FB between the second terminal of the first voltage divider resistor RFB1 and the first terminal of the second voltage divider resistor RFB2 is connected to the first input terminal of the error amplifier GMA, for example, the inverting input terminal.

[0044] The second input terminal of the error amplifier GMA, for example, the non-inverting input terminal, is coupled to the third reference voltage VREF3. The output terminal of the error amplifier GMA is connected to the second input terminal of the comparator CMP, for example, the non-inverting input terminal. The output terminal of the comparator CMP is connected to the input terminal of the driver circuit DRV.

[0045] For example, such as Figure 1 As shown, the driving circuit DRV may include one or more of the following: a turn-on signal generator TNG, a logic circuit LGC, a first buffer circuit (which may include a first buffer BU1 and a second buffer BU2) and a second buffer circuit (which may include a third buffer BU3 and a fourth buffer BU4). These are merely examples and are not intended to limit the invention.

[0046] The input of the turn-on signal generator TNG in the driver circuit DRV is connected to the output of the comparator CMP in the multi-slope compensation circuit CPN1. The output of the turn-on signal generator TNG can be connected to the input of the logic circuit LGC.

[0047] The output of the logic circuit LGC can be connected to the input of the first buffer circuit (first buffer BU1). The output of the first buffer BU1 can be connected to the input of the second buffer BU2. The output of the first buffer circuit (second buffer BU2) can be connected to the control terminal of the upper bridge switch HS.

[0048] The output of the logic circuit LGC can also be connected to the input of the second buffer circuit (the third buffer BU3). The output of the third buffer BU3 can be connected to the input of the fourth buffer BU4. The output of the second buffer circuit (the fourth buffer BU4) can be connected to the control terminal of the lower bridge switch LS.

[0049] The first input terminal of the error amplifier GMA of the multi-slope compensation circuit CPN1, for example, the inverting input terminal, receives the output voltage VOUT from the second terminal of the inductor L1. Alternatively, the first input terminal of the error amplifier GMA, for example, the inverting input terminal, receives the divided voltage output by the voltage divider circuit RDV after dividing the output voltage VOUT, that is, the voltage at node FB between the second terminal of the first voltage divider resistor RFB1 and the first terminal of the second voltage divider resistor RFB2.

[0050] The second input of the error amplifier GMA can receive a third reference voltage VREF3.

[0051] The error amplifier GMA multiplies the difference between the output voltage VOUT or its divided voltage (the voltage of node FB) and the third reference voltage VREF3 by a gain to output an error amplification signal.

[0052] The comparator CMP of the multi-slope compensation circuit CPN1 has multiple first inputs, such as the inverting input, that can receive multiple slope voltages Vramp1 to Vrampn (i.e., the voltages at the first terminals of multiple first resistors R11 to R1n). The second input of the comparator CMP, such as the non-inverting input, receives the error amplification signal from the error amplifier GMA.

[0053] The comparator CMP selects one of multiple slope voltages Vramp1 to Vrampn and compares it with the error amplification signal to output a comparison signal. For example, as Figure 4 As shown, the comparator CMP selects one of the slope voltages Vramp1 and Vramp2 and compares it with the error amplification signal EAO to output the comparison signal CPOUT.

[0054] It is worth noting that the resistance values ​​of the multiple first resistors R11 to R1n in the multi-slope compensation circuit CPN1 can be different from each other, and the capacitance values ​​of the multiple first capacitors C11 to C1n can also be different from each other, so as to generate multiple slope voltages Vramp1 to Vrampn with different voltage values. For example... Figure 4 As shown, the voltage value of slope voltage Vramp2 is lower than the voltage value of slope voltage Vramp1, and the amplitude of the slope voltage Vramp2 signal is lower than the amplitude of the slope voltage Vramp1 signal.

[0055] It should be understood that the comparator CMP selects the voltage with the smallest amplitude from multiple slope voltages Vramp1 to Vrampn and compares it with the voltage of the error amplification signal. The comparison signal is, for example... Figure 4 The faster the multiple pulses of the comparison signal CPOUT are generated, the better.

[0056] Therefore, when the instantaneous changes in the load connected to the power converter's output are faster and the load requires more power (e.g., a heavy load), the comparator CMP compares the voltage of the error amplification signal with the voltage of the multiple slope voltages Vramp1 to Vrampn with the smallest amplitude to accelerate the output pulse speed of the comparator CMP. Thus, the drive circuit DRV, based on the pulse of the comparison signal CMP (i.e., a high level), quickly drives the upper bridge switch HS to turn on, allowing the input voltage VIN to sequentially provide power to the power converter's output through the conducting upper bridge switch HS and inductor L1. This rapidly increases the output voltage VOUT of the power converter, providing the power required by the load, while effectively preventing the output voltage VOUT of the power converter from undershooting to an excessively low value.

[0057] like Figure 4 As shown, starting from time t1, when the load current ILOAD drawn from the output of the power converter increases, the output voltage VOUT of the power converter will decrease. At this time, the comparator CMP compares the voltage of the error amplification signal with the slope voltage Vramp2 with a smaller amplitude, thereby increasing the frequency of the pulse of the comparison signal CPOUT generated by the comparator CMP. Thus, the drive circuit DRV increases the frequency at which it turns on the upper bridge switch HG according to the level of the comparison signal CPOUT, for example, a high level, causing the output voltage VOUT of the power converter to rise rapidly, while simultaneously providing the load current ILOAD required by the load.

[0058] like Figure 5 As shown, the comparator CMP compares the error amplification signal EAO1 with a slope voltage Vramp1 with a large amplitude. The result is that the power converter outputs an output voltage VOUT1. At this time, the current in inductor L1 is the inductor current IL1.

[0059] Conversely, the comparator CMP compares the error amplification signal EAO2 with a small-amplitude slope voltage Vramp2. The result is that the power converter outputs an output voltage VOUT2. At this time, the current in inductor L1 is the inductor current IL2.

[0060] Compared to the output voltage VOUT1, the undershoot of the output voltage VOUT2 is improved by 29%. Obviously, comparing the error amplification signal EAO2 with the slope voltage Vramp2 with a smaller amplitude can effectively improve the undershoot of the output voltage VOUT2.

[0061] In other words, the comparator CMP can select one of multiple slope voltages Vramp1 to Vrampn based on the instantaneous changes in the load and the power required by the load, compare it with the voltage of the error amplification signal, and output the pulse of the comparison signal.

[0062] When the instantaneous change in load is greater and the current required for a heavy load is greater, the comparator CMP selects the voltage with the smaller amplitude (e.g., slope voltage Vramp2) from multiple slope voltages Vramp1 to Vrampn and compares it with the voltage of the error amplification signal to output the pulse of the comparison signal more quickly.

[0063] When the load is in a steady state, under light load, or when the current required by the load decreases, the larger amplitude (e.g., slope voltage Vramp1) can be selected from multiple slope voltages Vramp1 to Vrampn and compared with the voltage of the error amplification signal to stably output the pulse of the comparison signal.

[0064] After the comparator CMP outputs the comparison signal CPOUT, the turn-on signal generator TNG of the driver circuit DRV determines the levels of an upper bridge turn-on signal and a lower bridge turn-on signal based on the level of the comparison signal received from the comparator CMP, and outputs the upper bridge turn-on signal and the lower bridge turn-on signal.

[0065] The logic circuit LGC outputs a first logic signal based on the upper bridge conduction signal, which passes through the first buffer BU1 and the second buffer BU2 of the first buffer circuit to the control terminal of the upper bridge switch HS. The logic circuit LGC outputs a second logic signal based on the lower bridge conduction signal, which passes through the third buffer BU3 and the fourth buffer BU4 of the second buffer circuit to the control terminal of the lower bridge switch LS.

[0066] For example, in the bridge conduction signal, for example Figure 4 When the upper bridge on signal TON is high (i.e., when the lower bridge on signal is low), the upper bridge switch HS is on and the lower bridge switch LS is off. When the lower bridge on signal is high (i.e., when the upper bridge on signal is low), the lower bridge switch LS is on and the upper bridge switch HS is off.

[0067] Please see Figure 2 This is a circuit diagram of a multi-slope compensation circuit for a power converter with a multi-slope compensation mechanism according to the second embodiment of the present invention.

[0068] The power converter of this invention may include, as in the following embodiments: Figure 2 The multi-slope compensation circuit CPN2 shown can replace, for example, Figure 1 The multi-slope compensation circuit CPN1 is shown.

[0069] like Figure 2 As shown, the multi-slope compensation circuit CPN2 of the power converter in this embodiment may include multiple first capacitors C11 to C1n, a comparator CMP, multiple first resistors R11 to R1n, and a second resistor R2.

[0070] The first terminals of each of the first capacitors C11 to C1n are connected to the second terminal of the second resistor R2. The first terminal of the second resistor R2 is connected to the first terminal of the inductor L1, and the first terminal of the second resistor R2 can be connected to, for example... Figure 1 The node SW between the second terminal of the upper bridge switch HS and the lower bridge switch LS is shown.

[0071] The multiple first input terminals of the comparator CMP, such as the inverting input terminal, are respectively connected to the second terminals of multiple first capacitors C11 to C1n and the first terminals of multiple first resistors R11 to R1n. The second terminals of the multiple first resistors R11 to R1n can be connected (through the voltage divider circuit RDV) to the second terminal of the inductor L1, which is the output terminal of the power converter.

[0072] For example, such as Figure 2 As shown, the voltage divider circuit RDV may include a first voltage divider resistor RFB1 and a second voltage divider resistor RFB2. The first terminal of the first voltage divider resistor RFB1 is connected to the second terminal of the inductor L1. The second terminal of the first voltage divider resistor RFB1 is connected to the first terminal of the second voltage divider resistor RFB2. The second terminal of the second voltage divider resistor RFB2 is grounded. The node FB between the second terminal of the first voltage divider resistor RFB1 and the first terminal of the second voltage divider resistor RFB2 is connected to the second terminals of each of the first resistors R11 to R1n.

[0073] The second input terminal of the comparator CMP, such as the non-inverting input terminal, can be coupled to the first reference voltage VREF1. The output terminal of the comparator CMP can be connected to, for example,... Figure 1 The input terminal of the drive circuit DRV (with turn-on signal generator TNG) shown.

[0074] The comparator CMP selects one of multiple slope voltages Vramp1 to Vrampn and compares it with a first reference voltage VREF1 to output a comparison signal. The driver circuit DRV can drive the upper bridge switch HS (on) and the lower bridge switch LS (off) according to the (high) level of the comparison signal.

[0075] When the instantaneous load change is significant, or when the load is heavy and requires a large current, the comparator CMP selects the voltage with the smallest amplitude from multiple slope voltages Vramp1 to Vrampn and compares it with the first reference voltage VREF1 to quickly output a pulsed comparison signal. This rapidly increases the output voltage VOUT of the power converter, providing the power required by the load, while effectively preventing the output voltage VOUT from undershooting to an excessively low value.

[0076] Please see Figure 3 This is a circuit diagram of a multi-slope compensation circuit for a power converter with a multi-slope compensation mechanism according to an embodiment of the present invention.

[0077] The power converter of this invention may include, as in the following embodiments: Figure 3 The multi-slope compensation circuit CPN3 shown can replace, for example, Figure 1 The multi-slope compensation circuit CPN1 is shown.

[0078] The first terminals of each of the first capacitors C11 to C1n are connected to the second terminal of the second resistor R2. The first terminal of the second resistor R2 is connected to the first terminal of the inductor L1, and the first terminal of the second resistor R2 can be connected to, for example... Figure 1 The node SW between the second terminal of the upper bridge switch HS and the lower bridge switch LS is shown.

[0079] The comparator CMP has multiple first input terminals, such as non-inverting input terminals, connected to the second terminals of multiple first capacitors C11 to C1n and the first terminals of multiple first resistors R11 to R1n, respectively. The second terminals of the multiple first resistors R11 to R1n are coupled to a second reference voltage VREF2.

[0080] The second input terminal of the comparator CMP, such as the non-inverting input terminal, can be connected (through the voltage divider circuit RDV) to the second terminal of the inductor L1, which is the output terminal of the power converter.

[0081] For example, such as Figure 3 As shown, the voltage divider circuit RDV may include a first voltage divider resistor RFB1 and a second voltage divider resistor RFB2. The first terminal of the first voltage divider resistor RFB1 is connected to the second terminal of the inductor L1. The second terminal of the first voltage divider resistor RFB1 is connected to the first terminal of the second voltage divider resistor RFB2. The second terminal of the second voltage divider resistor RFB2 is grounded. The node FB between the second terminal of the first voltage divider resistor RFB1 and the first terminal of the second voltage divider resistor RFB2 may be connected to the second input terminal of the comparator CMP, such as the inverting input terminal.

[0082] The output of comparator CMP is connected as follows: Figure 1 The input terminal of the drive circuit DRV (with turn-on signal generator TNG) shown.

[0083] The comparator CMP selects one of multiple slope voltages Vramp1 to Vrampn and compares it with the voltage at the second terminal of inductor L1 (i.e., the output voltage VOUT of the power converter) or its divided voltage (i.e., the voltage at node FB between the second terminal of the first voltage divider resistor RFB1 and the first terminal of the second voltage divider resistor RFB2) to output a comparison signal. The drive circuit DRV drives the upper bridge switch HS (on) and the lower bridge switch LS (off) according to the (low) level of the comparison signal.

[0084] When the instantaneous load change is significant, or when the load is heavy and requires a large current, the comparator CMP selects the voltage with the smallest amplitude from multiple slope voltages Vramp1 to Vrampn and compares it with the output voltage VOUT or its voltage divider to quickly output a pulsed comparison signal. This rapidly increases the output voltage VOUT of the power converter, providing the power required by the load, while effectively preventing the output voltage VOUT from undershooting to an excessively low value.

[0085] Please see Figure 6 This is a circuit diagram of a multi-slope compensation circuit for a power converter with a multi-slope compensation mechanism according to the fourth embodiment of the present invention.

[0086] The fourth embodiment differs from the first embodiment in that the configuration of the multiple first resistors R11 to R1n and the multiple first capacitors C11 in the multi-slope compensation circuit CPN4 of the fourth embodiment is different from the configuration of the multiple first resistors R11 to R1n and the multiple first capacitors C11 to C1n in the multi-slope compensation circuit CPN1 of the first embodiment.

[0087] like Figure 6 As shown, the multi-slope compensation circuit CPN4 of the fourth embodiment of the present invention may include multiple first resistors R11 to Rn, a first capacitor C11, a second resistor R2, and a comparator CMP. If necessary, the multi-slope compensation circuit CPN4 may be configured as follows: Figure 6 The device also includes a second capacitor C2, an error amplifier GMA, or both, but the invention is not limited thereto.

[0088] like Figure 6 As shown, multiple first resistors R11 to R1n are connected in series. That is, the second end of the first resistor R11 is connected to the first end of the first resistor R12, the second end of the first resistor R12 is connected to the first end of the first resistor R13, the second end of the first resistor R13 is connected to the first end of the first resistor R14, and so on. The second end of the last of the multiple first resistors R11 to R1n, namely the first resistor R1n, is coupled to the second reference voltage VREF2.

[0089] The first terminal of the first resistor R11 is connected to the second terminal of the first capacitor C11. The first terminal of the first capacitor C11 is connected to the second terminals of the second resistor R2 and the second terminal of the second capacitor C2. The first terminal of the second resistor R2 is connected to the first terminal of the inductor L1, and the first terminal of the second resistor R2 can be connected to the node SW between the second terminal of the upper bridge switch HS and the lower bridge switch LS. The first terminal of the second capacitor C2 is connected to the second terminal of the inductor L1.

[0090] It is worth noting that the first terminals of the multiple first resistors R11 to R1n are respectively connected to the multiple first input terminals of the comparator CMP, such as the inverting input terminal. The second input terminal of the comparator CMP, such as the non-inverting input terminal, is connected to the output terminal of the error amplifier GMA. Thus, the comparator CMP selects one of the multiple slope voltages Vramp1 to Vrampn and compares it with the error amplification signal output from the error amplifier GMA to the second input terminal of the comparator CMP, such as the non-inverting input terminal, to output a comparison signal. The drive circuit DRV drives the upper bridge switch HS and the lower bridge switch LS according to the comparison signal received from the comparator CMP.

[0091] When the instantaneous load change is significant, or when the load is heavy and requires a large current, the comparator CMP selects the voltage with the smallest amplitude from multiple slope voltages Vramp1 to Vrampn and compares it with the error amplification signal to quickly output the pulse of the comparison signal. This rapidly increases the output voltage VOUT of the power converter, providing the power required by the load, while effectively preventing the output voltage VOUT from undershooting to an excessively low value.

[0092] The other similarities between the fourth embodiment and the first embodiment will not be repeated here.

[0093] In summary, this invention provides a power converter with a multi-slope compensation mechanism. It provides multiple slope voltages and, under different instantaneous load changes, selects a suitable slope voltage and compares it with the sensed voltage of the power converter to enable the power converter to provide an optimal instantaneous load response. Specifically, when the instantaneous load change is large and the instantaneous power requirement is high, a slope voltage with a smaller amplitude is selected and compared with the sensed voltage of the power converter to quickly activate the upper bridge switch. In this way, the power converter can provide sufficient power to the load while preventing the output voltage of the power converter from momentarily dropping to an excessively low value, which could damage the circuit components of the power converter.

[0094] The above-disclosed content is only a preferred embodiment of the present invention and is not intended to limit the claims of the present invention. Therefore, all equivalent technical changes made based on the description and drawings of the present invention are included in the claims of the present invention.

Claims

1. A power converter with a multi-slope compensation mechanism, characterized in that, The power converter with multi-slope compensation mechanism includes: An upper bridge switch, wherein the first terminal of the upper bridge switch is coupled to the input voltage; A lower bridge switch, the first end of which is connected to the second end of the upper bridge switch, the second end of which is grounded, the node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to the first end of an inductor, the second end of the inductor is connected to the first end of an output capacitor, and the second end of the output capacitor is grounded; Multi-slope compensation circuit, including: A plurality of first capacitors, each first capacitor having a first terminal and a second terminal; A comparator, wherein multiple first input terminals of the comparator are respectively connected to the second terminals of multiple first capacitors, and the second input terminal of the comparator is coupled to a first reference voltage; and A plurality of first resistors, the first ends of which are respectively connected to the plurality of first input terminals of the comparator and respectively connected to the second ends of the plurality of first capacitors, the second ends of which are coupled to a second reference voltage; The second resistor has its first end connected to the first end of the inductor and its second end connected to the first end of each of the first capacitors. as well as A driving circuit, wherein the input terminal of the driving circuit is connected to the output terminal of the comparator, and the output terminal of the driving circuit is connected to the control terminal of the upper bridge switch and the control terminal of the lower bridge switch.

2. The power converter with multi-slope compensation mechanism according to claim 1, characterized in that, The multi-slope compensation circuit also includes: The second capacitor has its first terminal connected to the second terminal of the inductor, and its second terminal connected to the first terminal of each of the first capacitors.

3. The power converter with multi-slope compensation mechanism according to claim 1, characterized in that, The multi-slope compensation circuit also includes: An error amplifier is provided, wherein the first input terminal of the error amplifier is connected to the second terminal of the inductor, the second input terminal of the error amplifier is coupled to a third reference voltage, the output terminal of the error amplifier is connected to the second input terminal of the comparator, and the voltage at the output terminal of the error amplifier is the first reference voltage.

4. The power converter with multi-slope compensation mechanism according to claim 3, characterized in that, The power converter with multi-slope compensation mechanism also includes: A voltage divider circuit is provided, wherein the input terminal of the voltage divider circuit is connected to the second terminal of the inductor, and the output terminal of the voltage divider circuit is connected to the first input terminal of the error amplifier.

5. The power converter with multi-slope compensation mechanism according to claim 4, characterized in that, The voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. The first end of the first voltage divider resistor is connected to the second end of the inductor, and the second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor. The node between the second end of the first voltage divider resistor and the first end of the second voltage divider resistor is connected to the first input terminal of the error amplifier. The second end of the second voltage divider resistor is grounded.

6. The power converter with multi-slope compensation mechanism according to claim 1, characterized in that, The second terminal of each of the first resistors is connected to the second terminal of the inductor, and the voltage at the second terminal of the inductor is the second reference voltage.

7. The power converter with multi-slope compensation mechanism according to claim 6, characterized in that, The power converter with multi-slope compensation mechanism also includes: A voltage divider circuit is provided, wherein the input terminal of the voltage divider circuit is connected to the second terminal of the inductor, and the output terminal of the voltage divider circuit is connected to the second terminal of each of the first resistors.

8. The power converter with multi-slope compensation mechanism according to claim 7, characterized in that, The voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. The first end of the first voltage divider resistor is connected to the second end of the inductor. The second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor. The node between the second end of the first voltage divider resistor and the first end of the second voltage divider resistor is connected to the second end of each of the first resistors. The second end of the second voltage divider resistor is grounded. The voltage at the first end of the second voltage divider resistor is the second reference voltage.

9. The power converter with multi-slope compensation mechanism according to claim 1, characterized in that, The second input terminal of the comparator is connected to the second terminal of the inductor, and the voltage at the second terminal of the inductor is the first reference voltage.

10. The power converter with multi-slope compensation mechanism according to claim 9, characterized in that, The power converter with multi-slope compensation mechanism also includes: A voltage divider circuit is provided, wherein the input terminal of the voltage divider circuit is connected to the second terminal of the inductor, and the output terminal of the voltage divider circuit is connected to the second input terminal of the comparator.

11. The power converter with multi-slope compensation mechanism according to claim 10, characterized in that, The voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. The first end of the first voltage divider resistor is connected to the second end of the inductor. The second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor. The node between the second end of the first voltage divider resistor and the first end of the second voltage divider resistor is connected to the second input terminal of the comparator. The second end of the second voltage divider resistor is grounded. The voltage at the first end of the second voltage divider resistor is the first reference voltage.

12. The power converter with multi-slope compensation mechanism according to claim 1, characterized in that, The driving circuit includes a turn-on signal generator connected to the output of the comparator, the control terminal of the upper bridge switch, and the control terminal of the lower bridge switch. It is configured to output an upper bridge turn-on signal to the control terminal of the upper bridge switch and an lower bridge turn-on signal to the control terminal of the lower bridge switch based on the comparison signal output by the comparator.

13. The power converter with multi-slope compensation mechanism according to claim 12, characterized in that, The driving circuit further includes a logic circuit connected to the conduction signal generator, the control terminal of the upper bridge switch, and the control terminal of the lower bridge switch. It is configured to output a first logic signal to the control terminal of the upper bridge switch based on the upper bridge conduction signal, and to output a second logic signal to the control terminal of the lower bridge switch based on the lower bridge conduction signal.

14. The power converter with multi-slope compensation mechanism according to claim 13, characterized in that, The driving circuit further includes a first buffer circuit, the input of which is connected to the output of the logic circuit, and the output of which is connected to the control terminal of the upper bridge switch.

15. The power converter with multi-slope compensation mechanism according to claim 14, characterized in that, The driving circuit also includes a second buffer circuit, the input of which is connected to the output of the logic circuit, and the output of which is connected to the control terminal of the lower bridge switch.

16. A power converter with a multi-slope compensation mechanism, characterized in that, The power converter with multi-slope compensation mechanism includes: An upper bridge switch, wherein the first terminal of the upper bridge switch is coupled to the input voltage; A lower bridge switch, the first end of which is connected to the second end of the upper bridge switch, the second end of which is grounded, the node between the first end of the lower bridge switch and the second end of the upper bridge switch is connected to the first end of an inductor, the second end of the inductor is connected to the first end of an output capacitor, and the second end of the output capacitor is grounded; Multi-slope compensation circuit, including: The first capacitor has a first terminal and a second terminal; A comparator having a second input terminal and a plurality of first input terminals, wherein the second input terminal of the comparator is coupled to a first reference voltage; A plurality of first resistors are connected in series with each other. The first ends of the plurality of first resistors are respectively connected to the plurality of first input terminals of the comparator. The first end of one of the first resistors is also connected to the second end of the first capacitor. The second end of another first resistor is coupled to a second reference voltage. The second ends of each of the other first resistors, except for the other first resistor, are connected to the first ends of the adjacent first resistors. and The second resistor has its first end connected to the first end of the inductor and its second end connected to the first end of the first capacitor. as well as A driving circuit, wherein the input terminal of the driving circuit is connected to the output terminal of the comparator, and the output terminal of the driving circuit is connected to the control terminal of the upper bridge switch and the control terminal of the lower bridge switch.

17. The power converter with multi-slope compensation mechanism according to claim 16, characterized in that, The multi-slope compensation circuit also includes: The second capacitor has its first terminal connected to the second terminal of the inductor, and its second terminal connected to the first terminal of the first capacitor.

18. The power converter with multi-slope compensation mechanism according to claim 16, characterized in that, The multi-slope compensation circuit also includes: An error amplifier is provided, wherein the first input terminal of the error amplifier is connected to the second terminal of the inductor, the second input terminal of the error amplifier is coupled to a third reference voltage, the output terminal of the error amplifier is connected to the second input terminal of the comparator, and the voltage at the output terminal of the error amplifier is the first reference voltage.

19. The power converter with multi-slope compensation mechanism according to claim 18, characterized in that, The power converter with multi-slope compensation mechanism also includes: A voltage divider circuit is provided, wherein the input terminal of the voltage divider circuit is connected to the second terminal of the inductor, and the output terminal of the voltage divider circuit is connected to the first input terminal of the error amplifier.

20. The power converter with multi-slope compensation mechanism according to claim 19, characterized in that, The voltage divider circuit includes a first voltage divider resistor and a second voltage divider resistor. The first end of the first voltage divider resistor is connected to the second end of the inductor, and the second end of the first voltage divider resistor is connected to the first end of the second voltage divider resistor. The node between the second end of the first voltage divider resistor and the first end of the second voltage divider resistor is connected to the first input terminal of the error amplifier. The second end of the second voltage divider resistor is grounded.

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