Peripheral interface timing parameter adaptive adjustment method and timing parameter adjustment device

Abstract

The present application relates to a method and a device for adaptively adjusting the interface timing parameters of a peripheral device. The method adaptively adjusts the interface timing parameters of the peripheral device according to a preset adjustment step based on an initialization signal to the peripheral device. The preset adjustment step includes: adjusting the interface timing parameters according to a preset timing parameter value, adjusting the interface timing parameters by adjusting the setup time parameter value in the timing parameter value, and adjusting the interface timing parameters by adjusting the hold time parameter value in the timing parameter value. When adjusting the interface timing parameters according to the preset adjustment step, a data read and write operation is performed under the interface timing parameters obtained after the adjustment in the current step. If successful, the operating frequency obtained in the current step is used as a candidate interface timing parameter. If unsuccessful, the adjustment of the next step is performed, and the data read and write operation results of each step are recorded. Under the candidate interface timing parameters, the data read and write operation is performed again. If successful, the interface timing parameters of the peripheral device are adaptively adjusted. If unsuccessful, the step corresponding to the success is returned, and the interface timing parameters are adjusted again according to the preset adjustment step. The method can realize adaptive adjustment of interface timing parameters of peripheral components, thereby avoiding manual operation and improving efficiency.

Description

Technical Field

[0001] The present application relates to the field of single-chip integrated circuit technology, and in particular to a method for adaptively adjusting timing parameters of a peripheral interface and a timing parameter adjustment device. Background Art

[0002] With the development of the integrated circuit industry, the main frequency of DSP (digital signal processing) chips is getting higher and higher. For peripheral interfaces, the general design is to work in the N-frequency state of the main frequency. (For example, the DSP main frequency is 400MHz, and the slow peripherals work in the four-frequency state of the main frequency, that is, 100MHz). When the DSP needs to be overclocked or downclocked, the operating frequency of the corresponding peripheral will also change, resulting in a change in the actual time controlled by the timing parameter register. The change in time will cause the interface timing to not meet the requirements of the standard protocol, resulting in data transmission failure. The timing parameter register can be used to control the setup time and hold time of the data signal of the peripheral interface relative to the clock signal. The register is generally used to record the number of cycles of the setup / hold time. If the setup time is configured as 4 and the hold time is configured as 3, the setup time on this peripheral interface is 5T and the hold time is 4T. T represents the working clock cycle of the peripheral component, that is, the value in the register + 1 cycle number.

[0003] However, the current conventional processing method is that when changing the DSP main frequency, the user needs to modify the value of the peripheral interface timing register parameter through software to meet the timing requirements under the current peripheral operating frequency. In another case, when the chip and the corresponding peripheral components are connected together through a PCB board, due to external interference such as unequal lengths that may exist during the design process of the PCB, the user needs to constantly try to adjust the value of the interface timing parameter register, and even use an oscilloscope / logic analyzer to capture the interface waveform for analysis, and then modify the value of the peripheral interface timing register parameter to meet the current peripheral interface timing requirements. This results in the deviation of the peripheral interface timing due to any of the above reasons, and the user needs to constantly try to modify the timing parameter register through software to meet the timing requirements. Although this problem can be solved, it requires the user to manually configure and adjust, and the steps are cumbersome, and adaptive adjustment cannot be achieved. Summary of the invention

[0004] Based on this, it is necessary to provide a method and a timing parameter adjustment device that can adaptively adjust the timing parameters of the peripheral interface with timing parameters in the DSP chip in order to solve the above technical problems.

[0005] A method for adaptively adjusting a timing parameter of a peripheral interface, the method comprising:

[0006] Get the initialization signal of the peripheral component;

[0007] According to the initialization signal, the interface timing parameters of the peripheral component are adaptively adjusted according to the preset adjustment steps, wherein the preset adjustment steps sequentially include: adjusting the timing of the peripheral component interface signal line according to the preset timing parameter value, adjusting the timing of the peripheral component interface signal line by adjusting the setup time parameter value in the timing parameter value, and adjusting the timing of the peripheral component interface signal line by adjusting the hold time parameter value in the timing parameter value;

[0008] After adjusting the interface timing parameters according to the preset adjustment steps, a data read / write operation is performed under the interface timing obtained after the adjustment in the current step. If successful, the interface timing parameters obtained in the current step are used as candidate timing parameters. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read / write operation results of each step are recorded;

[0009] Under the candidate timing parameters, perform two more data read and write operations. If successful, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If unsuccessful, return the steps corresponding to the success according to the data read and write operation results, and re-adjust the peripheral interface timing according to the preset adjustment steps.

[0010] In one of the embodiments, in the preset adjustment step, before adjusting the operating frequency according to the preset timing parameter value, a data read and write operation is first performed on the peripheral component at the chip main frequency. If successful, the default interface timing parameters are used as candidate timing parameters. If unsuccessful, the interface timing parameters are adaptively adjusted according to the preset adjustment step, and the data read and write operation results are recorded.

[0011] In one embodiment, when adjusting the interface timing according to the preset timing parameter value:

[0012] The interface timing is adjusted according to the preset first timing parameter value, and a data read and write operation is performed under the adjusted interface timing. If successful, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter;

[0013] If it fails, the result of the data read / write operation is recorded, and the interface timing is adjusted according to the preset second timing parameter value. Under the adjusted interface timing, a data read / write operation is performed. If it succeeds, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter.

[0014] If it fails, the result of the data read / write operation is recorded, and the interface timing parameters are adjusted according to the preset third timing parameter value. Under the adjusted interface timing, a data read / write operation is performed. If it succeeds, the interface timing parameters obtained in the current step are used as candidate interface timing parameters.

[0015] If it fails, the result of the data read and write operation is recorded, and the setup time parameter value in the timing parameter value is adjusted.

[0016] In one embodiment, the preset third timing parameter value is the timing parameter value after the last interface timing parameter adaptive adjustment is successful.

[0017] In one embodiment, when adjusting the setup time parameter value in the timing parameter value:

[0018] On the basis of the third timing parameter value, gradually increase the setup time parameter value according to a preset step length, and after each increase in the setup time parameter value, perform a data read and write operation, and if successful, use the interface timing parameter obtained in the current step as a candidate interface timing parameter;

[0019] If it fails, the result of the data read / write operation is recorded, and based on the third timing parameter value, the setup time parameter value is gradually reduced according to the preset step length. After each adjustment of the setup time parameter value, a data read / write operation is performed. If it succeeds, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter;

[0020] If it fails, the result of the data read and write operation is recorded, and the hold time parameter value in the timing parameter value is adjusted.

[0021] In one embodiment, when adjusting the hold time parameter value in the timing parameter value:

[0022] On the basis of the third timing parameter value, gradually increase the holding time parameter value according to the preset step length, and after each increase in the holding time parameter value, perform a data read and write operation, and if successful, use the interface timing parameter obtained in the current step as a candidate interface timing parameter;

[0023] If it fails, the result of the data read / write operation is recorded, and based on the third timing parameter value, the holding time parameter value is gradually reduced according to the preset step length. After each time the holding time parameter value is reduced, a data read / write operation is performed. If it succeeds, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter;

[0024] If it fails, the result of the data read and write operation is recorded, the timing parameter adjustment failure result is output, and an interrupt program signal is sent.

[0025] The present application also provides a timing parameter adjustment device, which is arranged in a DSP chip and includes a frequency adaptive adjustment module, a timing parameter register, a transmission detection register and a timing shadow register module;

[0026] The interface timing parameter adaptive adjustment module is used to obtain an initialization signal of a peripheral component, and adaptively adjust the interface timing parameters of the peripheral component according to the initialization signal and the preset adjustment steps, wherein the preset adjustment steps sequentially include: loading a preset timing parameter value from the timing shadow register module to the timing parameter register to adjust the interface timing parameter, adjusting the interface timing parameter by adjusting the setup time parameter value in the timing parameter register, and adjusting the interface timing parameter by adjusting the hold time parameter value in the timing parameter register;

[0027] When adjusting the timing parameters in the timing parameter register according to the preset adjustment steps, a data read / write operation is performed under the interface timing parameters obtained after the adjustment in the current step. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read / write operation results of each step are recorded in the transmission detection register;

[0028] Under the candidate operating frequency, perform two more data read and write operations. If successful, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If unsuccessful, return to the steps corresponding to the success according to the data read and write operation results recorded in the transmission detection register, and re-adjust the interface timing parameters according to the preset adjustment steps.

[0029] In one embodiment, the timing shadow register module includes three timing shadow registers, each storing a preset different timing parameter value.

[0030] In one embodiment, the timing shadow register module and the timing parameter register belong to the same register group.

[0031] The above-mentioned interface timing parameter adaptive adjustment method and timing parameter adjustment device for peripherals, according to the initialization signal of the peripheral component, according to the preset adjustment steps, the interface timing parameters of the peripheral component are adaptively adjusted, wherein the preset adjustment steps include: adjusting the interface timing parameters according to the preset timing parameter value, adjusting the interface timing parameters by adjusting the setup time parameter value in the timing parameter value, and adjusting the interface timing parameters by adjusting the hold time parameter value in the timing parameter value. When the interface timing parameters are adjusted according to the preset adjustment steps, a data read and write operation is performed under the interface timing parameters obtained after the adjustment of the current step. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters. If failed, the next step is adjusted, and the data read and write operation results of each step are recorded. Under the candidate interface timing parameters, two more data read and write operations are performed. If successful, the interface timing parameters of the peripheral component are adaptively adjusted. If failed, the step corresponding to the success is returned according to the data read and write operation results, and the interface timing parameters are adjusted again according to the preset adjustment steps. The method can realize automatic adaptive adjustment of interface timing parameters of peripheral components to improve efficiency. BRIEF DESCRIPTION OF THE DRAWINGS

[0032] Figure 1 A schematic diagram of connecting an external device to a DSP chip in one embodiment;

[0033] Figure 2 A schematic diagram of a flow chart of a method for adaptively adjusting timing parameters of a peripheral interface in one embodiment;

[0034] Figure 3 A flowchart of a method for adaptively adjusting interface timing parameters in an embodiment;

[0035] Figure 4 FIG. 4 is a diagram showing the internal structure of a computer device in one embodiment. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0037] like Figure 1 As shown in FIG. 1 , when a peripheral component (external device) is connected to a DSP chip through a peripheral interface, the peripheral interface timing needs to be adjusted to match the operating frequency of the peripheral component. In the prior art, the interface timing parameters provided by the DSP chip to the peripheral component need to be manually configured and adjusted, and the steps are cumbersome. Figure 2As shown, a method for adaptively adjusting the timing parameters of a peripheral interface is provided, which specifically includes the following steps:

[0038] Step S100, obtaining an initialization signal of a peripheral component.

[0039] Step S110, according to the initialization signal, adaptively adjust the interface timing parameters of the peripheral components according to the preset adjustment steps, wherein the preset adjustment steps include in sequence: adjusting the interface timing parameters according to the preset timing parameter values, adjusting the interface timing parameters by adjusting the setup time parameter values ​​in the timing parameter values, and adjusting the interface timing parameters by adjusting the hold time parameter values ​​in the timing parameter values.

[0040] Step S120, when the interface timing parameters are adjusted according to the preset adjustment steps, a data read and write operation is performed under the interface timing parameters obtained after the adjustment of the current step. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read and write operation results of each step are recorded.

[0041] Step S130, perform two more data read and write operations under the candidate interface timing parameters. If successful, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If unsuccessful, return to the step corresponding to the success record according to the data read and write operation result, and re-adjust the interface timing parameters according to the preset adjustment steps.

[0042] In this embodiment, during the initialization phase of the peripheral interface, the connectivity of the peripheral is checked, and when it is found that the timing is not satisfied, that is, data reading and writing operations cannot be performed, adaptive adjustments are made according to preset steps until correct reading and writing transmissions can be performed, thereby reducing the need for manual configuration adjustments.

[0043] In step S100, an initialization signal of the peripheral component is obtained, that is, after the peripheral component is connected to the DSP chip through the peripheral interface, the DSP chip senses that a device is connected to the peripheral interface, and performs an initialization operation on it.

[0044] In steps S110-120, in the preset adjustment step, before adjusting the interface timing parameters according to the preset timing parameter values, a data read and write operation is first performed on the peripheral components at the chip main frequency. If successful, the default interface timing parameters are used as candidate operating frequencies. If unsuccessful, the interface timing parameters are adaptively adjusted according to the preset adjustment steps, and the data read and write operation results are recorded.

[0045] In this embodiment, in the preset adjustment step, the relevant timing parameters in the timing register are first adjusted according to the preset timing parameter values, and data read and write operations are performed on the external device under the interface timing parameters obtained after the adjustment. If unsuccessful, the setup time parameter value and the hold time parameter value in the timing parameters are then adjusted.

[0046] In this embodiment, the timing parameter value in the timing register is actually adjusted to adjust the setup / hold time of the peripheral interface signal line to obtain different interface timing parameters, and the DSP chip and the peripheral device communicate data through the timing parameters.

[0047] In this embodiment, when adjusting the interface timing parameters according to the preset timing parameter values, the adjustments are performed in sequence according to the preset first timing parameter value, the second timing parameter value, and the third timing parameter value.

[0048] Specifically, the interface timing parameters are first adjusted according to the preset first timing parameter value, and a data read and write operation is performed under the adjusted interface timing parameters. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters, and then subsequent operations are performed according to step S130.

[0049] Specifically, after the adjustment according to the first timing parameter value fails, the result of the data read and write operation is recorded, and the operating frequency is adjusted according to the preset second timing parameter value. Under the adjusted interface timing parameters, a data read and write operation is performed. If successful, the operating frequency obtained in the current step is used as a candidate interface timing parameter, and then subsequent operations are performed according to step S130.

[0050] Specifically, after the adjustment according to the second timing parameter value fails, the result of the data read and write operation is recorded, and the interface timing parameters are adjusted according to the preset third timing parameter value. A data read and write operation is performed at the adjusted operating frequency. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters. After that, subsequent operations are performed according to step S130.

[0051] Specifically, after the adjustment according to the third timing parameter value fails, similarly, the result of the data read and write operation is recorded, and then the setup time parameter value in the timing parameter value is adjusted.

[0052] In this embodiment, the first timing parameter value and the second timing parameter value can be preset based on experience. When adjusting according to the first timing parameter value, it can be assumed that the current error situation is caused by the chip main frequency exceeding the operating frequency of the peripheral component, which is equivalent to the operating frequency of the peripheral interface being higher than the operating frequency of the peripheral component. Then the first timing parameter value can be preset to a timing parameter value that can reduce the chip main frequency. On the contrary, when adjusting according to the second timing parameter value, it can be assumed that the current error situation is caused by the chip main frequency being lower than the operating frequency of the peripheral component, which is equivalent to the operating frequency of the peripheral interface being lower than the operating frequency of the peripheral component. Then the second timing parameter can be preset to a timing parameter value that can increase the chip main frequency.

[0053] In this embodiment, the third timing parameter value can be preset as the timing parameter value after the last successful interface timing parameter adaptive adjustment. And when the setup time parameter value and the hold time parameter value are adjusted, the third timing parameter value is used as the initial value for adjustment.

[0054] In this embodiment, when adjusting the establishment time parameter value in the timing parameter value: on the basis of the third timing parameter value, the establishment time parameter value is gradually increased according to the preset step size, and after each increase in the establishment time parameter value, a data read and write operation is performed. If successful, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter, and then subsequent operations are performed according to step S130.

[0055] In this embodiment, if the adjustment of the setup time parameter value fails, the result of the data read and write operation is recorded, and the setup time parameter value is gradually reduced according to the preset step size based on the third timing parameter value. After each adjustment of the setup time parameter value, a data read and write operation is performed. If successful, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter. If the adjustment of the setup time parameter value fails twice, the result of the data read and write operation is recorded, and then the hold time parameter value in the timing parameter value is adjusted.

[0056] In this embodiment, when adjusting the establishment time parameter value, multiple adjustments are made according to the preset step size, and a read and write operation is performed after each adjustment. If it fails, the establishment time parameter value is increased or decreased again according to the step size until it reaches the preset maximum adjustment value or the minimum adjustment value. If it still fails, the adjustment result of this step is recorded as failure.

[0057] In this embodiment, when adjusting the hold time parameter value in the timing parameter value: similarly, based on the third timing parameter value, the hold time parameter value is gradually increased according to the preset step size, and after each increase in the hold time parameter value, a data read and write operation is performed. If successful, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter, and then subsequent operations are performed according to step S130.

[0058] In this embodiment, if the adjustment of the holding time parameter value to increase fails, the result of the data read and write operation is recorded, and based on the third timing parameter value, the holding time parameter value is gradually reduced according to the preset step length. After each reduction of the holding time parameter value, a data read and write operation is performed. If successful, the interface timing parameter obtained in the current step is used as a candidate interface timing parameter, and then subsequent operations are performed according to step S130. If both adjustments to the holding time parameter value fail, the result of the data read and write operation is recorded, the timing parameter adjustment failure result is output, and an interrupt program signal is sent.

[0059] Similarly, when adjusting the hold time parameter value, multiple adjustments are made according to the preset step size, and a read and write operation is performed after each adjustment. If it fails, the hold time parameter value is increased or decreased again according to the step size until it reaches the preset maximum adjustment value or the minimum adjustment value. If it still fails, the adjustment result of this step is recorded as failure.

[0060] In this embodiment, the entire preset adjustment step actually includes 10 steps, which are:

[0061] Step 1: Use the main frequency as the working frequency and perform a data read and write operation on the peripheral component. If successful, perform step S120; if unsuccessful, perform step 2;

[0062] Step 2: Set the timing parameter register according to the first timing parameter value, and perform a data read and write operation on the peripheral component at the adjusted working frequency. If successful, perform step S120, and if unsuccessful, perform step 3;

[0063] Step 3: Set the timing parameter register according to the second timing parameter value, and perform a data read and write operation on the peripheral component at the adjusted working frequency. If successful, perform step S120, and if unsuccessful, perform step 4;

[0064] Step 4: Set the timing parameter register according to the third timing parameter value, and perform a data read and write operation on the peripheral component at the adjusted working frequency. If successful, perform step S120, and if unsuccessful, perform step 5;

[0065] Step 5: Based on the third timing parameter value, gradually increase the setup time parameter value, and perform a data read and write operation on the peripheral component at the adjusted working frequency. If successful, perform step S120, and if unsuccessful, perform step 6;

[0066] Step 6: Based on the third timing parameter value, the setup time parameter value is gradually reduced, and a data read and write operation is performed on the peripheral component at the adjusted working frequency. If successful, step S120 is performed, and if failed, step 7 is performed;

[0067] Step 7: Based on the third timing parameter value, gradually increase the hold time parameter value, and perform a data read and write operation on the peripheral component at the adjusted working frequency. If successful, perform step S120, and if unsuccessful, perform step 8;

[0068] Step 8: Based on the third timing parameter value, the hold time parameter value is gradually reduced, and a data read and write operation is performed on the peripheral component at the adjusted working frequency. If successful, step S120 is implemented, and if failed, step 10 is performed.

[0069] Specifically, step 10 is that the timing parameter adjustment fails, the initialization is not completed, and it is recorded. At the same time, an interrupt is issued to the interrupt response program.

[0070] In step S120, in order to avoid the accidental correct data transmission, which is not repeatable, two more read and write checks of different types of data are required at the candidate operating frequency. If both are transmitted correctly, it can be considered that the timing parameter adjustment is successful, the initialization of the peripheral component is completed, and the record is made. At the same time, the parameters in the current timing register are retained as the third timing parameter for the next adaptive adjustment of the peripheral component. If the transmission fails, it can be considered that an accidental correct data transmission has occurred, but it is not repeatable, and the current timing parameter configuration is still in an unreasonable state, then it is necessary to return to the steps corresponding to the success in the recorded data read and write operation results, and adjust the timing parameters again according to the preset adjustment steps.

[0071] like Figure 3 As shown, it is the whole adaptive adjustment process, wherein step S120 is step9.

[0072] In the above-mentioned method for adaptively adjusting the timing parameters of the peripheral interface, after the peripheral component is connected to the DSP chip, the interface timing parameters provided by the main chip to the peripheral component are adjusted according to the given timing parameter adjustment steps. At the same time, two different types of data are read and written under the candidate interface timing parameters. On the basis of realizing the adaptive adjustment of the interface timing parameters of the peripheral component, it is also ensured that the interface timing parameters finally obtained are valid.

[0073] It should be understood that although Figure 1 The steps in the flowchart are shown in sequence as indicated by the arrows, but these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise specified in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least part of the steps may include multiple sub-steps or multiple stages. These sub-steps or stages are not necessarily executed at the same time, but can be executed at different times. The execution order of these sub-steps or stages is not necessarily sequential, but can be executed in turn or alternately with other steps or at least part of the sub-steps or stages of other steps.

[0074] The present application also provides a timing parameter adjustment device, which is arranged in a DSP chip and includes an interface timing parameter adaptive adjustment module, a timing parameter register, a transmission detection register and a timing shadow register module.

[0075] Among them, the interface timing parameter adaptive adjustment module is used to obtain the initialization signal of the peripheral component, and according to the initialization signal, the interface timing parameters of the peripheral component are adaptively adjusted according to the preset adjustment steps, wherein the preset adjustment steps include in sequence: loading the preset timing parameter value from the timing shadow register module to the timing parameter register to adjust the interface timing parameters, adjusting the interface timing parameters by adjusting the setup time parameter value in the timing parameter register, and adjusting the interface timing parameters by adjusting the hold time parameter value in the timing parameter register.

[0076] When adjusting the timing parameters in the timing parameter register according to the preset adjustment steps, a data read and write operation is performed under the interface timing parameters obtained after the adjustment of the current step. If successful, the operating frequency obtained in the current step is used as a candidate interface timing parameter. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read and write operation results of each step are recorded in the transmission detection register.

[0077] Under the candidate interface timing parameters, perform two more data read and write operations. If successful, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If unsuccessful, return to the steps corresponding to the success according to the data read and write operation results recorded in the transmission detection register, and re-adjust the interface timing parameters according to the preset adjustment steps.

[0078] In this embodiment, the interface timing parameter adaptive adjustment module may be a part of the control module in the DSP chip. The interface timing parameter adaptive adjustment module adjusts the timing parameters in the timing parameter register according to the above-mentioned peripheral interface timing parameter adaptive adjustment method, that is, the interface signal setup / hold time provided by the chip to the peripheral component is adaptively adjusted. The process refers to the above-mentioned explanation of the interface timing parameter adaptive adjustment method for the peripheral component, and will not be repeated here.

[0079] In this embodiment, the timing shadow register module includes three timing shadow registers, which respectively store different preset timing parameter values.

[0080] Preferably, the timing shadow register module includes a first timing shadow register, a second timing shadow register and a third timing shadow register, which respectively store a first timing parameter value, a second timing parameter value and a third timing parameter value, i.e., the timing parameter values ​​obtained after the last successful adaptive adjustment.

[0081] In this embodiment, according to the different peripheral components, the timing shadow register module and the timing parameter register belong to the same register group. For peripherals with simple interfaces, the timing shadow register and the timing parameter register both contain one setup time register and one hold time register, and they are in a one-to-one correspondence. Each time, the preset value is loaded from the setup time register of the timing shadow register to the setup time register in the timing parameter register. For peripherals with complex interfaces, the timing shadow register and the timing parameter register may contain multiple sets of setup time registers and hold time registers, so they also need to be in a one-to-one correspondence.

[0082] In this embodiment, the transmission detection register is used to record whether the timing parameters are adjusted successfully in each step, and the result of the corresponding step is recorded in a fixed position in the register. In this way, when the read and write verification of different data fails twice during the implementation of Step 9, the corresponding step can be returned to readjust according to the value recorded in the transmission detection register.

[0083] Specifically, the setting of the transmission detection register is shown in Table 1.

[0084] Table 1 Transmission Detection Register Bit Description

[0085]

[0086]

[0087] In this embodiment, according to the method for adaptively adjusting the timing parameters of the peripheral interface, the frequency adaptive adjustment module specifically implements the following steps:

[0088] Step 1: When the peripheral component is initialized, it first performs a data write and read operation through the transmission detection register. If successful, it jumps directly to step 9. If the read data is wrong, it is marked in the transmission detection register and step 2 is performed.

[0089] Step 2: Assume that the current error is that the chip main frequency exceeds the predetermined operating frequency. At this time, it is equivalent to that the operating frequency of the peripheral interface is higher than the predetermined operating frequency. At this time, the setup and hold time calculated according to the initial value of the timing parameter register does not meet the requirements of the interface protocol. Then, based on the empirical value, load the timing parameter value from the timing shadow register 1 to the timing parameter register. And re-perform the data write and read operation. If successful, jump directly to step 9. If failed, mark it in the transmission detection register and proceed to step 3.

[0090] Step 3: Assume that the current error is that the chip main frequency is significantly lower than the predetermined operating frequency. At this time, it is equivalent to that the peripheral interface operating frequency is lower than the predetermined operating frequency. At this time, the setup and hold time calculated according to the initial value of the timing parameter register does not meet the requirements of the interface protocol. Then, based on the empirical value, load the timing parameter value from the timing shadow register 2 to the timing parameter register. And re-perform the data write and read operation. If successful, jump directly to step 9. If failed, mark it in the transmission detection register and proceed to step 4.

[0091] Step 4: Load the timing parameter value from the timing shadow register 3 to the timing parameter register. Perform the data write and read operation again. If successful, jump directly to step 9. If failed, mark it in the transmission detection register and proceed to step 5.

[0092] Step 5: Reset the value of the timing parameter register and fix the hold time parameter value. According to the record in the transmission detection register, gradually increase the setup time parameter value and re-perform the read and write test. If successful, jump directly to step 9. If failed, record it in the transmission detection register and proceed to step 6.

[0093] Step 6: Reset the value of the timing parameter register and fix the hold time parameter value. According to the record in the transmission detection register, gradually reduce the setup time parameter value, and then re-perform the read and write test. If successful, jump directly to step 9. If failed, record it in the transmission detection register and proceed to step 7.

[0094] Step 7: Reset the value of the timing parameter register and fix the establishment time parameter value. According to the record in the transmission detection register, gradually increase the hold time parameter value, and then re-perform the read and write test. If successful, jump directly to step 9. If failed, record it in the transmission detection register and proceed to step 8.

[0095] Step 8: Reset the value of the timing parameter register and fix the establishment time parameter value. According to the record in the transmission detection register, gradually reduce the hold time parameter value, and then re-perform the read and write test. If successful, jump directly to step 9. If failed, record it in the transmission detection register and proceed to step 10.

[0096] Step 9: Perform two additional write and read checks on different data. If both are transmitted correctly, the timing parameter adjustment is successful, the initialization is completed, and the data is recorded in the transmission detection register. At the same time, the configuration of the timing parameter register in the current state is saved to the shadow register 3; if the transmission fails, the data is recorded in the transmission detection register, and the timing parameter adaptive adjustment of the next stage is performed according to the value of the transmission detection register.

[0097] Step 10: The timing parameter adjustment fails and the initialization is not completed. The information is recorded in the transmission detection register. At the same time, an interrupt is sent to the interrupt response program.

[0098] In the above-mentioned interface timing parameter adaptive adjustment module, a transmission detection register is added in the hardware design. When the peripheral component is initialized, the initialization control logic starts to work according to the transmission detection register, performs write and read access detection on the peripheral, and adaptively adjusts the value of the timing parameter register to ensure that the data communication between the peripheral component and the external device is normal. The newly added timing parameter shadow register group can improve the efficiency of the timing parameter adaptive adjustment based on experience. According to theoretical and empirical values, three timing parameter shadow registers can be pre-designed. Usually, timing shadow registers 1 and 2 are non-writable read-only registers used to save the preset timing parameters of the peripheral interface. Among them, timing shadow register 3 can save the timing parameter value of normal transmission after the last adaptive adjustment, and can also be configured by the user before the adaptive adjustment of the timing parameters. The register is only controlled by the chip reset, not by the reset control of the peripheral component. This module can perform adaptive adjustment on the timing parameters of the peripheral interface, reducing the cumbersome manual adjustment process of the user. The timing parameter shadow register can be set according to experience to improve the efficiency of adaptive adjustment.

[0099] In one embodiment, a computer device is provided. The computer device may be a terminal, and its internal structure diagram may be as follows: Figure 4 As shown. The computer device includes a processor, a memory, a network interface, a display screen and an input device connected through a system bus. Among them, the processor of the computer device is used to provide computing and control capabilities. The memory of the computer device includes a non-volatile storage medium and an internal memory. The non-volatile storage medium stores an operating system and a computer program. The internal memory provides an environment for the operation of the operating system and the computer program in the non-volatile storage medium. The network interface of the computer device is used to communicate with an external terminal through a network connection. When the computer program is executed by the processor, a method for adaptively adjusting the interface timing parameters for peripheral components is implemented. The display screen of the computer device can be a liquid crystal display screen or an electronic ink display screen, and the input device of the computer device can be a touch layer covered on the display screen, or a key, trackball or touchpad set on the computer device housing, or an external keyboard, touchpad or mouse, etc.

[0100] Those skilled in the art will understand that Figure 4 The structure shown in the figure is only a block diagram of a part of the structure related to the solution of the present application, and does not constitute a limitation on the computer device to which the solution of the present application is applied. The specific computer device may include more or fewer components than those shown in the figure, or combine certain components, or have a different arrangement of components.

[0101] In one embodiment, a computer device is provided, including a memory and a processor, wherein a computer program is stored in the memory, and when the processor executes the computer program, the following steps are implemented:

[0102] Get the initialization signal of the peripheral component;

[0103] According to the initialization signal, the operating frequency of the peripheral component is adaptively adjusted according to the preset adjustment steps, wherein the preset adjustment steps sequentially include: adjusting the interface timing parameters according to the preset timing parameter values, adjusting the interface timing parameters by adjusting the setup time parameter values ​​in the timing parameter values, and adjusting the interface timing parameters by adjusting the hold time parameter values ​​in the timing parameter values;

[0104] When the interface timing parameters are adjusted according to the preset adjustment steps, a data read / write operation is performed under the interface timing parameters obtained after the adjustment in the current step. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read / write operation results of each step are recorded.

[0105] Under the candidate interface timing parameters, perform two more data read and write operations. If successful, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If unsuccessful, return the steps corresponding to the success according to the data read and write operation results, and re-adjust the interface timing parameters according to the preset adjustment steps.

[0106] In one embodiment, a computer readable storage medium is provided, on which a computer program is stored, and when the computer program is executed by a processor, the following steps are implemented:

[0107] Get the initialization signal of the peripheral component;

[0108] According to the initialization signal, the interface timing parameters of the peripheral components are adaptively adjusted according to the preset adjustment steps, wherein the preset adjustment steps sequentially include: adjusting the interface timing parameters according to the preset timing parameter values, adjusting the interface timing parameters by adjusting the setup time parameter values ​​in the timing parameter values, and adjusting the interface timing parameters by adjusting the hold time parameter values ​​in the timing parameter values;

[0109] When the interface timing parameters are adjusted according to the preset adjustment steps, a data read / write operation is performed under the interface timing parameters obtained after the adjustment in the current step. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read / write operation results of each step are recorded.

[0110] Under the candidate interface timing parameters, perform two more data read and write operations. If successful, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If unsuccessful, return the steps corresponding to the success according to the data read and write operation results, and re-adjust the interface timing parameters according to the preset adjustment steps.

[0111] Those skilled in the art can understand that all or part of the processes in the above-mentioned embodiment methods can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to memory, storage, database or other media used in the embodiments provided in this application can include non-volatile and / or volatile memory. Non-volatile memory can include read-only memory (ROM), programmable ROM (PROM), electrically programmable ROM (EPROM), electrically erasable programmable ROM (EEPROM) or flash memory. Volatile memory can include random access memory (RAM) or external cache memory. As an illustration and not limitation, RAM is available in many forms, such as static RAM (SRAM), dynamic RAM (DRAM), synchronous DRAM (SDRAM), double data rate SDRAM (DDRSDRAM), enhanced SDRAM (ESDRAM), synchronous link (Synchlink) DRAM (SLDRAM), memory bus (Rambus) direct RAM (RDRAM), direct memory bus dynamic RAM (DRDRAM), and memory bus dynamic RAM (RDRAM).

[0112] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0113] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the attached claims.

Claims

1. A method for adaptively adjusting the timing parameters of a peripheral interface, characterized in that: The method comprises: Get the initialization signal of the peripheral component; According to the initialization signal, the interface timing parameters of the peripheral component are adaptively adjusted according to the preset adjustment steps, wherein the preset adjustment steps sequentially include: adjusting the timing of the peripheral component interface signal line according to the preset timing parameter value, adjusting the timing of the peripheral component interface signal line by adjusting the setup time parameter value in the timing parameter value, and adjusting the timing of the peripheral component interface signal line by adjusting the hold time parameter value in the timing parameter value, specifically: When adjusting the interface timing according to the preset timing parameter value: adjusting the interface timing according to the preset first timing parameter value, performing a data read and write operation under the adjusted interface timing, if successful, using the interface timing parameter obtained in the current step as a candidate interface timing parameter, if failed, recording the result of the data read and write operation, and adjusting the interface timing according to the preset second timing parameter value, performing a data read and write operation under the adjusted interface timing, if successful, using the interface timing parameter obtained in the current step as a candidate interface timing parameter, if failed, recording the result of the data read and write operation, and adjusting the interface timing parameters according to the preset third timing parameter value, performing a data read and write operation under the adjusted interface timing, if successful, using the interface timing parameter obtained in the current step as a candidate interface timing parameter, if failed, recording the result of the data read and write operation, and adjusting the setup time parameter value in the timing parameter value; When adjusting the setup time parameter value in the timing parameter value: on the basis of the third timing parameter value, gradually increase the setup time parameter value according to the preset step length, and after each increase in the setup time parameter value, perform a data read and write operation, if successful, use the interface timing parameter obtained in the current step as a candidate interface timing parameter, if unsuccessful, record the result of the data read and write operation, and on the basis of the third timing parameter value, gradually decrease the setup time parameter value according to the preset step length, and after each decrease in the setup time parameter value, perform a data read and write operation, if successful, use the interface timing parameter obtained in the current step as a candidate interface timing parameter, if unsuccessful, record the result of the data read and write operation, and adjust the hold time parameter value in the timing parameter value; When adjusting the hold time parameter value in the timing parameter value: based on the third timing parameter value, gradually increase the hold time parameter value according to the preset step length, and after each increase in the hold time parameter value, perform a data read and write operation, if successful, use the interface timing parameter obtained in the current step as a candidate interface timing parameter, if unsuccessful, record the result of the data read and write operation, and based on the third timing parameter value, gradually decrease the hold time parameter value according to the preset step length, and after each decrease in the hold time parameter value, perform a data read and write operation, if successful, use the interface timing parameter obtained in the current step as a candidate interface timing parameter, if unsuccessful, record the result of the data read and write operation, output the timing parameter adjustment failure result, and send an interrupt program signal; After adjusting the interface timing parameters according to the preset adjustment steps, a data read / write operation is performed under the interface timing obtained after the adjustment in the current step. If successful, the interface timing parameters obtained in the current step are used as candidate timing parameters. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read / write operation results of each step are recorded; Under the candidate timing parameters, perform two more data read and write operations. If successful, the adaptive adjustment of the interface timing parameters of the peripheral component is completed. If unsuccessful, return the steps corresponding to the success according to the data read and write operation results, and re-adjust the peripheral interface timing according to the preset adjustment steps.

2. The method for adaptively adjusting the timing parameters of a peripheral interface according to claim 1, characterized in that: In the preset adjustment step, before adjusting the operating frequency according to the preset timing parameter value, a data read and write operation is first performed on the peripheral component at the chip main frequency. If successful, the default interface timing parameters are used as candidate timing parameters. If unsuccessful, the interface timing parameters are adaptively adjusted according to the preset adjustment step, and the data read and write operation results are recorded.

3. The method for adaptively adjusting the timing parameters of a peripheral interface according to claim 2, characterized in that: The preset third timing parameter value is the timing parameter value after the last interface timing parameter adaptive adjustment is successful.

4. A timing parameter adjustment device, characterized in that: The device is arranged in a DSP chip, and includes an interface timing parameter adaptive adjustment module, a timing parameter register, a transmission detection register and a timing shadow register module; The interface timing parameter adaptive adjustment module is used to obtain an initialization signal of a peripheral component, and adaptively adjust the interface timing parameters of the peripheral component according to the initialization signal and the preset adjustment steps, wherein the preset adjustment steps sequentially include: loading a preset timing parameter value from the timing shadow register module to the timing parameter register to adjust the interface timing parameter, adjusting the interface timing parameter by adjusting the setup time parameter value in the timing parameter register, and adjusting the interface timing parameter by adjusting the hold time parameter value in the timing parameter register; When adjusting the timing parameters in the timing parameter register according to the preset adjustment steps, a data read / write operation is performed under the interface timing parameters obtained after the adjustment in the current step. If successful, the interface timing parameters obtained in the current step are used as candidate interface timing parameters. If unsuccessful, the next step is adjusted according to the preset adjustment steps, and the data read / write operation results of each step are recorded in the transmission detection register; Under the candidate operating frequency, perform two more data read and write operations. If successful, the interface timing parameters of the peripheral components are adaptively adjusted. If unsuccessful, return to the steps corresponding to the success according to the data read and write operation results recorded in the transmission detection register, and re-adjust the interface timing parameters according to the preset adjustment steps.

5. The timing parameter adjustment device according to claim 4, characterized in that: The timing shadow register module includes three timing shadow registers, which respectively store different preset timing parameter values.

6. The timing parameter adjustment device according to claim 5, characterized in that: The timing shadow register module and the timing parameter register belong to the same register group.

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