Display panel and manufacturing method thereof

Abstract

The present invention relates to a display panel and a method for manufacturing the same. The first active layer of the first thin film transistor in the non-display area of ​​the present invention includes a first channel portion arranged on the first groove wall, a second channel portion arranged on the second groove wall, a first conductive portion arranged on the bottom of the first groove and connected between the first channel portion and the second channel portion, a second conductive portion arranged on the first sub-source electrode and connected to the first channel portion, and a third conductive portion arranged on the second sub-source electrode and connected to the second channel portion, thereby enabling the first thin film transistor to have two vertical channel structures connected to each other on the left and right. By adopting a first thin film transistor with a dual vertical channel structure, the carrier mobility and current of the first thin film transistor are improved, the size of the first thin film transistor is avoided from being increased, and the size of the display panel is reduced, thereby facilitating the realization of a narrow frame design of the display panel.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a method for preparing the same. Background Art

[0002] The current active-driven self-luminous display devices such as Organic Light-Emitting Diode (OLED), Micro Light Emitting Diode (Micro LED), and sub-millimeter light-emitting diode (MiniLED) generally require two or more thin-film transistors on their driving substrates to control the display state of a single pixel, such as the common 2T1C circuit or 3T1C circuit. On the other hand, with the rapid development of 5G and the Internet of Things (IoT), the application scenarios of mobile terminals have become more diversified. Reduce costs or improve product performance through certain circuit integration. Among them, the most common are array substrate gate driver (Gate Driver on Array, GOA) technology and demultiplexing circuit (Demux) technology. Array substrate gate driver technology integrates the gate driver circuit on the array substrate of the display panel to achieve a row-by-row scanning drive mode, thereby eliminating the gate driver circuit part. Demultiplexing circuit technology refers to a circuit that uses data signal selection before the source and drain of the pixel in the display area from the IC to the display area. Usually, a data selection circuit is used to input the data signal, so as to connect the data signal to the IC channel.

[0003] GOA and Demux technologies, as mainstream display technologies, offer significant advantages in achieving low costs and reducing borders in high-quality display devices. As is well known, GOA and Demux circuits require high current drive. Using conventional device structures requires increasing the size of thin-film transistors (TFTs) to increase current flow, which in turn increases the size of the GOA circuits and the border, hindering the realization of narrow-border designs. Summary of the Invention

[0004] An object of the present invention is to provide a display panel and a method for manufacturing the same, which can solve the problem in the prior art that increasing the size of thin film transistors to increase current makes it difficult to achieve a narrow frame design.

[0005] In order to solve the above problems, the present invention provides a display panel, the display panel includes a display area and a non-display area located on at least one side of the display area, the display panel includes: a substrate and a first thin film transistor arranged on the substrate; wherein the first thin film transistor is located in the non-display area, the first thin film transistor includes: a first drain electrode, a first active layer, an interlayer insulating layer arranged on the first drain electrode, and a first source electrode arranged on the interlayer insulating layer; the first thin film transistor is further provided with a first groove penetrating the first source electrode and the interlayer insulating layer; wherein the first groove has a first groove wall, a second groove wall, and a groove connecting the first groove wall and the second groove wall. wherein the first source electrode comprises a first sub-source electrode and a second sub-source electrode, the first sub-source electrode is located on the interlayer insulating layer on one side of the first groove, and the second sub-source electrode is located on the interlayer insulating layer on the other side of the first groove; wherein the first active layer comprises: a first channel portion arranged on the first groove wall, a second channel portion arranged on the second groove wall, a first conductive portion arranged on the first groove bottom and connected between the first channel portion and the second channel portion, a second conductive portion arranged on the first sub-source electrode and connected to the first channel portion, and a third conductive portion arranged on the second sub-source electrode and connected to the second channel portion.

[0006] Furthermore, the first groove wall and the second groove wall are straight lines, and angles between the first groove wall and the second groove wall and the surface of the interlayer insulating layer close to the substrate are both in the range of 65°-85°.

[0007] Furthermore, a distance between a surface of the interlayer insulating layer away from the substrate and a surface of the first drain electrode away from the substrate is in a range of 0.5 um to 2 um.

[0008] Furthermore, the display panel also includes: a buffer layer, arranged on the first drain and the substrate, and located in the display area and the non-display area; a first gate insulating layer, arranged on the first active and first source electrodes, and located in the display area and the non-display area; wherein the first groove passes through the buffer layer on the first drain; the first thin film transistor also includes: a first gate arranged on the first gate insulating layer.

[0009] Furthermore, the first gate insulating layer is provided with a second groove at a position corresponding to the first groove, and the second groove has a third groove wall, a fourth groove wall, and a second groove bottom connected between the third groove wall and the fourth groove wall;

[0010] The first gate is arranged on the first gate insulation layer on both sides of the third groove wall, the fourth groove wall, the second groove bottom and the second groove.

[0011] Furthermore, the display panel also includes: a second thin film transistor, arranged on the substrate in the display area; wherein, the second thin film transistor includes: a second active layer, arranged on the surface of the buffer layer on the side away from the substrate; wherein, the material of the first active layer includes amorphous oxide, and the material of the second active layer includes crystalline oxide.

[0012] Furthermore, the second thin film transistor also includes: a second gate insulating layer, which is arranged on a side of the second active layer away from the substrate and corresponds to the second active layer; and a second gate, which is arranged on a side of the second gate insulating layer away from the substrate and corresponds to the second active layer; wherein the second gate is made of the same material as the first source.

[0013] Furthermore, the second thin film transistor also includes: a second source electrode, which is arranged in the same layer as the first gate electrode; and a second drain electrode, which is arranged in the same layer as the second source electrode; wherein the second source electrode, the second drain electrode and the first gate electrode are made of the same material.

[0014] Furthermore, the display panel further includes: a light shielding layer, which is provided in the same layer as the first drain electrode and corresponding to the second active layer; wherein the light shielding layer and the first drain electrode are made of the same material.

[0015] In order to solve the above problems, the present invention provides a method for manufacturing a display panel, wherein the display panel includes a display area and a non-display area located on at least one side of the display area, and the method includes the following steps: preparing a first drain electrode on a substrate in the non-display area; preparing a buffer layer on the first drain electrode, and forming a first through hole at a position of the buffer layer corresponding to the first drain electrode; preparing an interlayer insulating layer on the buffer layer, and forming a second through hole at a position of the interlayer insulating layer corresponding to the first through hole; preparing a first source electrode on the interlayer insulating layer, and providing a third through hole at a position of the first source electrode corresponding to the second through hole, and forming a first groove on a surface of the first through hole, the second through hole, the third through hole and the first drain electrode away from the substrate, and the first groove has a first groove wall, a second groove wall and The first groove bottom is connected between the first groove wall and the second groove wall, the first source includes a first sub-source and a second sub-source, the first sub-source is located on the interlayer insulating layer on one side of the first groove, and the second sub-source is located on the interlayer insulating layer on the other side of the first groove; a first channel portion is arranged on the first groove wall, a second channel portion is arranged on the second groove wall, a first conductive portion connected between the first channel portion and the second channel portion is arranged on the first groove bottom, a second conductive portion connected to the first channel portion is arranged on the first sub-source, and a third conductive portion connected to the second channel portion is arranged on the second sub-source, the first channel portion, the second channel portion, the first conductive portion, the second conductive portion and the third conductive portion form a first active layer.

[0016] The advantages of the present invention are as follows: the first active layer of the first thin film transistor in the non-display area of ​​the present invention includes a first channel portion disposed on the first groove wall, a second channel portion disposed on the second groove wall, a first conductive portion disposed on the first groove bottom and connected between the first and second channel portions, a second conductive portion disposed on the first sub-source electrode and connected to the first channel portion, and a third conductive portion disposed on the second sub-source electrode and connected to the second channel portion, thereby enabling the first thin film transistor to have two mutually connected vertical channel structures on the left and right. By adopting a first thin film transistor with a dual vertical channel structure, the carrier mobility and current of the first thin film transistor are improved, the size of the first thin film transistor is avoided from being increased, and the size of the display panel is reduced, thereby facilitating a narrow-frame design of the display panel.

[0017] In the present invention, the first drain is arranged on the same layer and made of the same material as the light shielding layer, the first source and the second gate are arranged on the same layer and made of the same material, and the first gate, the second source and the second drain are arranged on the same layer and made of the same material, which is beneficial to saving process masks, simplifying the process and reducing production costs. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0019] Figure 1 is a schematic structural diagram of a display panel of the present invention;

[0020] Figure 2 is a plan view schematically illustrating a first thin film transistor structure of the present invention;

[0021] Figure 3-Figure 12 Schematic diagram corresponding to each step of the method for manufacturing a display panel of the present invention.

[0022] Description of reference numerals:

[0023] 100. Display panel; 101. Display area;

[0024] 102. non-display area;

[0025] 1. substrate; 2. first thin film transistor;

[0026] 3. A second thin film transistor; 4. A buffer layer;

[0027] 5. First gate insulating layer; 6. Passivation layer;

[0028] 7. Pixel electrode; 8. Light shielding layer;

[0029] 21. a first drain electrode; 22. an interlayer insulating layer;

[0030] 23. First source electrode; 24. First active layer;

[0031] 25. a first gate; 26. a first groove;

[0032] 31. Second active layer; 32. Second gate;

[0033] 33. a second source electrode; 34. a second drain electrode;

[0034] 35. a second gate insulating layer;

[0035] 231, first sub-source; 232, second sub-source;

[0036] 233, third through hole;

[0037] 241, first channel portion; 242, second channel portion;

[0038] 243. First conductive portion; 244. Second conductive portion;

[0039] 245, third conductive portion;

[0040] 261, first groove wall; 262, second groove wall;

[0041] 263, first trough bottom;

[0042] 41, first through hole; 221, second through hole;

[0043] 51. Second groove; 52. First connecting hole;

[0044] 511, third groove wall; 512, fourth groove wall;

[0045] 513, second trough bottom;

[0046] 53. Second connecting hole; 54. Third connecting hole;

[0047] 61. The fourth connecting hole. DETAILED DESCRIPTION

[0048] The following describes in detail preferred embodiments of the present invention in conjunction with the accompanying drawings to fully introduce the technical content of the present invention to those skilled in the art, to illustrate that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied in many different forms of embodiments, and the scope of protection of the present invention is not limited to the embodiments described herein. The description of the embodiments below is not intended to limit the scope of the present invention.

[0049] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate the present invention, and are not used to limit the scope of protection of the present invention.

[0050] In the accompanying drawings, components with the same structure are represented by the same numerical labels, and components with similar structures or functions are represented by similar numerical labels. In addition, for ease of understanding and description, the size and thickness of each component shown in the accompanying drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

[0051] The present application provides a display device, which includes a display panel 100 .

[0052] Example 1

[0053] like Figure 1As shown, the display panel 100 includes a display area 101 and a non-display area 102 located at least on one side of the display area 101. The display panel 100 includes: a substrate 1, a first thin film transistor 2, and a second thin film transistor 3.

[0054] The substrate 1 is located in the display area 101 and the non-display area 102. The material of the substrate 1 includes glass, polyimide, polycarbonate, polyethylene terephthalate, polyethylene naphthalate, etc. In this application, the material of the substrate 1 is glass.

[0055] The first thin film transistor 2 is disposed on the substrate 1 and is located in the non-display area 102. The first thin film transistor 2 includes a first drain electrode 21, an interlayer insulating layer 22, a first source electrode 23, a first active layer 24, a first gate electrode 25, and a first groove 26. The first thin film transistor 2 can be used in both a gate driver on array (GOA) circuit and a demultiplexer (Demux) circuit.

[0056] The first drain electrode 21 is disposed on the substrate 1. The material of the first drain electrode 21 can be Mo, a combination structure of Mo / Al, a combination structure of Mo / Cu, a combination structure of MoTi / Cu, a combination structure of MoTi / Cu / MoTi, a combination structure of Ti / Al / Ti, a combination structure of Ti / Cu / Ti, a combination structure of Mo / Cu / IZO, a combination structure of IZO / Cu / IZO, or a combination structure of Mo / Cu / ITO.

[0057] The display panel 100 further includes a buffer layer 4. The buffer layer 4 is disposed on a side of the first drain electrode 21 away from the substrate 1, extends over the substrate 1, and is located in the display area 101 and the non-display area 102. The buffer layer 4 can be made of SiOx, SiNx, a combination of Al2O3 / SiNx / SiOx, or a combination of SiOx / SiNx / SiOx.

[0058] The interlayer insulating layer 22 is disposed on the side of the buffer layer 4 away from the substrate 1. The interlayer insulating layer 22 may be made of an organic polyimide material combined with an inorganic film material. The inorganic film material may be SiOx, SiNx, or a combination of SiNx / SiOx.

[0059] The first source electrode 23 is disposed on a side of the interlayer insulating layer 22 away from the substrate 1. The material of the first source electrode 23 can be Mo, a combination structure of Mo / Al, a combination structure of Mo / Cu, a combination structure of MoTi / Cu, a combination structure of MoTi / Cu / MoTi, a combination structure of Ti / Al / Ti, a combination structure of Ti / Cu / Ti, a combination structure of Mo / Cu / IZO, a combination structure of IZO / Cu / IZO, or a combination structure of Mo / Cu / ITO.

[0060] like Figure 1 and Figure 2 As shown, the first source electrode 23 includes a first sub-source electrode 231 and a second sub-source electrode 232. The first sub-source electrode 231 is located on the interlayer insulating layer 22 on one side of the first groove 26, and the second sub-source electrode 232 is located on the interlayer insulating layer 22 on the other side of the first groove 26. Specifically, the first sub-source electrode 231 is located on the interlayer insulating layer 22 on the side of the first groove 26 away from the display area 101, and the second sub-source electrode 232 is located on the interlayer insulating layer 22 on the side of the first groove 26 closer to the display area 101. It is worth noting that the first sub-source electrode 231 and the second sub-source electrode 232 are connected to each other at other locations. In this embodiment, the first source electrode 23 is annular.

[0061] The first groove 26 extends perpendicularly to the substrate 1 through the first source electrode 23, the interlayer insulating layer 22, and the buffer layer 4 on the first drain electrode 21. The first groove 26 has a first groove wall 261, a second groove wall 262, and a first groove bottom 263 connected between the first groove wall 261 and the second groove wall 262. Specifically, the first groove bottom 263 of the first groove 26 is flush with the surface of the first drain electrode 21 on the side away from the substrate 1.

[0062] The first groove wall 261 and the second groove wall 262 are straight lines. Angles A between the first groove wall 261 and the surface of the interlayer insulating layer 22 near the substrate 1 are both in the range of 65°-85°. Angles B between the second groove wall 262 and the surface of the interlayer insulating layer 22 near the substrate 1 are both in the range of 65°-85°. In this embodiment, A = B = 80°. In other embodiments, A may not equal B. A distance H between the surface of the interlayer insulating layer 22 away from the substrate 1 and the surface of the first drain electrode 21 away from the substrate 1 is in the range of 0.5 μm-2 μm. In this embodiment, H = 1.5 μm. This allows the interlayer insulating layer 22 and the buffer layer 4 to create a certain height difference between the first source electrode 23 and the first drain electrode 21, facilitating the subsequent formation of the first channel portion 241 and the second channel portion 242. This results in the first thin-film transistor 2 having two connected vertical channels on the left and right sides. By using a first thin-film transistor 2 with a dual vertical channel structure, the carrier mobility and current of the first thin-film transistor 2 are improved, while avoiding increasing the size of the first thin-film transistor 2. This helps reduce the size of the display panel 100, thereby facilitating a narrow-frame design for the display panel 100. The first active layer 24 is made of an amorphous metal oxide, such as IGZO, IGZO, IZO, AIZO, or ATZO. The first active layer 24 includes a first channel portion 241, a second channel portion 242, a first conductive portion 243, a second conductive portion 244, and a third conductive portion 245.

[0063] The first channel portion 241 is disposed on the first groove wall 261, the second channel portion 242 is disposed on the second groove wall 262, the first conductive portion 243 is disposed on the first groove bottom 263 and connected between the first channel portion 241 and the second channel portion 242, the second conductive portion 244 is disposed on the first sub-source electrode 231 and connected to the first channel portion 241, and the third conductive portion 245 is disposed on the second sub-source electrode 232 and connected to the second channel portion 242. The first conductive portion 243 is electrically connected to the first drain electrode 21, the second conductive portion 244 is electrically connected to the first source electrode 23, and the third conductive portion 245 is electrically connected to the first source electrode 23. As a result, the first thin-film transistor 2 has two vertical channel structures connected to each other on the left and right. By adopting a first thin-film transistor 2 with a dual vertical channel structure, the carrier mobility and current of the first thin-film transistor 2 are improved, while the size of the first thin-film transistor 2 is avoided from being increased, which facilitates reducing the size of the display panel 100 and thus facilitates a narrow-frame design of the display panel 100.

[0064] The display panel 100 further includes a first gate insulating layer 5. The first gate insulating layer 5 is disposed on a side of the first active layer 24 away from the substrate 1 and extends over the first source electrode 23, the second gate electrode 32, and the buffer layer 4. The first gate insulating layer 5 is located in the display area 101 and the non-display area 102. The material of the first gate insulating layer 5 can be SiOx, SiNx, a combination of Al2O3 / SiNx / SiOx, or a combination of SiOx / SiNx / SiOx. The first gate insulating layer 5 is primarily used to prevent short circuits between the first active layer 24 and the first gate electrode 25.

[0065] The first gate insulating layer 5 has a second groove 51 at a position corresponding to the first groove 26 . The second groove 51 has a third groove wall 511 , a fourth groove wall 512 and a second groove bottom 513 connected between the third groove wall 511 and the fourth groove wall 512 .

[0066] The first gate 25 is disposed on a side of the first gate insulating layer 5 away from the substrate 1. Specifically, the first gate 25 is disposed on the first gate insulating layer 5 on both sides of the third groove wall 511, the fourth groove wall 512, the second groove bottom 513, and the second groove 51. The material of the first gate 25 can be Mo, a combination structure of Mo / Al, a combination structure of Mo / Cu, a combination structure of MoTi / Cu, a combination structure of MoTi / Cu / MoTi, a combination structure of Ti / Al / Ti, a combination structure of Ti / Cu / Ti, a combination structure of Mo / Cu / IZO, a combination structure of IZO / Cu / IZO, or a combination structure of Mo / Cu / ITO.

[0067] The second thin film transistor 3 is disposed on the substrate 1 in the display area 101 and includes a second active layer 31 , a second gate electrode 32 , a second source electrode 33 , a second drain electrode 34 and a second gate insulating layer 35 .

[0068] The second active layer 31 is disposed on the surface of the buffer layer 4 away from the substrate 1. The material of the second active layer 31 includes crystalline oxide, such as IGO and IGTO.

[0069] The second gate insulating layer 35 is disposed on a side of the second active layer 31 away from the substrate 1 and corresponding to the second active layer 31. The second gate insulating layer 35 is primarily used to prevent a short circuit between the second active layer 31 and the second gate 32. The second gate insulating layer 35 can be made of SiOx, SiNx, or a combination of SiNx / SiOx.

[0070] The second gate 32 is disposed on a side of the second gate insulating layer 35 away from the substrate 1 and is disposed corresponding to the second active layer 31. The material of the second gate 32 can be Mo, a combination structure of Mo / Al, a combination structure of Mo / Cu, a combination structure of MoTi / Cu, a combination structure of MoTi / Cu / MoTi, a combination structure of Ti / Al / Ti, a combination structure of Ti / Cu / Ti, a combination structure of Mo / Cu / IZO, a combination structure of IZO / Cu / IZO, or a combination structure of Mo / Cu / ITO.

[0071] In this embodiment, the second gate 32 and the first source 23 are made of the same material. Therefore, the same photomask can be used to prepare the second gate 32 and the first source 23, which saves photomasks, simplifies the process, and reduces production costs. In other embodiments, the second gate 32 and the first source 23 can also be made of different materials.

[0072] The second source electrode 33 is disposed on a side of the first gate insulating layer 5 away from the substrate 1 and is electrically connected to the second active layer 31. The material of the second source electrode 33 can be Mo, a combination structure of Mo / Al, a combination structure of Mo / Cu, a combination structure of MoTi / Cu, a combination structure of MoTi / Cu / MoTi, a combination structure of Ti / Al / Ti, a combination structure of Ti / Cu / Ti, a combination structure of Mo / Cu / IZO, a combination structure of IZO / Cu / IZO, or a combination structure of Mo / Cu / ITO.

[0073] In this embodiment, the second source electrode 33 and the first gate electrode 25 are provided in the same layer and made of the same material. Therefore, the second source electrode 33 and the first gate electrode 25 can be manufactured using the same photomask, which saves photomasks, simplifies the process, and reduces production costs. In other embodiments, the second source electrode 33 and the first gate electrode 25 can also be made of different materials.

[0074] The second drain electrode 34 is provided in the same layer as the second source electrode 33. The material of the second drain electrode 34 can be Mo, a combination structure of Mo / Al, a combination structure of Mo / Cu, a combination structure of MoTi / Cu, a combination structure of MoTi / Cu / MoTi, a combination structure of Ti / Al / Ti, a combination structure of Ti / Cu / Ti, a combination structure of Mo / Cu / IZO, a combination structure of IZO / Cu / IZO, or a combination structure of Mo / Cu / ITO.

[0075] The second drain electrode 34 and the second source electrode 33 are electrically connected to the two ends of the second active layer 31. In this embodiment, the second drain electrode 34 and the second source electrode 33 are made of the same material. Therefore, the second drain electrode 34 and the second source electrode 33 can be manufactured using the same photomask, which saves photomasks, simplifies the process, and reduces production costs. In other embodiments, the second drain electrode 34 and the second source electrode 33 can also be made of different materials.

[0076] The display panel 100 further includes a passivation layer 6. The passivation layer 6 is disposed on a side of the first gate electrode 25, the second source electrode 33, and the second drain electrode 34 away from the substrate 1, and extends over the first gate insulating layer 5. The passivation layer 6 is located in the display area 101 and the non-display area 102. A fourth connection hole 61 is defined in the passivation layer 6 at a position corresponding to the second drain electrode 34. The passivation layer 6 can be made of SiOx, SiNx, a combination of Al2O3 / SiNx / SiOx, or a combination of SiOx / SiNx / SiOx.

[0077] The display panel 100 further includes a pixel electrode 7. The pixel electrode 7 is disposed on a side of the passivation layer 6 away from the substrate 1 and located in the display area 101. The pixel electrode 7 is electrically connected to the second drain electrode 34 through the fourth connection hole 61. The pixel electrode 7 can be made of ITO, IZO, a combination of ITO / Ag / ITO, an IZO / Ag / IZO, a Mo / Cu, or a MoTi / Cu / MoTi.

[0078] The display panel 100 further includes a light shielding layer 8. The light shielding layer 8 is provided on the same layer as the first drain electrode 21 and corresponds to the second active layer 31. The light shielding layer 8 is mainly used to prevent light from irradiating the second active layer 31 to avoid affecting the performance of the second active layer 31.

[0079] In this embodiment, the light shielding layer 8 and the first drain electrode 21 are made of the same material. Therefore, the light shielding layer 8 and the first drain electrode 21 can be prepared using the same photomask, which saves photomasks, simplifies the process, and reduces production costs. In other embodiments, the light shielding layer 8 and the first drain electrode 21 can also be made of different materials.

[0080] This embodiment also provides a method for manufacturing a display panel of this embodiment, wherein the display panel 100 includes a display area 101 and a non-display area 102 located on at least one side of the display area 101. The method for manufacturing the display panel includes the following steps:

[0081] S1 : forming a first drain electrode 21 on the substrate 1 in the non-display area 102 , and forming a light shielding layer 8 on the substrate 1 in the display area 101 .

[0082] like Figure 3As shown, a metal film is deposited on the substrate 1 and patterned, and at the same time, a first drain electrode 21 is formed in the non-display area 102 and a light shielding layer 8 is formed in the display area 101 .

[0083] S2 : preparing a buffer layer 4 on the first drain electrode 21 , the light shielding layer 8 and the substrate 1 , and forming a first through hole 41 at a position of the buffer layer 4 corresponding to the first drain electrode 21 .

[0084] like Figure 4 As shown, a buffer material layer is prepared on the first drain electrode 21 , the light shielding layer 8 and the substrate 1 , and then the buffer material layer is patterned to form a buffer layer 4 and a first through hole 41 penetrating the buffer layer on the first drain electrode 21 .

[0085] S3 : preparing an interlayer insulating layer 22 on the buffer layer 4 in the non-display area 102 , and providing second through holes 221 at positions of the interlayer insulating layer 22 corresponding to the first through holes 41 .

[0086] like Figure 5 As shown, an interlayer insulating material layer is prepared on the buffer layer 4 in the non-display area 102 , and then the interlayer insulating material layer is patterned to form an interlayer insulating layer and a second through hole 221 penetrating the interlayer insulating layer 22 at a position corresponding to the first through hole 41 .

[0087] S4 : preparing a second active layer 31 on the buffer layer 4 in the display area 101 at a position corresponding to the light shielding layer 8 .

[0088] like Figure 6 As shown, a second active material layer is formed on the buffer layer 4 , and then the second active material layer is patterned to form a second active layer 31 corresponding to the light shielding layer 8 .

[0089] S5 : forming a second gate insulating layer 35 on the second active layer 31 at a position corresponding to the light shielding layer 8 .

[0090] like Figure 7 As shown, a second gate insulating layer material layer is prepared on the second active layer 31 , and then the second gate insulating layer material layer is patterned to form a second gate insulating layer 35 corresponding to the light shielding layer 8 .

[0091] S6: Prepare a first source electrode 23 on the interlayer insulating layer 22, and set a third through hole 233 at a position in the interlayer insulating layer 22 corresponding to the second through hole 221, and prepare a second gate 32 on the second gate insulating layer 35. The first through hole 41, the second through hole 221, the third through hole 233, and the surface of the first drain electrode 21 on the side away from the substrate 1 form a first groove 26. The first groove 26 has a first groove wall 261, a second groove wall 262, and a first groove bottom 263 connected between the first groove wall 261 and the second groove wall 262. The first source electrode 23 includes a first sub-source electrode 231 and a second sub-source electrode 232. The first sub-source electrode 231 is located on the interlayer insulating layer 22 on one side of the first groove 26, and the second sub-source electrode 232 is located on the interlayer insulating layer 22 on the other side of the first groove 26. The second gate insulating layer 35 is patterned using the second gate 32 , and then the second active layer 31 not covered by the second gate 32 is conductively processed by self-alignment using the second gate 32 .

[0092] like Figure 8 As shown, a metal layer is prepared on the interlayer insulating layer 22, the second gate insulating layer 35 and the buffer layer 4, and then the metal layer is patterned to form a first source electrode 23 arranged on the interlayer insulating layer, a third through hole 233 passing through the first source electrode 23 at a position corresponding to the second through hole, and a second gate 32 arranged on the second gate insulating layer.

[0093] S7: A first channel portion 241 is formed on the first groove wall 261, a second channel portion 242 is formed on the second groove wall 262, a first conductive portion 243 connecting the first channel portion 241 and the second channel portion 242 is formed on the first groove bottom 263, a second conductive portion 244 connected to the first channel portion 241 is formed on the first sub-source electrode 231, and a third conductive portion 245 connected to the second channel portion 242 is formed on the second sub-source electrode 232. The first channel portion 241, the second channel portion 242, the first conductive portion 243, the second conductive portion 244, and the third conductive portion 245 together form the first active layer 24. The first conductive portion 243 is electrically connected to the first drain electrode 21, the second conductive portion 244 is electrically connected to the first source electrode 23, and the third conductive portion 245 is electrically connected to the first source electrode 23.

[0094] like Figure 9 As shown, a first active material layer is prepared on the first source electrode 23 , the second gate electrode 32 and the buffer layer 4 , and then the first active material layer is patterned to form a first active layer 24 .

[0095] S8: A first gate insulating layer 5 is formed on the first active layer 24, the second gate electrode 32, the first source electrode 23, the second active layer 31, and the buffer layer 4. The first gate insulating layer has a second groove 51 at a position corresponding to the first groove 26 in the non-display area 102. The first gate insulating layer 5 has a second groove 51 at a position corresponding to the first groove 26. The second groove 51 has a third groove wall 511, a fourth groove wall 512, and a second groove bottom 513 connected between the third groove wall 511 and the fourth groove wall 512. The first gate insulating layer has a first connection hole 52, a second connection hole 53, and a third connection hole 54 in the display area 101.

[0096] like Figure 10 As shown, a first gate insulating material layer is prepared on the first active layer 24 , the second gate 32 , the first source 23 , the second active layer 31 and the buffer layer 4 , and then the first gate insulating material layer is patterned to form a first gate insulating layer 5 .

[0097] S9: Prepare the first gate electrode 25 on the first gate insulating layer 5 in the non-display area 102, and prepare the second source electrode 33 and the second drain electrode 34 on the first gate insulating layer 5 in the display area 101. Figure 11 As shown, a metal film layer is formed on the first gate insulating layer 5, and then the metal film layer is patterned to form a first gate 25 disposed on the first gate insulating layer 5 in the non-display area 102, and two source electrodes 33 and a second drain electrode 34 disposed on the first gate insulating layer 5 in the display area 101. The first gate 25 is disposed on the first gate insulating layer 5 on both sides of the third groove wall 511, the fourth groove wall 512, the second groove bottom 513, and the second groove 51. The second source electrode 33 is filled in the first connection hole 52 and electrically connected to the light shielding layer 8. The second source electrode 33 is filled in the second connection hole 53 and electrically connected to one end of the second active layer 31. The second drain electrode 34 is filled in the third connection hole 54 and electrically connected to the other end of the second active layer 31.

[0098] S10 : preparing a passivation layer 6 on the first gate 25 , the second source electrode 33 , the second drain electrode 34 and the first gate insulating layer 5 , and providing a fourth connection hole 61 at a position of the passivation layer 6 corresponding to the second drain electrode 34 .

[0099] like Figure 12 As shown, a passivation material layer is prepared on the first gate 25, the second source 33, the second drain 34 and the first gate insulation layer 5, and the passivation material layer is patterned to form a passivation layer 6 and a fourth connection hole 61 penetrating the passivation layer 6 at a position corresponding to the second drain 34.

[0100] S11 : preparing a pixel electrode 7 on the passivation layer 6 . The pixel electrode 7 is filled in the fourth connection hole 61 and electrically connected to the second drain electrode 34 .

[0101] like Figure 1 As shown, a pixel electrode material layer is prepared on the passivation layer 6 , and then the pixel electrode material layer is patterned to form a pixel electrode 7 . The pixel electrode 7 is filled in the fourth connection hole 61 and electrically connected to the second drain electrode 34 .

[0102] The above is a detailed introduction to a display panel and a preparation method thereof provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core idea. At the same time, for technical personnel in this field, based on the ideas of the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A display panel, comprising a display area (101) and a non-display area (102) located on at least one side of the display area (101), characterized in that: The display panel comprises: a substrate (1) and a first thin film transistor (2) arranged on the substrate (1); The first thin film transistor (2) is located in the non-display area (102), and comprises: a first drain electrode (21), a first active layer (24), an interlayer insulating layer (22) disposed on the first drain electrode (21), and a first source electrode (23) disposed on the interlayer insulating layer (22); the first thin film transistor (2) is further provided with a first groove (26) penetrating the first source electrode (23) and the interlayer insulating layer (22); The first groove (26) has a first groove wall (261), a second groove wall (262), and a first groove bottom (263) connected between the first groove wall (261) and the second groove wall (262); The first source electrode (23) comprises a first sub-source electrode (231) and a second sub-source electrode (232), the first sub-source electrode (231) being located on the interlayer insulating layer (22) on one side of the first groove (26), and the second sub-source electrode (232) being located on the interlayer insulating layer (22) on the other side of the first groove (26); The first active layer (24) comprises: a first channel portion (241) arranged on the first groove wall (261), a second channel portion (242) arranged on the second groove wall (262), a first conductive portion (243) arranged on the first groove bottom (263) and connected between the first channel portion (241) and the second channel portion (242), a second conductive portion (244) arranged on the first sub-source electrode (231) and connected to the first channel portion (241), and a third conductive portion (245) arranged on the second sub-source electrode (232) and connected to the second channel portion (242).

2. The display panel according to claim 1, wherein: The first groove wall (261) and the second groove wall (262) are in the shape of straight lines, and the angles between the first groove wall (261) and the second groove wall (262) and the surface of the interlayer insulating layer (22) close to the substrate (1) are both in the range of 65°-85°.

3. The display panel according to claim 1, wherein: The distance between the surface of the interlayer insulating layer (22) away from the substrate (1) and the surface of the first drain electrode (21) away from the substrate (1) is in the range of 0.5um-2um.

4. The display panel according to claim 1, wherein: The display panel further includes: a buffer layer (4) disposed on the first drain electrode (21) and the substrate (1), and located in the display area (101) and the non-display area (102); A first gate insulating layer (5) is provided on the first active layer (24) and the first source electrode (23), and is located in the display area (101) and the non-display area (102); Wherein, the first groove (26) penetrates the buffer layer (4) on the first drain electrode (21); The first thin film transistor (2) further comprises a first gate (25) arranged on the first gate insulating layer (5).

5. The display panel according to claim 4, wherein: The first gate insulating layer (5) is provided with a second groove (51) at a position corresponding to the first groove (26); the second groove (51) has a third groove wall (511), a fourth groove wall (512), and a second groove bottom (513) connected between the third groove wall (511) and the fourth groove wall (512); The first gate (25) is arranged on the first gate insulating layer (5) on both sides of the third groove wall (511), the fourth groove wall (512), the second groove bottom (513) and the second groove (51).

6. The display panel according to claim 4, wherein: The display panel further includes: A second thin film transistor (3) is arranged on the substrate (1) in the display area (101); Wherein, the second thin film transistor (3) comprises: a second active layer (31) disposed on a surface of the buffer layer (4) on a side away from the substrate (1); The material of the first active layer (24) includes amorphous oxide, and the material of the second active layer (31) includes crystalline oxide.

7. The display panel according to claim 6, wherein: The second thin film transistor (3) further comprises: a second gate insulating layer (35), arranged on a side of the second active layer (31) away from the substrate (1), and arranged corresponding to the second active layer (31); and A second gate (32) is arranged on a side of the second gate insulating layer (35) away from the substrate (1), and is arranged corresponding to the second active layer (31); The second gate (32) and the first source (23) are made of the same material.

8. The display panel according to claim 7, wherein: The second thin film transistor (3) further comprises: A second source electrode (33) is provided in the same layer as the first gate electrode (25); A second drain electrode (34) is provided in the same layer as the second source electrode (33); The second source (33), the second drain (34) and the first gate (25) are made of the same material.

9. The display panel according to claim 6, wherein: The display panel further includes: a light shielding layer (8), arranged in the same layer as the first drain electrode (21), and arranged corresponding to the second active layer (31); The light shielding layer (8) and the first drain electrode (21) are made of the same material.

10. A method for manufacturing a display panel, the display panel comprising a display area (101) and a non-display area (102) located on at least one side of the display area (101), characterized in that: The following steps are involved: preparing a first drain electrode (21) on the substrate (1) in the non-display area (102); preparing a buffer layer (4) on the first drain electrode (21), and forming a first through hole (41) at a position of the buffer layer (4) corresponding to the first drain electrode (21); preparing an interlayer insulating layer (22) on the buffer layer (4), and forming a second through hole (221) at a position of the interlayer insulating layer (22) corresponding to the first through hole (41); A first source electrode (23) is prepared on the interlayer insulating layer (22), and a third through hole (233) is provided at a position of the first source electrode (23) corresponding to the second through hole (221); a first groove (26) is formed on the surface of the first through hole (41), the second through hole (221), the third through hole (233), and the first drain electrode (21) away from the substrate (1); the first groove (26) has a first groove wall (261), a second groove wall (262), and a first groove bottom (263) connected between the first groove wall (261) and the second groove wall (262); the first source electrode (23) includes a first sub-source electrode (231) and a second sub-source electrode (232); the first sub-source electrode (231) is located on the interlayer insulating layer (22) on one side of the first groove (26); and the second sub-source electrode (232) is located on the interlayer insulating layer (22) on the other side of the first groove (26); A first channel portion (241) is provided on the first groove wall (261), a second channel portion (242) is provided on the second groove wall (262), a first conductive portion (243) connected between the first channel portion (241) and the second channel portion (242) is provided on the first groove bottom (263), a second conductive portion (244) connected to the first channel portion (241) is provided on the first sub-source electrode (231), and a third conductive portion (245) connected to the second channel portion (242) is provided on the second sub-source electrode (232), the first channel portion (241), the second channel portion (242), the first conductive portion (243), the second conductive portion (244) and the third conductive portion (245) forming a first active layer (24).

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