A cross-chip routing method for multi-chip interconnection

Abstract

The present invention belongs to the field of chip communication technology, and specifically discloses a method for cross-chip routing when multiple chips are interconnected. The method proposes to use only one set of mechanisms to implement routing between nodes, which not only effectively reduces the table lookup overhead caused by on-chip and inter-chip hierarchical routing, but also solves the difficulty of upper-layer software in grasping the node resource allocation situation when chips are interconnected. In addition, it also enables the upper-layer software to directly monitor the communication bandwidth between the interconnected multi-chip nodes and the real-time computing power within the nodes.

Description

Technical Field

[0001] The present invention belongs to the field of chip communication technology, and in particular relates to a method for cross-chip routing when multiple chips are interconnected. Background Art

[0002] Currently, when multiple chips communicate across chips, address remapping is mostly used to achieve addressing between nodes. That is, in a network composed of multiple chips, the nodes in all chips are addressed by chip addresses and on-chip node addresses, and when the chips are actually running, the data sent by the source node in the source chip is routed to the destination node in the destination chip.

[0003] This method usually requires defining the chip network address and chip node address separately, so that the source node and the destination node need to communicate through two-layer routing mechanisms, intra-chip and inter-chip. This not only makes the location where the transmitted data is sent or received between chip nodes invisible from the perspective of the chip network, making it difficult to control the resource allocation of nodes within the chip from a global perspective, but also leads to the need to route the chip network address and chip node address at the same time when communicating across chips, resulting in large routing overhead. Summary of the invention

[0004] In order to solve at least one of the problems mentioned in the above background technology, the present invention proposes a method for cross-chip routing when multiple chips are interconnected.

[0005] A method for cross-chip routing when multiple chips are interconnected, the process is as follows:

[0006] Step S1, deploying the chip in an interconnection network, where the chip interconnection in the interconnection network needs to satisfy a topology structure;

[0007] Step S2, marking the physical IDs of all communication nodes in all chips in the interconnection network, the specific rules are as follows:

[0008] First, select a node as the reference physical node. If it is a two-dimensional topology, mark it as the physical coordinate (0, 0); if it is a three-dimensional topology, mark it as the physical coordinate (0, 0, 0);

[0009] Then, mark the coordinates of other nodes relative to this reference node in the topology. If it is a two-dimensional topology, mark the xy coordinates; if it is a three-dimensional topology, mark the xyz coordinates.

[0010] Step S3, after the physical ID is marked, a part of the nodes in a part of the chips in the interconnected network are configured in a computing task according to actual needs;

[0011] Step S4, marking the logical IDs of the communication nodes in different chips configured in the same computing task, the specific rules are as follows:

[0012] First, select a node as the reference logical node. If it is a two-dimensional topology, mark it as the logical coordinate (0, 0); if it is a three-dimensional topology, mark it as the logical coordinate (0, 0, 0);

[0013] Then, mark the coordinates of other nodes relative to this reference node in the topology. If it is a two-dimensional topology, mark the xy coordinates; if it is a three-dimensional topology, mark the xyz coordinates.

[0014] Step S5, marking the communication node that needs to send data as the source node, and the communication node that needs to receive data as the destination node, and deriving the ID mapping relationship when the source node sends a request to the destination node in the computing task, the derivation process includes:

[0015] Step S501, the request ID is described by the global physical ID of the destination node, the physical offset of the chip where the destination node is located, and the physical offset of the chip where the source node is located. The calculation method is:

[0016] TargetId=DstRoutId+DstChipPhyOffset-SrcChipPhyOffset

[0017] Where TargetId is the request ID, DstRouteId is the local physical ID of the destination node in its chip, DstChipPhyOffset is the physical offset of the chip where the destination node is located, and SrcChipPhyOffset is the physical offset of the chip where the source node is located;

[0018] Step S502, calculate the local physical ID of the destination node in its chip, the calculation method is:

[0019] DstRouteId=DstPhyId-DstChipPhyOffset

[0020] Wherein, DstRouteId is the local physical ID of the destination node in its chip, DstPhyId is the global physical ID of the destination node, and DstChipPhyOffset is the physical offset of the chip where the destination node is located;

[0021] Step S503: Substitute the formula of step S502 into step S501 to obtain a calculation formula for the request ID. The calculation method is:

[0022] TargetId=DstPhyId-SrcChipPhyOffset

[0023] Where TargetId is the request ID, DstPhyId is the global physical ID of the destination node, and SrcChipPhyOffset is the physical offset of the chip where the source node is located;

[0024] Step S504: Establish a mapping relationship between the destination node global physical ID, the destination node logical ID, the source node global physical ID and the source node logical ID. The specific mapping relationship is:

[0025] DstPhyId=DstLogicId+(SrcPhyId-SrcLogicId)

[0026] Wherein, DstPhyId is the destination node global physical ID, DstLogicId is the destination node logical ID, SrcPhyId is the source node global physical ID, and SrcLogicId is the source node logical ID;

[0027] Step S505, substitute DstPhyId in the mapping relationship of step S403 into the formula in step S402, and calculate the general formula of the request ID based on the logical IDs of the source and destination nodes, the physical offset of the source chip, and the physical ID of the source node. The specific calculation method is:

[0028] TargetId=DstLogicId-SrcPhyId+SrcPhyId-SrcChipPhyOffset

[0029] Among them, TargetId is the request ID, DstLogicId is the destination node logical ID, SrcLogicId is the source node logical ID, SrcPhyId is the source node global physical ID, and SrcChipPhyOffset is the physical offset of the chip where the source node is located.

[0030] Traditional methods usually require distinguishing between the main network and the subnet. However, if the main network address and the subnet address are distinguished and their respective routes are implemented separately, each module responsible for inter-chip routing needs to be able to carry the addresses of all devices in the network, which will not only cause huge hardware overhead, but also because the path between nodes is uncertain, it makes it difficult for the upper-level software to monitor the communication bandwidth between nodes and the real-time computing power within the nodes.

[0031] The present invention proposes to use only one set of mechanisms to realize routing between nodes. When the network is deployed, the nodes within and between chips are equal in routing and computing, which effectively reduces the table lookup overhead caused by hierarchical routing on and between chips. Moreover, since the node is assigned a logical ID, the TargetId addressed globally can be directly determined according to the logical ID and the physical address of the source node and the offset of the chip, so that the upper-level software can still grasp the resource allocation of the node after networking. In addition, because the logical domain of the node has been determined and the paths between the nodes are more coupled, the upper-level software can directly monitor the communication bandwidth between the interconnected multi-chip nodes and the real-time computing power within the node.

[0032] Step S6, the source node obtains the requested ID according to the derived ID mapping relationship, and decides whether to forward the request to the next level chip according to the coordinates of the requested ID, which specifically includes the following steps:

[0033] Step S601, counting the number of nodes on the X-axis, Y-axis and Z-axis of the chip where the source node is located, recorded as N1, N2 and N3 respectively;

[0034] Step S602, parse the xyz coordinates of the request ID, and set the value greater than the current coordinate value as the positive direction, and the value less than the current coordinate value as the negative direction;

[0035] Step S603, compare the parsed xyz coordinates with N1, N2, and N3 to determine whether the request falls within the chip where the source node is located, and decide whether to forward the request based on the determination result;

[0036] The specific judgment and forwarding rules are as follows:

[0037]

[0038]

[0039]

[0040] If the xyz coordinate of the request ID is less than 0, the request is forwarded in the negative direction of the coordinate value. Accordingly, the xyz coordinate value is added to the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, and the original request ID is replaced with the new request ID.

[0041] If the xyz coordinates of the request ID are greater than or equal to 0 and less than the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, the request is not forwarded;

[0042] If the xyz coordinate of the request ID is greater than the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, the request is forwarded in the positive direction of the coordinate value. Accordingly, the xyz coordinate value is added to the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, and the original request ID is replaced with the new request ID.

[0043] Step S604: if the request falls within the chip where the source node is located, it is routed to the final destination node through an intra-chip routing method; otherwise, the request is forwarded to the next-level chip.

[0044] Step S7, after the next-level chip receives the request, it determines whether to forward the request according to the steps in step S6. If not, the request ID falls into this chip and is routed to the final destination node through the on-chip routing method. Otherwise, the request is forwarded to the next-level chip.

[0045] The present invention proposes a method for cross-chip routing when multiple chips are interconnected, which has the following beneficial effects compared with the existing technology:

[0046] This method proposes to use only one set of mechanisms to implement routing between nodes, which not only effectively reduces the table lookup overhead caused by on-chip and inter-chip hierarchical routing, but also solves the difficulty that the upper-level software still has difficulty in grasping the node resource allocation situation during chip interconnection. In addition, it also enables the upper-level software to directly monitor the communication bandwidth between multi-chip nodes after interconnection and the real-time computing power within the nodes. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] Figure 1 It is a schematic diagram of the process of the present invention;

[0048] Figure 2 This is a logical judgment diagram of whether to forward a request in the present invention. DETAILED DESCRIPTION

[0049] In order to make the purpose and features of the present invention more obvious and easy to understand, the present technical solution is described in detail below through embodiments and in conjunction with the accompanying drawings.

[0050] according to Figure 1 The process shown is a method for cross-chip routing when multiple chips are interconnected.

[0051] The specific implementation process is as follows:

[0052] Step S1, deploying chips in an interconnection network, where chip interconnections in the interconnection network need to satisfy a topology structure.

[0053] Optionally, the topological structure includes topologies of two-dimensional mesh and torus and three-dimensional mesh and torus.

[0054] Step S2, marking the physical IDs of all communication nodes in all chips in the interconnection network, the specific rules are as follows:

[0055] First, a node is selected as a reference physical node. If it is a two-dimensional topology, it is marked as the physical coordinate (0, 0). If it is a three-dimensional topology, it is marked as the physical coordinate (0, 0, 0).

[0056] Then, mark the coordinates of other nodes relative to this reference node in the topology. If it is a two-dimensional topology, mark the xy coordinates; if it is a three-dimensional topology, mark the xyz coordinates.

[0057] Step S3, after the physical ID is marked, a part of the nodes in a part of the chips in the interconnected network are configured in a computing task according to actual needs.

[0058] Step S4, marking the logical IDs of the communication nodes in different chips configured in the same computing task, the specific rules are as follows:

[0059] First, a node is selected as a reference logical node. If it is a two-dimensional topology, it is marked as the logical coordinate (0, 0). If it is a three-dimensional topology, it is marked as the logical coordinate (0, 0, 0).

[0060] Then, mark the coordinates of other nodes relative to this reference node in the topology. If it is a two-dimensional topology, mark the xy coordinates; if it is a three-dimensional topology, mark the xyz coordinates.

[0061] In the actual implementation process, since there may be a plurality of chips each having a portion of nodes configured to be used in the same computing task, the present invention marks the logical IDs of the communication nodes in different chips in the same computing task.

[0062] Step S5: mark the communication node that needs to send data as the source node, and the communication node that needs to receive data as the destination node, and derive the ID mapping relationship when the source node sends a request to the destination node in the computing task.

[0063] The derivation process includes:

[0064] Step S501, the request ID is described by the global physical ID of the destination node, the physical offset of the chip where the destination node is located, and the physical offset of the chip where the source node is located. The calculation method is:

[0065] TargetId=DstRoutId+DstChipPhyOffset-SrcChipPhyOffset

[0066] Where TargetId is the request ID, DstRouteId is the local physical ID of the destination node in its chip, DstChipPhyOffset is the physical offset of the chip where the destination node is located, and SrcChipPhyOffset is the physical offset of the chip where the source node is located;

[0067] Step S502, calculate the local physical ID of the destination node in its chip, the calculation method is:

[0068] DstRouteId=DstPhyId-DstChipPhyOffset

[0069] Wherein, DstRouteId is the local physical ID of the destination node in its chip, DstPhyId is the global physical ID of the destination node, and DstChipPhyOffset is the physical offset of the chip where the destination node is located;

[0070] Step S503: Substitute the formula of step S502 into step S501 to obtain a calculation formula for the request ID. The calculation method is:

[0071] TargetId=DstPhyId-SrcChipPhyOffset

[0072] Where TargetId is the request ID, DstPhyId is the global physical ID of the destination node, and SrcChipPhyOffset is the physical offset of the chip where the source node is located;

[0073] Step S504: Establish a mapping relationship between the destination node global physical ID, the destination node logical ID, the source node global physical ID and the source node logical ID. The specific mapping relationship is:

[0074] DstPhyId=DstLogicId+(SrcPhyId-SrcLogicId)

[0075] Wherein, DstPhyId is the destination node global physical ID, DstLogicId is the destination node logical ID, SrcPhyId is the source node global physical ID, and SrcLogicId is the source node logical ID;

[0076] Step S505, substitute DstPhyId in the mapping relationship of step S403 into the formula in step S402, and calculate the general formula of the request ID based on the logical IDs of the source and destination nodes, the physical offset of the source chip, and the physical ID of the source node. The specific calculation method is:

[0077] TargetId=DstKogicId-SrcLogicId+SrcPhyId-SrcChipPhyOffset

[0078] Among them, TargetId is the request ID, DstLogicId is the destination node logical ID, SrcLogicId is the source node logical ID, SrcPhyId is the source node global physical ID, and SrcChipPhyOffset is the physical offset of the chip where the source node is located.

[0079] After the above steps, the mapping relationship of the request ID has been derived. The above steps are to achieve that the source node can send a request to the destination node without knowing the physical ID information of the destination node and the destination chip.

[0080] Step S6, the source node obtains the requested ID according to the derived ID mapping relationship, and decides whether to forward the request to the next level chip according to the coordinates of the requested ID, which specifically includes the following steps:

[0081] Step S601 , counting the number of nodes on the X-axis, Y-axis and Z-axis of the chip where the source node is located, and denoted as N1 , N2 and N3 respectively.

[0082] Step S602, parse the xyz coordinates of the request ID, and set the value greater than the current coordinate value as the positive direction, and the value less than the current coordinate value as the negative direction.

[0083] Step S603 , compare the parsed xyz coordinates with N1 , N2 , and N3 to determine whether the request falls within the chip where the source node is located, and decide whether to forward the request based on the determination result.

[0084] The specific judgment and forwarding rules are as follows:

[0085]

[0086]

[0087]

[0088] If the xyz coordinate of the request ID is less than 0, the request is forwarded in the negative direction of the coordinate value. Accordingly, the xyz coordinate value is added to the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, and the original request ID is replaced with the new request ID.

[0089] If the xyz coordinates of the request ID are greater than or equal to 0 and less than the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, the request is not forwarded.

[0090] If the xyz coordinate of the request ID is greater than the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, the request will be forwarded in the positive direction of the coordinate value. Accordingly, the xyz coordinate value is added to the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, and the original request ID is replaced with the new request ID.

[0091] Step S604: if the request falls within the chip where the source node is located, it is routed to the final destination node through an intra-chip routing method; otherwise, the request is forwarded to the next-level chip.

[0092] Step S7, after the next-level chip receives the request, it determines whether to forward the request according to the steps in step S6. If not, the request ID falls into this chip and is routed to the final destination node through the on-chip routing method. Otherwise, the request is forwarded to the next-level chip.

[0093] So far, according to the method disclosed in the present invention, the working process of the present invention has been implemented once.

[0094] It should be noted that the serial numbers of the above embodiments of the present invention are only for description and do not represent the advantages and disadvantages of the embodiments. And the terms "including", "comprising" or any other variants thereof in this article are intended to cover non-exclusive inclusion, so that a process, device, article or method including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, device, article or method. In the absence of further restrictions, an element defined by the sentence "including a ..." does not exclude the presence of other identical elements in the process, device, article or method including the element.

[0095] Through the description of the above implementation methods, those skilled in the art can clearly understand that the above-mentioned embodiment methods can be implemented by means of software plus a necessary general hardware platform, and of course by hardware, but in many cases the former is a better implementation method. Based on such an understanding, the technical solution of the present invention is essentially or the part that contributes to the prior art can be embodied in the form of a software product, which is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) as described above, and includes a number of instructions for a terminal device (which can be a mobile phone, a computer, a server, or a network device, etc.) to execute the methods described in each embodiment of the present invention.

[0096] The above are only preferred embodiments of the present invention, and are not intended to limit the patent scope of the present invention. Any equivalent structure or equivalent process transformation made using the contents of the present invention specification and drawings, or directly or indirectly applied in other related technical fields, are also included in the patent protection scope of the present invention.

Claims

1. A method for cross-chip routing when multiple chips are interconnected, characterized in that: Includes steps: Step S1, deploying the chip in an interconnection network, where the chip interconnection in the interconnection network needs to satisfy a topology structure; Step S2, marking the physical IDs of all communication nodes in all chips in the interconnection network; Step S3, after the physical ID is marked, a part of the nodes in a part of the chips in the interconnected network are configured in a computing task according to actual needs; Step S4, marking logical IDs of communication nodes in different chips configured in the same computing task; Step S5, marking the communication node that needs to send data as the source node, and the communication node that needs to receive data as the destination node, and deriving the ID mapping relationship when the source node sends a request to the destination node in the computing task; The derivation of the ID mapping relationship when the source node sends a request to the destination node in the computing task in step S5 specifically includes the following steps: Step S501, the request ID is described by the global physical ID of the destination node, the physical offset of the chip where the destination node is located, and the physical offset of the chip where the source node is located. The calculation method is: TargetId = DstRoutId + DstChipPhyOffset - SrcChipPhyOffset, where TargetId is the request ID, DstRouteId is the local physical ID of the destination node in its chip, DstChipPhyOffset is the physical offset of the chip where the destination node is located, and SrcChipPhyOffset is the physical offset of the chip where the source node is located; Step S502, calculate the local physical ID of the destination node in its chip, the calculation method is: DstRouteId=DstPhyId-DstChipPhyOffset Wherein, DstRouteId is the local physical ID of the destination node in its chip, DstPhyId is the global physical ID of the destination node, and DstChipPhyOffset is the physical offset of the chip where the destination node is located; Step S503: Substitute the formula of step S502 into step S501 to obtain a calculation formula for the request ID. The calculation method is: TargetId=DstPhyId-SrcChipPhyOffset Where TargetId is the request ID, DstPhyId is the global physical ID of the destination node, and SrcChipPhyOffset is the physical offset of the chip where the source node is located; Step S504: Establish a mapping relationship between the destination node global physical ID, the destination node logical ID, the source node global physical ID and the source node logical ID. The specific mapping relationship is: DstPhyId=DstLogicId+(SrcPhyId-SrcLogicId) Wherein, DstPhyId is the destination node global physical ID, DstLogicId is the destination node logical ID, SrcPhyId is the source node global physical ID, and SrcLogicId is the source node logical ID; Step S505, substitute DstPhyId in the mapping relationship of step S504 into the formula in step S503, and a general formula for the request ID based on the logical IDs of the source and destination nodes, the physical offset of the source chip, and the physical ID of the source node can be calculated. The specific calculation method is: TargetId=DstLogicId-SrcLogicId+SrcPhyId-SrcChipPhyOffset Wherein, TargetId is the request ID, DstLogicId is the destination node logical ID, SrcLogicId is the source node logical ID, SrcPhyId is the source node global physical ID, and SrcChipPhyOffset is the physical offset of the chip where the source node is located; Step S6, the source node obtains the requested ID according to the derived ID mapping relationship, and decides whether to forward the request to the next level chip according to the coordinates of the requested ID; Step S7, after the next-level chip receives the request, it determines whether to forward the request according to the steps in step S6. If not, the request ID falls into this chip and is routed to the final destination node through the on-chip routing method; otherwise, the request is forwarded to the next-level chip.

2. The method for cross-chip routing when multiple chips are interconnected according to claim 1, characterized in that: Step S2 of marking the physical IDs of all communication nodes in all chips in the interconnected network includes the following specific rules: Step A1, select a node as a reference physical node, if it is a two-dimensional topology, mark it as the physical coordinate (0, 0), if it is a three-dimensional topology, mark it as the physical coordinate (0, 0, 0); Step A1, mark the coordinates of other nodes relative to the reference node in the topology, if it is a two-dimensional topology, mark the xy coordinates, if it is a three-dimensional topology, mark the xyz coordinates.

3. The method for cross-chip routing when multiple chips are interconnected according to claim 1, characterized in that: Step S4 marks the logical IDs of all communication nodes in all chips in the interconnected network. The specific rules include the following steps: Step B1, select a node as a reference logical node, if it is a two-dimensional topology, mark it as a logical coordinate (0, 0), if it is a three-dimensional topology, mark it as a logical coordinate (0, 0, 0); Step B2, marking the coordinates of other nodes relative to the reference node in the topology, if it is a two-dimensional topology, mark the xy coordinates, if it is a three-dimensional topology, mark the xyz coordinates.

4. The method for cross-chip routing when multiple chips are interconnected according to claim 1, characterized in that: Step S6 comprises the steps of: Step S601, counting the number of nodes on the X-axis, Y-axis and Z-axis of the chip where the source node is located, recorded as N1, N2 and N3 respectively; Step S602, parse the xyz coordinates of the request ID, and set the value greater than the current coordinate value as the positive direction, and the value less than the current coordinate value as the negative direction; Step S603, compare the parsed xyz coordinates with N1, N2, and N3 to determine whether the request falls within the chip where the source node is located, and decide whether to forward the request based on the determination result; The specific judgment and forwarding rules are as follows: If the xyz coordinate of the request ID is less than 0, the request is forwarded in the negative direction of the coordinate value. Accordingly, the xyz coordinate value is added to the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, and the original request ID is replaced with the new request ID. If the xyz coordinates of the request ID are greater than or equal to 0 and less than the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, the request is not forwarded; If the xyz coordinate of the request ID is greater than the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, the request is forwarded in the positive direction of the coordinate value. Accordingly, the xyz coordinate value is added to the number of nodes on the X-axis, Y-axis, and Z-axis of the chip, and the original request ID is replaced with the new request ID. Step S604: if the request falls within the chip where the source node is located, it is routed to the final destination node through an on-chip routing method; otherwise, the request is forwarded to the next-level chip.

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