Detection method for representing interface roughness of interconnection structure by using low-frequency noise

Abstract

The invention discloses a detection method for representing interface roughness of an interconnection structure by using low-frequency noise. According to the method, constant low current is applied to a to-be-tested structure, output current of the to-be-tested structure is measured, and then random current fluctuation generated by interaction of electrons and interconnection structure interfaces, defects and phonons is obtained; fourier transform is carried out on random current fluctuation to obtain frequency domain parameters of the current; calculating the power spectrum density of random current fluctuation according to the frequency domain parameter of the current; wherein the PSD is proportional to the f, and then fitting is carried out to obtain a slope k; and evaluating the interface roughness of the interconnection structure by using the slope k. According to the method, the experiment can be rapidly completed under the condition that the sample is not damaged, and the reusability of the sample is improved. In addition, the low-frequency noise characterization method does not need direct contact or imaging, is suitable for testing packaged chips, and can measure the overall roughness of long interconnection line segments at the same time.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor manufacturing, and relates to a detection method for characterizing the interface roughness of an interconnect structure by using low-frequency noise. Background Art

[0002] In the process of continuous miniaturization of semiconductor devices, the interface roughness between conductors and semiconductor structures has become a key factor affecting device performance and reliability. As the process nodes continue to advance to the nanoscale (such as below 7 nm), the widths of interconnect metal lines and the sizes of semiconductor channels are continuously reduced, and the atomic-scale irregularities in the interface morphologies such as the sidewalls and bottoms of the structures have an increasingly significant negative impact on electrical performance.

[0003] Chip interconnect structures are usually composed of metal materials (such as copper, aluminum, etc.) or semiconductor materials (such as silicon). There are often certain roughnesses in areas such as the sidewalls and bottoms of these materials. The generation of this roughness is affected by various factors, including manufacturing process parameters, lithography and etching technologies, manufacturing equipment, material quality, and cleaning treatment processes. These factors can cause random roughness at the edges of gate patterns or printed patterns. If the roughness of the structure sidewalls or bottoms is large, it may lead to uneven local current density or electric field distribution, thereby exacerbating the electromigration phenomenon. Interface roughness also affects electrical conductivity, signal transmission quality, and may even cause problems such as current leakage. For example, the sidewall roughness of a metal interconnect structure increases the scattering of electrons during transmission, thereby increasing the resistance and reducing the signal transmission rate. For smaller process nodes, as the current density increases, the impact of roughness on current transmission becomes more obvious.

[0004] Currently, common methods for detecting the interface roughness of chip interconnect structures or other sidewalls and bottoms of conductors and semiconductor structures include scanning electron microscopy (SEM), atomic force microscopy (AFM), profilometer, and transmission electron microscopy (TEM), etc. However, these detection methods usually have high requirements for the sample surface, and most methods require cutting, polishing, or thinning of the sample, which may cause certain damage to the material, resulting in the non-reusability of the device, thus affecting the accuracy of the measurement results. Summary of the Invention

[0005] The purpose of the present invention is to provide a detection method for characterizing the interface roughness of an interconnect structure by using low-frequency noise in view of the deficiencies of the prior art, and to develop a non-destructive, global, and highly sensitive detection method by utilizing the strong correlation between the spectral characteristics of low-frequency noise and the interface roughness.

[0006] In a first aspect, the present invention provides a detection method for characterizing the interface roughness of an interconnect structure by using low-frequency noise, and the method includes the following steps:

[0007] Step 1: Apply a constant low current \(i_c\) to the structure to be measured, and measure the output current \(i(t)\) of the structure to be measured at time \(t\). Since \(i(t)=i\) c +\(\Delta i(t)\), calculate the random current fluctuation \(\Delta i(t)\) generated by the interaction of electrons with the interface of the interconnect structure, defects, and phonons;

[0008] Step 2: Obtain the frequency-domain parameters \(I(f)\) of the current by performing a Fourier transform on the random current fluctuation \(\Delta i(t)\);

[0009] Step 3: Calculate the power spectral density PSD of the random current fluctuation according to the frequency-domain parameters \(I(f)\) of the current; Since the power spectral density PSD is proportional to the frequency, the slope \(k\) is obtained by least-square fitting; Use the slope \(k\) to evaluate the interface roughness of the interconnect structure.

[0010] Further, in Step 2, the calculation formula for the frequency-domain parameters \(I(f)\) of the current is:

[0011]

[0012] where \(f\) represents frequency and \(j\) represents the imaginary unit.

[0013] Further, in Step 3, the calculation formula for the power spectral density PSD of the random current fluctuation is:

[0014]

[0015] where \(p\) is the period of the periodic signal, and \(I\) P (f) is the segment of \(I(f)\) over the period \([-p / 2, p / 2]\).

[0016] Further, in Step 1, the temperature of the structure to be measured is room temperature.

[0017] Further, in Step 1, the temperature \(T\) of the structure to be measured satisfies \(-150^{\circ}C\leq T\leq350^{\circ}C\).

[0018] Further, since the PSD has a good proportional relationship with \(1 / f\) m where \(f\) m represents the \(m\)th power of the frequency, indicating that the noise generated at the interface of the interconnect structure is low-frequency noise.

[0019] Further, the structure to be measured is a device containing an interconnect structure.

[0020] Further, the material of the interconnect structure is selected from one or more of pure metals, metal alloys, and semiconductor materials.

[0021] The interface roughness obtained by the above method of the present invention is used to analyze the influence of the resistivity, electromigration, and stress migration characteristics of the interconnect structure, and then the reliability is evaluated.

[0022] Advantages of the present invention:

[0023] In the test of the present invention, a constant low current is used, which is far lower than the electromigration threshold, to avoid damage to the metal structure caused by Joule heat or electromigration. At the same time, there is no need to cut, polish, or coat the sample (such as required for TEM / AFM), and the original state of the packaged chip is completely retained, significantly improving the reusability of the sample.

[0024] The present invention indirectly characterizes the interface roughness through electrical signals (low-frequency noise), without physical probe contact (such as AFM) or high-energy electron beam scanning (such as SEM), avoiding the introduction of surface contamination or radiation damage. It is especially suitable for on-line testing of packaged chips, and the current can be directly applied through external pins and the noise signal can be collected.

[0025] The test structure of the present invention supports a temperature range of -150°C to 350°C. Under high-temperature conditions (such as 200°C), the defect dynamics is accelerated to reveal the long-term influence of interface roughness on electromigration. The device lifetime can be extrapolated from the high-temperature k value, and it is expected to be applicable to the reliability assessment of harsh environments such as automotive electronics and high-temperature chips.

[0026] Through the strong correlation between the frequency-domain characteristics of low-frequency noise and the interface roughness, this method realizes non-destructive, highly sensitive, and global metal interconnect detection, and has both the functions of process optimization guidance and reliability prediction, providing an efficient solution for the quality control of advanced process chips. Description of the Drawings

[0027] In order to more clearly illustrate the technical solutions of the embodiments of the present invention, the embodiments of the present invention will be briefly introduced below.

[0028] Figure 1 It is a typical structure of BEOL (backend process of chip manufacturing) after PT process treatment of TaN / Ta metal barrier layer under the dual-damascene process. In the figure, M1 is the first layer of metal (such as copper material), M2 is the second layer of metal (such as copper material), V1 is the via hole (such as copper material), TaN / Ta is the barrier layer, Low k is the low-k dielectric layer, which is the insulating layer between the chip metal layers (also called the inter-metal dielectric layer).

[0029] Figure 2 It is a TEM cross-sectional view of the metal wire parallel to the wire direction after PT treatment, where (a) is VF-BSL and (b) is VF-AGG.

[0030] Figure 3It is a TEM cross-sectional view of the metal wire perpendicular to the wire direction after PT treatment, where (a) is VF-BSL and (b) is VF-AGG.

[0031] Figure 4 It is a low-frequency noise test structure.

[0032] Figure 5 In (a)- Figure 5 In (c) are the low-frequency noise tests and PSD curves of the VF-AGG sample at 200 °C in the time domain and frequency domain respectively. Specific implementation manners

[0033] To make the objectives, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below with reference to the figures. Obviously, the described embodiments are some but not all of the embodiments of the present invention. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the scope of protection of the present invention.

[0034] The terms "including" and "having" and any variations thereof mentioned in the embodiments of the present invention are intended to cover non-exclusive inclusion.

[0035] With the continuous progress of integrated circuit technology, especially in the context of gradually shrinking process nodes, the critical dimension (CD) of the chip interconnect structure has been continuously shrinking. However, when the CD shrinks below dozens of nanometers, the roughness of the wire edge or bottom does not shrink synchronously with the reduction of the nano-device size, and this problem has become a hot topic of industry concern. This makes the interface roughness problem at the microscale become more prominent, having a profound impact on the performance and reliability of the chip.

[0036] The present invention proposes a method for detecting the interface roughness of an interconnect structure - a low-frequency noise test method. Due to the non-uniformity of the sidewall and bottom edge, the current is prone to concentration at the rough edge, resulting in enhanced electron scattering. The rough surface may generate more interface states or defects, which will capture and release carriers, thereby causing current fluctuations, and thus affecting the low-frequency noise of the device such as low-frequency noise. In severe cases, it may affect the performance of semiconductor devices. Therefore, by measuring the change in low-frequency noise, the roughness of the interconnect wire can be indirectly evaluated.

[0037] The power spectral density (PSD) is obtained by calculating the current fluctuations within a frequency range, thereby obtaining information on how power is distributed in the frequency domain. Further, the sidewall or bottom roughness information of different test structures is characterized by fitting the curve slope of the power spectral density with respect to frequency. In summary, the low-frequency noise test method can nondestructively, quickly, and conveniently characterize the roughness information of the sidewalls and bottoms of chip interconnect structures or other conductor and semiconductor structures, improving reliability and the reusability of samples.

[0038] The present invention proposes a detection method for characterizing the interface roughness such as the sidewalls or bottoms of interconnect structures using low-frequency noise, including the following steps:

[0039] Step 1: Apply a constant low current \(i_c\) to the structure to be tested, and measure the output current \(i(t)\) of the structure to be tested at time \(t\). Since \(i(t)=i\) c +\(\Delta i(t)\), calculate the random current fluctuations \(\Delta i(t)\) generated by the interaction of electrons with the interface, defects, phonons, etc. of the interconnect structure.

[0040] The temperature of the structure to be tested is room temperature, or it can also be during the heating process, for example, \(-150^{\circ}C\leq T\leq350^{\circ}C\).

[0041] The structure to be tested is a device containing an interconnect structure. Among them, the material of the interconnect structure is selected from one or more of pure metals, metal alloys, and semiconductor materials.

[0042] To measure the low-frequency noise of the structure to be tested, the current density of \(i_c\) needs to be low enough to avoid electromagnetic damage and prevent additional defects. \(i_c\) is lower than the electromigration threshold, and a current density of \(0.25 MA / cm\) can be used 2 .

[0043] In this embodiment, a Keysight B1500A semiconductor parameter analyzer can be used, in cooperation with a low-noise preamplifier (Stanford Research SR560), with the bandwidth set to \(0.1 Hz - 100 kHz\) and the sampling frequency of \(1 MHz\) to ensure coverage of the low-frequency noise characteristic frequency band.

[0044] Step 2: Obtain the frequency-domain parameter \(I(f)\) of the current by performing a Fourier transform on the random current fluctuations \(\Delta i(t)\);

[0045] In one implementation, the calculation formula for the frequency-domain parameter \(I(f)\) of the current is:

[0046]

[0047] where \(f\) represents frequency and \(j\) represents the imaginary unit.

[0048] Step 3: Calculate the power spectral density PSD of the random current fluctuation according to the frequency-domain parameter I(f) of the current. The PSD is proportional to the frequency. Then, obtain the slope k by least-squares fitting. Use the slope k to evaluate the interface roughness of the interconnect structure.

[0049] The PSD measured for the structure under test is also proportional to 1 / f m which indicates that the noise is low-frequency noise. Here, f m represents the m-th power of the frequency.

[0050] In the low-frequency noise range, the frequency exponent 0 < m < 2. At relatively high frequencies where thermal noise dominates, the PSD is independent of the frequency and is proportional to 4kBT / R (kB is the Boltzmann constant, T is the temperature, and R is the line resistance).

[0051] The difference in the slope k indicates the change in low-frequency noise, which means a change in the electron scattering mechanism. Therefore, low-frequency noise measurement can be used to characterize the roughness.

[0052] In one implementation, the calculation formula for the power spectral density PSD of the random current fluctuation is:

[0053]

[0054] where p is the period of the periodic signal, and I P (f) is the segment of I(f) over the period [-p / 2, p / 2].

[0055] The noise power spectral density is a function related to the frequency, which describes the energy distribution of the noise at lower frequencies.

[0056] Low-frequency noise is jointly caused by factors such as the random processes of the material itself and defect carriers, and interface states. Low-frequency noise is jointly caused by factors such as the random processes of the material itself and defect carriers, and interface states. Additionally, the structure under test can be at room temperature or in the process of being heated. At a certain temperature, the thermally activated diffusion mechanism suddenly causes an increase in the formation and annihilation of vacancies at specific locations (such as grain boundaries or interfaces). The interaction between electrons and these vacancies changes the fluctuation of the output current, thereby also changing the low-frequency noise spectrum. The low-frequency noise characterization method can still be effectively applied to the detection and analysis of samples, can provide reliable noise characteristic data under heating conditions, and further conduct in-depth research on the behavioral characteristics of the samples.

[0057] The low-frequency noise characterization method can directly utilize the low-frequency noise generated by the structure itself as the test signal, simplifying the test device and process compared to some classical methods that require external frequency excitation signals, and reducing costs and complexity. The low-frequency noise characterization method can quickly complete experiments without damaging the sample, improving the reusability of the sample. Due to the special spectral characteristics of low-frequency noise, it can respond more sensitively to minute changes and fluctuations in the structure, and thus can provide higher sensitivity and resolution in some cases.

[0058] Example:

[0059] The samples used in the experiment were prepared in advance during the optimization of the metal barrier layer punch-through process (Punch Through, PT). The experimental samples were prepared based on the 55nm CMOS BEOL (backend process) via-first (ViaFirst, VF) process, and multiple 12-inch test wafers were used for the experiment. The specific structure is as Figure 1 shown.

[0060] Due to the deposition or etching process, micro-grooved small tips as shown in Figure 2 can be formed at both ends of the wire cross-section, where BSL represents the original PT process and AGG represents the active optimization based on the original process. Different process parameters directly result in different cross-sectional profiles of the metal wire bottom. As shown in Figure 2 and Figure 3 , the cross-sectional profile of VF-BSL without PT process optimization in (a) shows the most obvious micro-grooves. Through PT process optimization, under the same VF process, the cross-sectional profiles of VF-AGG in Figure 2 and Figure 3 in (b) are improved, showing almost invisible micro-grooves.

[0061] The TaN / Ta of the VF-AGG group is thinner than that of the VF-BSL group, with shorter re-sputtering time and lower bias voltage.

[0062] After the experimental samples were prepared, specific low-frequency noise measurements were carried out at 3 temperatures through a thermal chuck to explore the low-frequency noise characteristics of the roughness of different metal wire bottom cross-sections. The test structure mainly includes a metal wire and two vias connecting the metal wire, as shown in Figure 4 shown.

[0063] By applying a relatively low constant DC current (current density of 0.25MA / cm 2), extremely small current fluctuation noise can be obtained from metal lines based on voltage fluctuations, and it is ensured that the wires do not undergo electromigration. These fluctuations are caused by the interaction of electrons with the sidewalls, defects, phonons, etc. of the interconnects. After analyzing these fluctuations in the frequency domain through Fourier transform, the power spectral density of the noise fluctuations can be calculated and deduced, and the slope of the fitted curve can be obtained, thereby providing information on the distribution of power in the frequency domain. The calculated power spectral density PSD curve is in good proportion to 1 / f m with 0 < m < 2 in the low-frequency range. Usually, a rough surface will generate more interface states or defects, which will capture and release carriers, thereby triggering current fluctuations and affecting the low-frequency noise of the device. Figure 5 For sample VF-AGG at 0.25 MA / cm 2 , the calculation process of the current density and the power spectral density at a high temperature of 200 degrees. Among them Figure 5 Figure (a) in Figure 5 and Figure (b) in Figure 5 are the low-frequency noise tests of the VF-AGG sample at 200 °C in the time domain and the frequency domain respectively. Although the ordinate is represented by voltage, since the resistance is almost constant, the relationships between voltage and time, frequency are equivalent to the relationships between current and time, frequency respectively. Then, the PSD curve is fitted by the least squares method, as shown in Figure 5 Figure (c), and the slope k is obtained. At this time, it can be found that the PSD slope k of the low-frequency noise at 200 degrees is close to 2, which may imply more defects generated internally. When the temperature is high, the vibration of atoms in the metal becomes more intense, resulting in more collisions and scattering between electrons and atoms during movement. In addition, with the increase in temperature, thermal excitation in the metal will lead to the formation of more local defects, or a slight change in the relative positions of atoms. At the same time, metal atoms are more likely to be displaced from their original positions by moving electrons at high temperatures, forming temporary or permanent voids.

[0064] It can be found from Table 1 that at room temperature (25 °C) and at a relatively small test current, there are fewer voids and defects in the metal wire structure, so the overall slope and value are close to 1. In addition to the temperature dependence of low-frequency noise, flakes with a better cross-sectional profile and less roughness have a smaller absolute slope in the PSD of low-frequency noise. This may be because the better cross-sectional morphology reduces the collisions and scattering of electrons with the bottom of the metal wire, slowing down the generation of voids and defects. Whether at room temperature or at a higher temperature, the absolute slope of sample VF-BSL is larger than that of VF-AGG, so it can be qualitatively explained that low-frequency noise can be used to characterize structures with different cross-sections or sidewall roughnesses.

[0065] Table 1 Absolute slope k of different samples at different temperatures

[0066]

[0067] As described above, the above embodiments are only used to illustrate the technical solutions of the present invention, rather than limiting it; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements on some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A detection method for characterizing the interface roughness of an interconnect structure using low-frequency noise, characterized in that: The method comprises the following steps: Apply a constant low current i to the structure under test c , the output current i(t) of the structure to be tested at time t is measured, because i(t) = i c +Δi(t), calculates the random current fluctuation Δi(t) generated by the interaction between electrons and the interconnection structure interface, defects, and phonons; The random current fluctuation Δi(t) is transformed by Fourier transform to obtain the frequency domain parameter I(f) of the current; The power spectral density PSD of random current fluctuations is calculated based on the frequency domain parameter I(f) of the current. Since the power spectral density PSD is proportional to the frequency, the slope k is obtained by fitting. The slope k is used to evaluate the interface roughness of the interconnect structure.

2. The method according to claim 1, characterized in that: The calculation formula of the frequency domain parameter I(f) of the current is: Where f represents frequency and j represents an imaginary number.

3. The method according to claim 1, characterized in that: The power spectral density PSD of random current fluctuations is calculated as: Where p is the period of the periodic signal, I P (f) is the fragment of I(f) over the period [-p / 2, p / 2].

4. The method according to claim 1, characterized in that: The temperature of the structure to be measured is room temperature.

5. The method according to claim 1, characterized in that: The temperature T of the structure to be measured satisfies -150°C≤T≤350°C.

6. The method according to claim 1, characterized in that: The structure to be tested is a device containing an interconnection structure.

7. The method according to claim 6, characterized in that: The material of the interconnection structure is selected from one or more of pure metal, metal alloy, and semiconductor material.

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