Storage device, digital subsystem, terrestrial broadcast receiver and boot firmware method

Abstract

The present invention discloses a storage device, a digital subsystem, a terrestrial broadcast receiver and a boot firmware method. The storage device includes a first structural layer, a second structural layer and a third structural layer stacked in sequence along the thickness direction of the storage device. The first structural layer includes a first electrode connection; the second structural layer includes a shared connector connected to the first electrode, a phase change material arranged around the shared connector, and at least two connection components connected to the phase change material at intervals; the third structural layer includes an electrode connection component connected to at least two connection components. The present invention optimizes the storage device structure to improve density and performance, thereby achieving the advantages of single-chip integration, fast read and write speed, and high reliability. At the same time, the digital subsystem and terrestrial broadcast receiver using the storage device can succinctly optimize the firmware code and improve execution efficiency.

Description

[0001] This application is based on a Chinese patent application, with the corresponding application number being 2023115520296, the application date being November 16, 2023, and the application name being “Storage device, digital subsystem, terrestrial broadcast receiver, boot firmware method”. This application claims the priority of the above-mentioned Chinese patent application, and the entire contents of the above-mentioned Chinese patent application are hereby incorporated into this application by reference. Technical Field

[0002] The present invention relates to the field of memory technology, and in particular to a memory device, a digital subsystem, a terrestrial broadcast receiver and a boot firmware method. Background Art

[0003] Existing terrestrial broadcast receivers have digital signal processors and microcontrollers, both of which have program memory and data memory required for execution.

[0004] Terrestrial broadcast receivers include frequency modulation (FM) reception, amplitude modulation (AM) reception, weather band (WB) reception, etc. However, the limited storage space of existing digital signal processors and microcontrollers makes it difficult to implement frequency modulation (FM) reception, amplitude modulation (AM) reception, and weather band (WB) signal reception of terrestrial broadcast receivers. In addition, when receiving the above-mentioned multiple signals, the existing terrestrial broadcast receivers have complex execution procedures and low execution efficiency. Summary of the invention

[0005] The present invention provides a storage device, a digital subsystem, a terrestrial broadcast receiver and a boot firmware method. The present invention can optimize the storage device structure, improve the storage performance, optimize the execution program, and improve the execution efficiency.

[0006] According to a first aspect of the present disclosure, a memory device is provided. The memory device comprises a first structural layer, a second structural layer and a third structural layer stacked in sequence along the thickness direction of the memory device. The first structural layer comprises a first electrode connection. The second structural layer comprises a shared connection member connected to the first electrode, a phase change material arranged around the shared connection member and at least two connection components connected to the phase change material at intervals. The third structural layer comprises an electrode connection component connected to at least two connection components.

[0007] In one embodiment, the at least two connection components include a first connection component and a second connection component spaced apart on both sides of the phase change material, and the electrode connection component includes a second electrode connection connected to the first connection component and a third electrode connection connected to the second connection component.

[0008] In one embodiment, the first connecting component includes a first electrode connected to the phase change material, and a first connecting member connected between the first electrode and the second electrode.

[0009] The second connecting component includes a second electrode connected to the phase change material, and a second connecting member connected between the second electrode and the third electrode.

[0010] In one embodiment, the shared connection member and the phase change material penetrate the second structure layer along the thickness direction of the memory device.

[0011] The first electrode and the second electrode are respectively arranged in a thickness direction of the memory device and spaced apart from the first structure layer.

[0012] In one embodiment, the storage device further includes a base layer for supporting the first structure layer.

[0013] According to a second aspect of the present disclosure, a digital subsystem is provided, which includes a digital signal processor, a microcontroller unit coupled to the digital signal processor to provide a control signal to the digital signal processor, a memory controller coupled between the digital signal processor and the microcontroller unit, and the above-mentioned memory device.

[0014] The memory device includes a first memory coupled to the memory controller, and a plurality of memories coupled between the memory controller and the microcontroller unit.

[0015] The first memory includes a first code block for controlling a digital signal processor and a second code block for controlling a microcontroller unit, and the memory controller downloads the firmware from the first memory to the plurality of memories.

[0016] In one of the embodiments, the digital subsystem further includes a plurality of multiplexers coupled between the microcontroller unit and the memory controller, the plurality of multiplexers being matched with the plurality of memories to selectively provide address and data information to each memory and obtain address and data information from each memory through each multiplexer.

[0017] In one embodiment, the digital subsystem further includes a digital signal processor controller coupled between the digital signal processor, the memory controller and the microcontroller unit, and other multiplexers coupled between the digital signal processor and the digital signal processor controller. The digital subsystem further includes other multiple memories coupled to other multiplexers.

[0018] In one embodiment, the digital subsystem further includes a digital signal processing front end and a digital signal processing back end. The digital signal processor is coupled to the digital signal processing front end through a digital signal processor controller, and the digital signal processing front end is coupled to receive input I and Q signals from the analog subsystem. The digital signal processing back end is coupled to provide output digital signals to the analog subsystem.

[0019] In one of the embodiments, the digital subsystem further includes a control interface coupled to the memory controller and / or the microcontroller unit, the control interface coupled to send and receive data and control signals with another portion of the system.

[0020] In one embodiment, the first memory includes a non-volatile memory.

[0021] According to a third aspect of the present disclosure, a terrestrial broadcast receiver is provided, which includes an analog subsystem and the above-mentioned digital subsystem.

[0022] In one of the embodiments, a terrestrial broadcast receiver includes at least an FM antenna receiving path and an AM antenna receiving path, the signals outputted by the FM antenna receiving path and the AM antenna receiving path are respectively processed by a programmable gain amplifier module, and the output signal of the programmable gain amplifier module is converted into digital I and Q values ​​by a sigma delta analog-to-digital converter module, so as to process the digital I and Q values ​​by a digital system to generate left and right digital audio output signals which can be provided to a digital-to-analog conversion circuit to generate left and right analog output signals.

[0023] In one embodiment, the terrestrial broadcast receiver further includes a low IF module including additional circuitry for controlling the operation of the DSP circuitry when processing digital I and Q values.

[0024] In one embodiment, a terrestrial broadcast receiver includes a digital control interface arranged in the terrestrial broadcast receiver for communicating with an external device, the digital control interface being used for a digital communication interface reset input signal, a bidirectional serial data input / output signal, a serial clock input signal, and a serial interface enable input signal.

[0025] In one embodiment, the FM antenna receiving path includes an FM antenna, a first low noise amplifier module receiving an output signal of the FM antenna, and a first automatic gain control module controlling the first low noise amplifier module.

[0026] The AM antenna receiving path includes an AM antenna, a second low noise amplifier module receiving an output signal of the AM antenna, and a second automatic gain control module controlling the second low noise amplifier module.

[0027] In one embodiment, the terrestrial broadcast receiver further comprises a mixer module for receiving an input radio frequency signal and providing an intermediate frequency signal, and the output signals of the two low noise amplifier modules are respectively processed by the mixer module to generate I and Q signals.

[0028] In one of the embodiments, the terrestrial broadcast receiver further includes an automatic frequency control module and a phase-locked loop-voltage controlled oscillation module.

[0029] The local clock mixing signal is received by the mixer from the phase-locked loop-voltage controlled oscillation module, which generates two mixing signals that are 90 degrees apart from each other. The phase-locked loop-voltage controlled oscillation module receives a control signal from the automatic frequency control block, which receives a tuning error signal from a receiving path circuit within the terrestrial broadcast receiver and provides a correction control signal.

[0030] In one embodiment, the terrestrial broadcast receiver also includes a weather band reception path.

[0031] According to a fourth aspect of the present disclosure, a boot firmware method is provided. The boot firmware method is applied to the above-mentioned terrestrial broadcast receiver, wherein the digital subsystem of the terrestrial broadcast receiver includes a digital signal processor and a microcontroller unit coupled to the digital signal processor to provide a control signal to the digital signal processor, and specifically includes the following steps:

[0032] Receive power-on start signal.

[0033] Execute the startup module.

[0034] Execute the import procedure.

[0035] The microcontroller unit is powered up and used to calibrate the analog portion coupled to the digital subsystem and begin normal digital signal processor operation.

[0036] In one embodiment, the step of executing the import procedure further includes the following steps:

[0037] Import digital signal processing firmware from non-volatile memory to digital signal processing program and data random access memory. Import microcontroller firmware from non-volatile memory to microcontroller program and data random access memory.

[0038] Compared with the prior art, the present invention has the following beneficial effects:

[0039] The memory device provided by the present invention can share a shared connection piece by embedding a memory unit, and can realize heat accumulation and improve the influence on the phase change material, so that the memory device has the advantages of high density, single chip integration, fast reading and writing speed, high reliability, etc.

[0040] The digital subsystem provided by the present invention has the above storage device, which simplifies the execution program and improves the execution efficiency.

[0041] The terrestrial broadcast receiver provided by the present invention has the above-mentioned digital subsystem, so that when the terrestrial broadcast receiver realizes the reception of multiple signals at the same time but the different signals are not received at the same time, the demand for memory addressing space of the digital signal processor and the microcontroller can be effectively reduced. In addition, only the targeted program and data firmware are executed in the digital signal processor and the microcontroller, and the execution program is more concise and better, and the execution efficiency is high.

[0042] The booting firmware method provided by the present invention is applied to the above-mentioned terrestrial broadcasting receiver, so that the firmware code is concise and optimized, and the execution efficiency is high. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] Figure 1 is a block diagram of a terrestrial broadcast receiver in the present invention;

[0044] Figure 2 is a block diagram of a digital subsystem in the present invention;

[0045] Figure 3 is a flow chart of a method for booting different firmwares in the present invention;

[0046] Figure 4 is a structural diagram of a storage device in the present invention;

[0047] Figure 5 It is a manufacturing flow chart of the storage device in the present invention. DETAILED DESCRIPTION

[0048] The technical solution of the present invention will be described clearly and completely below in conjunction with the accompanying drawings of the present invention. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0049] Existing terrestrial broadcast receivers have digital signal processors and microcontrollers, both of which have program memory and data memory required for execution. Terrestrial broadcast receivers include frequency modulation (FM) reception, amplitude modulation (AM) reception, weather band (WB) reception, etc. The limited storage space of existing digital signal processors and microcontrollers makes it difficult to realize frequency modulation (FM) reception, amplitude modulation (AM) reception, and weather band (WB) signal reception of terrestrial broadcast receivers. In addition, when receiving the above-mentioned multiple signals, the existing terrestrial broadcast receivers have complex execution procedures and low execution efficiency.

[0050] See also Figure 1The present embodiment provides a terrestrial broadcast receiver 300 having analog and digital subsystems that may be integrated into a single SOC (system on chip). The terrestrial broadcast receiver 300 may be used in a portable device having an integrated terrestrial audio broadcast receiver. The portable device may be a digital media player, such as an MP3 player, and may include the ability to receive a variety of audio broadcasts, including FM spectrum and AM spectrum signals.

[0051] Specifically, the terrestrial broadcast receiver 300 includes a frequency modulation (FM) antenna 308 and an amplitude modulation (AM) antenna 309. The FM antenna 308 provides an FM signal input by the FMI to the first low noise amplifier (LNA) module 302A. The first low noise amplifier (LNA) module 302A is controlled by a first automatic gain control (AGC) module 304A. The FM antenna 308 can be tuned with an on-chip variable capacitor circuit. The AM antenna 309 provides a differential AM input signal represented by a signal, which is provided to the second low noise amplifier (LNA) module 302B through AMI (AM input positive) and RFGND (AM input negative). The second low noise amplifier (LNA) module 302B is controlled by a second automatic gain control (AGC) module 304B. The AM antenna 309 can be a ferrite strip antenna, and an on-chip variable capacitor circuit can be used to tune the AM reception.

[0052] The terrestrial broadcast receiver 300 also includes a mixer for receiving an input radio frequency (RF) signal and providing an intermediate frequency (IF) signal, and the outputs of the two low noise amplifier (LNA) modules 302A and 302B are processed by mixer modules 306A and 306B to produce I (real) and Q (imaginary) signals, respectively. These signals are processed by a programmable gain amplifier (PGA) module 330, which is controlled by a third automatic gain control (AGC) module 335. The output signal of the programmable gain amplifier (PGA) module 330 is converted into digital I and Q values ​​by a sigma delta analog-to-digital converter (ΣΔADC) module 340.

[0053] The terrestrial broadcast receiver 300 also includes an analog-to-digital converter (DAC) for converting the IF signal into a digital signal and a digital signal processor for processing the digital signal. The DSP circuit 350 processes the digital I and Q values ​​to generate left (L) and right (R) digital audio output signals that can be provided to two digital-to-analog conversion (DAC) circuits 360A and 360B, thereby generating left (LOUT) and right (ROUT) analog output signals. These analog output signals can be output to a listening device such as a headphone amplifier, and can also be output as a speaker, such as output to a headphone for listening to the analog audio output signal. Among them, the DSP circuit 350 can provide various signal processing, including digital filtering, FM and AM demodulation (DEMOD) and stereo / audio decoding (such as MPX decoding). At the same time, the terrestrial broadcast receiver 300 also includes a low IF module 355, which includes additional circuits for controlling the operation of the DSP circuit 350 when processing digital I / Q signals.

[0054] It should be noted that the digital subsystem included in the terrestrial broadcast receiver 300 may generally correspond to all circuits of the terrestrial broadcast receiver 300 to the right of the ΣΔADC module 340. Of course, at least a part of the ΣΔADC module 340 may also be included in the digital subsystem.

[0055] See also Figure 1 In some embodiments, the terrestrial broadcast receiver 300 further includes a digital control interface 370, which can be provided in the terrestrial broadcast receiver 300 to communicate with an external device such as a controller. Among them, the digital communication interface reset (RST_) input signal, the bidirectional serial data input / output (SDIO) signal, the serial clock input (SCLK) signal, and the serial interface enable (SEN_) input signal. Of course, in other embodiments, other communication interfaces can also be used according to the use requirements, including serial or parallel interfaces using synchronous or asynchronous communication protocols.

[0056] See also Figure 1 In some embodiments, the terrestrial broadcast receiver 300 further includes an integrated low-voltage dropout (LDO) module 380, which can generate a stable low voltage and reduce power consumption to help regulate on-chip power.

[0057] Continue to see Figure 1In some embodiments, the local clock mixing signal is received by mixers 306A and 306B from a phase-locked loop-voltage controlled oscillator (PLL-VCO) module 315, which generates two mixing signals that are 90 degrees out of phase with each other. The phase-locked loop-voltage controlled oscillator (PLL-VCO) module 315 receives a control signal from an automatic frequency control (AFC) module 310. The AFC module 310 can receive a tuning error signal from a receive path circuit within the terrestrial broadcast receiver 300 and provide a correction control signal.

[0058] In a method of manufacturing a terrestrial broadcast receiver 300 having analog and digital subsystems, it includes programming the radio broadcast receiver with firmware for the operation of the DSP and microcontroller. Such programming can be implemented in different ways, such as by downloading the firmware directly to one or more volatile memories of the digital radio to be executed therefrom.

[0059] See also Figure 2 In some embodiments, a digital subsystem 200 is also provided, which is applied to a terrestrial broadcast receiver. The digital subsystem 200 includes multiple cores and storage devices for processing digital data in a terrestrial broadcast receiver environment. These cores may include a digital signal processor (DSP) 220 and a microcontroller unit (MCU) 230. Among them, the DSP core 220 can be programmed to execute various algorithms for processing audio data, such as wireless radio data. The MCU core 230 can be used as a controller for the digital subsystem 200 and the analog subsystem. The storage device can be a non-volatile memory (NVM), and the NVM can be a read-only memory ROM, a one-time programmable memory (OTP), a flash memory (Flash), a phase change memory, etc.

[0060] See also Figure 2 , the digital subsystem 200 also includes a memory controller 235 coupled to the MCU core 230. The memory controller 235 can control memory access to various memories of the digital subsystem 200. Among them, the various memories include a first memory 240 for storing program data of the digital subsystem 200. The first memory 240 is set as a non-volatile memory (NVM). The first memory 240 stores various programs including firmware of both the DSP core 220 and the MCU core 230, such as a first code block for controlling the DSP core 220 and a second code block for controlling the MCU core 230. The first code block and the second code block can be firmware, and include executing the control function of the terrestrial broadcast receiver 300 and the analog calibration function of its analog part. The first memory 240 can also be a one-time programmable memory or a read-only memory, etc. in other embodiments.

[0061] The digital subsystem 200 further includes a plurality of memories and a plurality of multiplexers coupled between the MCU core 230 and the memory controller 235. The plurality of memories include a second memory 232 and a third memory 234 associated with the MCU core 230. The plurality of multiplexers include a first multiplexer 231 and a second multiplexer 233.

[0062] The first multiplexer 231 controls access to a second memory 232 associated with the MCU core 230. The second memory 232 includes a program random access memory (Program RAM) and a program non-volatile memory (Program NVM). The second multiplexer 233 controls access to a third memory 234 associated with the MCU core 230. The third memory 234 includes a data random access memory (DATARAM).

[0063] In some embodiments, the MCU core 230 may be an 8051 compatible microcontroller, which directly executes code from the second memory 232 and is used to initialize and calibrate all components of the analog signal path for the receive chain, such as low noise amplifier (LNA), programmable amplifier (PGA), mixer, analog-to-digital converter (ADC), and digital-to-analog converter (DAC), including voltage regulator (LDO), voltage controlled oscillator (VCO), and all on-chip analog blocks.

[0064] See also Figure 2 The digital subsystem 200 further includes a microcontroller unit 225, a digital signal processing front end 221, and a digital signal processing back end 222. The DSP core 220 is coupled to the digital signal processing front end 221 and the digital signal processing back end 222 through the microcontroller unit 225.

[0065] Among them, the digital signal processing front end 221 can perform various functions including DDFS, CIC extraction and comb filtering, and the digital signal processing front end 221 is configured to receive digital I / Q signals from the analog subsystem of the terrestrial broadcast receiver 300. The digital signal processing back end 222 can perform CIC interpolation and Δ-Σ DAC modulation, and the digital signal processing back end 222 is configured to provide an output digital signal to the analog subsystem of the terrestrial broadcast receiver 300.

[0066] The digital subsystem 200 also includes other multiple memories and other multiplexers coupled between the DSP core 220 and the microcontroller unit 225. The other multiple memories include a fourth memory 227 and a fifth memory 229 associated with the DSP core 220, and the other multiplexers include a third multiplexer 226 and a fourth multiplexer 228.

[0067] The third multiplexer 226 controls access to a fourth memory 227 associated with the DSP core 220. The fourth memory 227 includes a program random access memory (Program RAM) and a program non-volatile memory (Program NVM). The fourth multiplexer 228 controls access to a fifth memory 229 associated with the DSP core 220. The fifth memory 229 includes a data random access memory (DATARAM). The third multiplexer 226 and the fourth multiplexer 228 are coupled between the DSP core 220, the microcontroller unit 225, and the RAM to selectively provide address and data information to the RAM and obtain address information and data information from the RAM.

[0068] It should be noted that the DSP core 220 and its digital signal processing front end 221 and digital signal processing back end 222 may be used to perform demodulation of digitized stereo frequency modulation (FM) signals and measure signal strength, etc. The DSP core 220 may execute directly from the fourth memory 227 and the fifth memory 229. The DSP firmware responds to commands from the MCU core 230 to enable / disable stereo, change volume, etc.

[0069] See also Figure 2 In some embodiments, the digital subsystem 200 further includes a control interface 250. The MCU core 230 is coupled to the control interface 250, and the control interface 250 may be directly coupled to the memory controller 235. At the same time, the control interface 250 is also coupled to send and receive data and control signals with another part of the system.

[0070] It should be noted that the control interface 250 includes a serial port, which is used to address a register group that stores incoming and outgoing information. Some register bits control digital and analog hardware, for example, powering the on-chip voltage regulator and the startup clock. Other bits are used to communicate information between an external controller and the firmware running on the MCU core 230. This information can be used for the configuration of a terrestrial broadcast receiver and the control of a terrestrial broadcast receiver. Among them, the configuration of the terrestrial broadcast receiver 300 includes different operating modes, frequency band sizes and intervals, etc., and the control of the terrestrial broadcast receiver 300 includes tuning or finding new radio stations, changing volume, stereo / mono selection, etc. Other bits are used to control general purpose input and output (GPIO) pins, which can be controlled by the MCU core 230. In addition, the control interface 250 can be powered by a dedicated power pin to allow the registers to remain in working condition when the rest of the chip including the digital subsystem 200 is powered off.

[0071] Continue to see Figure 2In some embodiments, the MCU core 230 can also execute user commands sent via the control interface 250 to tune or find new radio stations, audio volume changes, and many other functions. When the chip boots up, the MCU core 230 uses the memory controller 235 to copy code and data from the first memory 240 to the second memory 232 and the third memory 234.

[0072] In some embodiments, the memory controller 235 may be a general purpose module that allows the control interface 250 or the MCU core 230 to initiate block data transfer between any two memories (including the non-volatile memory 240). During a normal chip boot process, the MCU core 230 issues a command to the memory controller 235 to transfer the firmware from the first memory 240 to each on-chip volatile random access memory (RAM), and the firmware may be downloaded directly to the volatile memory through a serial port to boot the chip, which may allow for efficient software development.

[0073] See also Figure 3 In some embodiments, a boot firmware method is provided, which is applied to a digital subsystem. The boot firmware method comprises the following steps:

[0074] S100: receiving a power-on start signal.

[0075] S200: Execute the startup module.

[0076] S300: Execute the import procedure.

[0077] S400: The MCU core 230 is powered up and used to calibrate the analog portion coupled to the digital subsystem 200 and start normal DSP operations.

[0078] Wherein, step S300 also includes the following two steps:

[0079] S310: Importing digital signal processing firmware from the non-volatile memory to the digital signal processing program and data random access memory.

[0080] S320: Importing microcontroller firmware from the non-volatile memory to the microcontroller program and data random access memory.

[0081] As an example, the boot firmware method can be started by receiving a power-on start signal. For example, after power is applied to the chip, the user can write a register in the control interface 250 via a serial port to provide instructions for booting the firmware. In response to such a boot signal, the program non-volatile memory 232 as a boot module can begin execution.

[0082] Next, the startup module is executed, and the chip is initialized, such as power supply, etc. Since different signals correspond to different firmware, the power-on startup signal also includes one of the three signals of frequency modulation (FM), amplitude modulation (AM) and weather band (WB) signals for preparing to receive terrestrial broadcast signals.

[0083] Next, the boot program is executed. As an example, the MCU core 230 may execute the boot module to issue commands to the memory controller 235. The issued commands may include instructions that enable the memory controller 235 to load the boot loader code from the NVM to the controller RAM.

[0084] Optionally, the MCU core 230 can put itself into a sleep mode to reduce power consumption while the memory controller 235 loads the boot loader code. When the loading is complete, the memory controller 235 can wake up the MCU core 230, and the MCU core 230 can execute the boot loader code. For example, under the control of the boot loader code, the MCU core 230 can issue a command to the memory controller 235 to clear the DSP data memory and copy small blocks of data from the first memory (NVM) 240 to the fifth memory 229 of the DSP. As an example, the second memory (RAM) 229 can store various program data, such as digital coefficients for digital filtering performed by the DSP core 220.

[0085] In some embodiments, the bootloader code may also include a small decompression algorithm that may be used to decompress the DSP firmware obtained from the first memory (NVM) 240 and loaded into the DSP RAM. The DSP firmware may correspond to the main DSP control program to implement various operations performed by the DSP core 220 during normal chip operation. After completing loading the DSP code (the DSP code may be loaded into the DSP fourth memory 227), the controller firmware may be loaded into the controller RAM.

[0086] For example, after step S310 ends, the bootloader code may issue a command to the memory controller 235 to copy the firmware of the MCU core 230 to the program fourth memory (RAM) 232. Optionally, the MCU core 230 may be put into a sleep state while the memory controller 235 loads the firmware into the program second memory 232. After completion, the memory controller 235 may wake up the MCU core 230.

[0087] Finally, the MCU core 230 can be powered on and used to calibrate the analog portion coupled to the digital subsystem 200 and start normal DSP operations. That is, the MCU core 230 can start executing its main program (i.e., firmware) from the program first memory (RAM) 227. The firmware includes code for performing power-on and calibration of various analog components. Among them, the analog components are such as the analog portion of the terrestrial broadcast receiver 300.

[0088] In addition, the MCU core 230 can perform various activities, such as setting the appropriate operating voltage and clock frequency. The MCU core 230 can also start the normal operation of the DSP core 220. In this way, the terrestrial broadcast receiver 300 can be ready for normal operation because the DSP core 220 can tune to the initial radio station and wait for user commands.

[0089] It should be noted that in the various embodiments described above, non-volatile memory such as read-only memory can be used to store firmware used with the semiconductor device. That is, different firmware functions can be downloaded directly to an on-chip volatile memory, such as a random access memory (RAM), and executed directly therefrom. In this way, concise optimization of the firmware code can be achieved without considering whether the corresponding controller and digital signal processor are suitable for the ROM space problem that usually stores the firmware.

[0090] Among them, the firmware may include programs for implementing terrestrial broadcast operations, such as demodulators, filters, radio data systems (RDS), volume control, stereo mixing, etc. If a programmable NVM is used, the downloaded data can be sent to the memory controller on the chip, which then forwards the data to various volatile memories, which then write the data to non-volatile memories under the control of the memory controller. In order to implement programming from volatile memory to non-volatile storage, a burning program can be executed on the chip's microcontroller unit (MCU) to achieve firmware update optimization.

[0091] Therefore, in the terrestrial broadcast receiver system-on-chip (SOC) solution, a digital signal processor and a microcontroller are required. If multiple signals (such as FM signals, AM signals, and weather band signals, etc.) are to be received simultaneously but different signals are not received simultaneously, the terrestrial broadcast receiver 300 provided in the above embodiments can effectively reduce the demand for memory addressing space of the digital signal processor and the microcontroller. Moreover, when the terrestrial broadcast receiver 300 receives a signal, only the targeted program and data firmware are executed in the digital signal processor and the microcontroller, and the execution program is simpler and better, and the execution efficiency is high.

[0092] It can be seen that in various terrestrial broadcast digital receivers, memory is an indispensable and important part of the system. The configuration method of memory in digital structure is one of the basic technologies of single chip system (SOC). The non-volatile memory (NVM) and memory controller of existing products use two separate chips, or a low-density single SOC integrated chip, which has high performance and cost, which is not conducive to the promotion of products. In addition, the read and write speed of traditional NVM is slow, which has a certain impact on product performance.

[0093] See also Figure 4 In some embodiments, a memory device 100 is also provided, which has the advantages of high density, single-chip integration, fast read and write speed, high reliability and low cost.

[0094] Specifically, the memory device 100 includes a first structure layer 110, a second structure layer 120 and a third structure layer 130 sequentially arranged along the thickness direction thereof. As an example, Figure 4 The X direction is the thickness direction, and the Y direction is the length direction.

[0095] The first structure layer 110 includes a first medium 110a and a first electrode connection 110b embedded in the first medium 110a, and the first electrode connection 110b extends along the X direction and penetrates the first medium 110a. Optionally, the first electrode connection 110b is disposed in the middle of the first medium 110a.

[0096] The second structural layer 120 includes a second medium 120a and a first connector 120c, a shared connector 120b, and a second connector 120d embedded in the second medium 120a and sequentially arranged in the Y direction, and a phase change material 121 is arranged around the shared connector 120b. A first electrode 140 is arranged between the first connector 120c and the phase change material 121, and a second electrode 150 is arranged between the second connector 120d and the phase change material 121. Optionally, the shared connector 120b is a shared electrode metal, and the first connector 120c and the second connector 120d are respectively used as connection metals of other electrodes.

[0097] The two ends of the shared connection member 120b spaced apart in the X direction penetrate the second structure layer 120, one end of the shared connection member 120b facing the first structure layer 110 is connected to the first electrode connection 110b, and one end of the shared connection member 120b facing the third structure layer 130 is connected to the third structure layer 130. The two ends of the first connection member 120c spaced apart in the X direction are respectively set as the first end and the second end, the first end is connected to the third structure layer 130, and the second end is connected to the first electrode 140. The two ends of the second connection member 120d spaced apart in the X direction are respectively set as the third end and the fourth end, the third end is connected to the third structure layer 130, and the fourth end is connected to the second electrode 150.

[0098] The third structure layer 130 includes a third medium 130a and a second electrode connection 130b and a third electrode connection 130c embedded in the third medium 130a, and the second electrode connection 130b and the third electrode connection 130c are arranged at intervals along the Y direction. The second electrode connection 130b extends along the X direction and penetrates the second medium 130a, and the second electrode connection 130b is connected to the first connection member 120c at the end facing the second structure layer 120. The third electrode connection 130c extends along the X direction and penetrates the second medium 130a, and the third electrode connection 130c is connected to the second connection member 120d at the end facing the second structure layer 120. Optionally, the second electrode connection 130b is a contact hole or a metal connection, and the third electrode connection 130c is a contact hole or a metal connection.

[0099] It should be noted that, in some embodiments, the memory device 100 may further include a base layer 160 having an ASIC (application specific integrated circuit) memory control circuit. The first structure layer 110 is disposed on the base layer 160, which is equivalent to the first structure layer 110, the second structure layer 120 and the third structure layer 130 forming a memory unit, and the memory unit is deposited in the base layer 160 to form the memory device 100.

[0100] When the memory device 100 is in use, when the first signal is passed to the memory device 100, data 0 is stored. When the second signal is passed to the memory device 100, data 1 is stored. As an example, the state of the memory device 100 is changed by two processes of setting (SET) or resetting (RESET) to achieve the storage of data 0 or 1. Among them, the SET process passes the first signal, the first signal is a long-time low-current signal, at which time part of the phase change material is crystallized, the resistance is reduced, and "0" is achieved. The RESET process passes the second signal, the second signal is a short-time high-pulse signal, at which time part of the phase change material is amorphous, the resistance is increased, and "1" is achieved. The SET process and RESET process of the memory device 100 can be achieved by heating the crystal by passing a current signal.

[0101] Furthermore, the first electrode 140 and the second electrode 150 are respectively made of planar thin metal to increase resistance and realize SET / RESET of the phase change material by heat.

[0102] It should also be noted that when the storage device 100 is in use, the second electrode connection 130b, the first connector 120c, the first electrode 140, the shared connector 120b and the first electrode connection 110b on the left side of the storage device 100 can constitute the electrode of the first device. The third electrode connection 130c, the second connector 120d, the second electrode 150, the shared connector 120b and the first electrode connection 110b on the right side of the storage device 100 can constitute the electrode of the second device. That is, the first device and the second device can share the shared connector 120b, and at the same time, a material with high thermal resistance and low thermal conductivity is arranged around the metal and the two phase change materials to better achieve the accumulation of heat and the influence on the phase change material, so that the storage device 100 has the advantages of high density, single-chip integration, fast read and write speed, and high reliability.

[0103] See also Figure 5 In some embodiments, the memory device 100 is fabricated based on a CMOS process. Figure 5 The direction of the arrow indicates the preparation process.

[0104] Figure 5 The method specifically includes the following steps: first, a substrate material on which a CMOS array and circuit have been prepared is selected as the base layer 160 ( Figure 5 (not shown). Optionally, the substrate may be a Si substrate, an SOI substrate, or other substrates that meet usage requirements.

[0105] Next, as in step a, a first dielectric 110a is deposited on the substrate, and a first electrode through hole is formed on a portion of the first dielectric 110a by photolithography, etching, and the like. A tungsten plugging process is performed on the first electrode through hole to form a first electrode connection 110b, thereby forming a first structural layer 110. Of course, the first electrode connection 110b may also be formed by other methods. Afterwards, a portion of the second dielectric is deposited on the first structural layer 110, and a first electrode 140 and a second electrode 150 are disposed at intervals along the Y direction on the portion of the second dielectric, so as to reserve an interval corresponding to the first electrode connection 110b between the first electrode 140 and the second electrode 150.

[0106] Next, in step b, another portion of the second medium is formed on the portion of the second medium to form a complete second medium 120 a , and the first electrode 140 and the second electrode 150 are embedded in the second medium 120 a .

[0107] Next, as in step c, a first through hole is formed in a portion of the second dielectric 120a between the first electrode 140 and the second electrode 150 by photolithography, etching or the like, and a phase change material is filled in the second dielectric 120a and the surface of the first through hole.

[0108] Next, in step d, the phase change material on the bottom wall of the first through hole and the surface of the second dielectric 120a is removed to retain the phase change material on the side wall of the first through hole and enable the first electrode connection 110b to communicate with the first through hole.

[0109] Next, in step e, a second through hole and a third through hole are formed in the second dielectric 120a on both sides of the first through hole, wherein the first electrode 140 is connected to the bottom of the second through hole, and the second electrode 150 is connected to the bottom of the third through hole.

[0110] Next, in step f, a metal material is filled on the second dielectric 120 a to form a metal layer. The metal layer can be formed on the surface of the second dielectric 120 a and filled into each through hole.

[0111] Next, as in step g, the portion of the metal layer protruding from the second medium 120a is removed, and the second medium 120a is polished to make its surface flat, and the metal layer is only retained in each through hole. As an example, the metal layer in the first through hole forms a shared connector 120b, the metal layer in the second through hole forms a first connector 120c, and the metal layer in the third through hole forms a second connector 120d. Thus, the second structural layer 120 is formed.

[0112] Next, in step h, a third dielectric 130 a is formed on the second structure layer 120 .

[0113] Next, as in step i, second and third electrode through holes are formed in the third medium 130a along the Y direction. The second electrode through hole corresponds to the first connector 120c in the second through hole, and the third electrode through hole corresponds to the second connector 120d in the third through hole.

[0114] Next, as in step j, an electrode connection layer is deposited on the surface of the third medium 130a. Optionally, the electrode connection layer can be set as a tungsten layer.

[0115] Next, as in step k, the portion of the electrode connection layer protruding from the third dielectric 130a is removed, and the third dielectric 130a is polished to make its surface flat, and the electrode connection layer is only retained in each electrode through hole. As an example, the tungsten plug in the second electrode through hole forms the second electrode connection 130b, and the tungsten plug in the third electrode through hole forms the third electrode connection 130c. Thus, the third structure layer 130 is formed. Finally, the above-mentioned memory device 100 is formed.

[0116] That is, Figure 5When the CMOS process is used, the contact holes and the pre-metal dielectric layer remain unchanged, and a high-density phase-change memory is embedded between the back-end interconnection layers of the ASIC to realize the function of a single SOC chip. The high-density phase-change memory realizes multi-bit storage in a single CELL device by optimizing the structure, thereby realizing that the storage device 100 can greatly improve the storage density and reduce the cost. The phase-change memory has a faster read and write speed and high reliability.

[0117] It should be noted that the above-mentioned storage device 100 can be used to store firmware for use with semiconductor devices. That is, different firmware functions can be downloaded directly to an on-chip volatile memory, such as a random access memory (RAM), and executed directly therefrom. In this way, the firmware code can be optimized concisely without considering whether the corresponding controller and digital signal processor are suitable for the ROM space problem where the firmware is usually stored. The firmware may include programs for implementing terrestrial broadcast operations, such as demodulators, filters, radio data systems (RDS), volume control, stereo mixing, etc. If a programmable NVM is used, the downloaded data can be sent to a memory controller on the chip, which then forwards the data to various volatile memories, which then write the data to non-volatile memories under the control of the memory controller. In order to implement programming from volatile memory to non-volatile storage, a burning program can be executed on the microcontroller unit (MCU) of the chip. Firmware update optimization can be achieved.

[0118] Meanwhile, the memory device 100 manufactured according to the above-described embodiment has various applications for semiconductor devices including nonvolatile memory. One example is that the terrestrial broadcast receiver 300 uses a nonvolatile memory.

[0119] It should be understood that the division of the above components in the present invention is only one of the embodiments, for the convenience of reading, rather than limiting the scope of protection of the present invention, as long as the above components are included and have the same function, it should be understood that they are equivalent technical solutions of the present invention. In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise", "axial", "radial", "circumferential" and the like indicate the orientation or position relationship based on the orientation or position relationship shown in the accompanying drawings, only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation to the present invention.

[0120] In addition, the terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include at least one of the features. In the description of the present invention, the meaning of "plurality" is at least two, such as two, three, etc., unless otherwise clearly and specifically defined.

[0121] In the present invention, unless otherwise clearly specified and limited, the terms "installed", "connected", "connected", "fixed" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements, unless otherwise clearly defined. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0122] In the present invention, unless otherwise clearly specified and limited, a first feature being "above" or "below" a second feature may mean that the first and second features are in direct contact, or the first and second features are in indirect contact through an intermediate medium. Moreover, a first feature being "above", "above" or "above" a second feature may mean that the first feature is directly above or obliquely above the second feature, or simply means that the first feature is higher in level than the second feature. A first feature being "below", "below" or "below" a second feature may mean that the first feature is directly below or obliquely below the second feature, or simply means that the first feature is lower in level than the second feature.

[0123] It should be noted that when an element is referred to as being "fixed to", "disposed on", "fixedly arranged on" or "installed on" another element, it may be directly on the other element or there may be a central element. When an element is considered to be "connected to" another element, it may be directly connected to the other element or there may be a central element at the same time. Furthermore, when an element is considered to be "fixedly connected to" another element, the two may be fixed in a detachable connection manner or in a non-detachable connection manner, such as socketing, snap-fitting, integral molding, welding, etc., which can be achieved in traditional technologies and will not be repeated here.

[0124] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0125] The above embodiments only express several implementation methods of the present invention, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the invention patent. It should be pointed out that, for ordinary technicians in this field, several variations and improvements can be made without departing from the inventive concept of the present invention, and these all belong to the protection scope of the present invention.

Claims

1. A digital subsystem, characterized in that: include: Digital signal processor; a microcontroller unit coupled to the digital signal processor to provide control signals to the digital signal processor; a memory controller coupled between the digital signal processor and the microcontroller unit; as well as A memory device, comprising a first memory coupled to the memory controller, and a plurality of memories coupled between the memory controller and the microcontroller unit; the first memory comprises a first code block for controlling the digital signal processor and a second code block for controlling the microcontroller unit, and the memory controller downloads firmware from the first memory to the plurality of memories; At least one memory in the memory device includes a first structure layer, a second structure layer and a third structure layer stacked in sequence along the thickness direction of the memory; the first structure layer includes a first electrode connection; the second structure layer includes a shared connection connected to the first electrode connection, a phase change material arranged around the shared connection, and at least two connection components connected to the phase change material and spaced from each other; the third structure layer includes an electrode connection component connected to the at least two connection components in a one-to-one correspondence.

2. The digital subsystem according to claim 1, characterized in that: The at least two connection components include a first connection component and a second connection component spaced apart on both sides of the phase change material, and the electrode connection component includes a second electrode connection connected to the first connection component and a third electrode connection connected to the second connection component.

3. The digital subsystem according to claim 2, characterized in that: The first connecting component includes a first electrode connected to the phase change material, and a first connecting member connected between the first electrode and the second electrode; The second connecting component includes a second electrode connected to the phase change material, and a second connecting member connected between the second electrode and the third electrode.

4. The digital subsystem according to claim 3, characterized in that: The shared connection member and the phase change material penetrate the second structural layer along the thickness direction of the memory; The first electrode and the second electrode are respectively disposed apart from the first structure layer and the third structure layer in a thickness direction of the memory.

5. The digital subsystem according to any one of claims 1 to 4, characterized in that: The memory further comprises a base layer for supporting the first structural layer.

6. The digital subsystem according to claim 1, characterized in that: The digital subsystem further includes a plurality of multiplexers coupled between the microcontroller unit and the memory controller, the plurality of multiplexers being matched with the plurality of memories to selectively provide address and data information to the plurality of memories and obtain address and data information from the plurality of memories through the plurality of multiplexers.

7. The digital subsystem according to claim 6, characterized in that: The digital subsystem also includes a digital signal processor controller coupled between the digital signal processor, the memory controller and the microcontroller unit, and multiple other multiplexers coupled between the digital signal processor and the digital signal processor controller; the digital subsystem also includes multiple other memories coupled to the multiple other multiplexers.

8. The digital subsystem according to claim 7, characterized in that: The digital subsystem also includes a digital signal processing front end and a digital signal processing back end; The digital signal processor is coupled to the digital signal processing front end through the digital signal processor controller, and the digital signal processing front end is coupled to receive input I signal and Q signal from the analog subsystem; the digital signal processing back end is coupled to provide output digital signal to the analog subsystem.

9. The digital subsystem according to claim 8, characterized in that: The digital subsystem also includes a control interface coupled to the memory controller and / or the microcontroller unit, the control interface being coupled to send and receive data and control signals with another portion of the system.

10. The digital subsystem according to claim 9, characterized in that: The first memory includes a nonvolatile memory, and the plurality of memories and the other plurality of memories include a nonvolatile memory.

11. A terrestrial broadcast receiver, characterized in that: The invention comprises an analog subsystem and a digital subsystem according to any one of claims 1 to 10.

12. The terrestrial broadcast receiver according to claim 11, characterized in that The terrestrial broadcast receiver includes at least an FM antenna receiving path and an AM antenna receiving path. The signals outputted by the FM antenna receiving path and the AM antenna receiving path are respectively processed by a programmable gain amplifier module. The output signal of the programmable gain amplifier module is converted into digital I and Q values ​​by a sigma delta analog-to-digital converter module, so as to utilize a digital system to process the digital I and Q values ​​and thereby generate left and right digital audio output signals which can be provided to a digital-to-analog conversion circuit to generate left and right analog output signals.

13. The terrestrial broadcast receiver according to claim 12, characterized in that The terrestrial broadcast receiver also includes a low IF module that includes additional circuitry for controlling the operation of the DSP circuitry when processing digital I and Q values.

14. The terrestrial broadcast receiver according to claim 13, characterized in that The terrestrial broadcast receiver includes a digital control interface provided within the terrestrial broadcast receiver to communicate with an external device, the digital control interface being used for a digital communication interface reset input signal, a bidirectional serial data input / output signal, a serial clock input signal, and a serial interface enable input signal.

15. The terrestrial broadcast receiver according to any one of claims 12 to 14, characterized in that: The FM antenna receiving path includes an FM antenna, a first low noise amplifier module that receives an output signal of the FM antenna, and a first automatic gain control module that controls the first low noise amplifier module; The AM antenna receiving path includes an AM antenna, a second low noise amplifier module that receives an output signal of the AM antenna, and a second automatic gain control module that controls the second low noise amplifier module.

16. The terrestrial broadcast receiver according to claim 15, characterized in that The terrestrial broadcast receiver further comprises a mixer module for receiving an input radio frequency signal and providing an intermediate frequency signal, and the output signals of the two low noise amplifier modules are processed by the mixer module to generate I and Q signals respectively.

17. The terrestrial broadcast receiver according to claim 16, characterized in that The terrestrial broadcast receiver also includes an automatic frequency control module and a phase-locked loop-voltage controlled oscillation module; The local clock mixing signal is received by the mixer from the phase-locked loop-voltage controlled oscillation module, the phase-locked loop-voltage controlled oscillation module generates two mixing signals that are 90 degrees apart from each other, the phase-locked loop-voltage controlled oscillation module receives a control signal from the automatic frequency control block, and the automatic frequency control module receives a tuning error signal from a receiving path circuit within the terrestrial broadcast receiver and provides a correction control signal.

18. The terrestrial broadcast receiver according to claim 12, characterized in that The terrestrial broadcast receiver also includes a weather band reception path.

19. A method for booting firmware, characterized in that: Applied to the terrestrial broadcast receiver according to any one of claims 11 to 18, specifically comprising the following steps: Receive a power-on start signal; Execute the startup module; Execute the import procedure; The microcontroller unit is powered up and used to calibrate the analog portion coupled to the digital subsystem and initiate normal digital signal processor operation.

20. The boot firmware method according to claim 19, characterized in that: The step of executing the import procedure also includes the following steps: Importing digital signal processing firmware from non-volatile memory into digital signal processing program and data random access memory; Import microcontroller firmware from non-volatile memory into microcontroller program and data RAM.

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