Storage device and data reading method thereof, and electronic device

Abstract

The present disclosure relates to a storage device and a data reading method and an electronic device thereof, and relates to the field of storage technology, and can ensure and improve the accuracy of storage data reading without selecting transistors. The storage device includes: a storage cell array, a plurality of word lines, a plurality of bit lines, and a read-write controller. The word line extends along a first direction and connects the first electrode of each ferroelectric storage cell in the corresponding row. The bit line extends along a second direction and connects the second electrode of each ferroelectric storage cell in the corresponding column. The read-write controller is connected to the word line and the bit line, and is configured to: set the voltage of each word line to a first initial voltage, and set the voltage of each bit line to a second initial voltage; set the voltage of the selected bit line to a first selected voltage, and connect the selected bit line to a sensing amplifier; set the voltage of the selected word line to a second selected voltage, so that the sensing amplifier outputs a data reading signal according to whether charge transfer occurs on the bit line.

Description

Technical Field

[0001] The present disclosure relates to the field of storage technology, and in particular to a storage device and a data reading method thereof, and an electronic device. Background Art

[0002] With the development of communication technology and digital technology, people continue to pursue products with lower power consumption, lighter weight and better performance. Storage devices, as memory devices that can store information, such as random access memory (RAM), disk, flash memory, etc., have been widely used in electronic devices. Summary of the invention

[0003] The embodiments of the present disclosure provide a storage device and a data reading method thereof, and an electronic device, which can ensure and improve the accuracy of reading storage data without a selection transistor, and effectively improve the performance of the storage device and the electronic device.

[0004] According to some embodiments, the present disclosure provides a storage device on one hand, including: a storage cell array, a plurality of word lines, a plurality of bit lines and a read-write controller. The storage cell array includes: a plurality of storage cells arranged in rows along a first direction and arranged in columns along a second direction. The storage cell includes a first electrode, a second electrode and a dielectric layer disposed between the first electrode and the second electrode. The first direction and the second direction intersect. The word line extends along the first direction and connects the first electrode of each storage cell in the corresponding row. The bit line extends along the second direction and connects the second electrode of each storage cell in the corresponding column. The read-write controller is connected to the word line and the bit line, and is configured to: set the voltage of each word line to a first initial voltage, and set the voltage of each bit line to a second initial voltage; set the voltage of the selected bit line to a first selected voltage, and connect the selected bit line to a sense amplifier; set the voltage of the selected word line to a second selected voltage, so that the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to characterize the data stored in the storage cell.

[0005] According to some embodiments, the read / write controller is further configured to: after the charge on the bit line is charge transferred and the sense amplifier outputs the data read signal, perform a recovery write operation on the memory cell to restore the read data in the memory cell.

[0006] According to some embodiments, the read / write controller includes: a control module, a word line selection circuit, a bit line selection circuit, and a sense amplifier. The word line selection circuit connects the control module and each word line, and is configured to: provide a first initial voltage to each word line in response to a first control instruction of the control module, and provide a second selected voltage to the selected word line in response to a third control instruction of the control module. The bit line selection circuit connects the control module and each bit line, and is configured to: provide a second initial voltage to each bit line in response to a first control instruction of the control module, and provide a first selected voltage to the selected bit line in response to a second control instruction of the control module. The sense amplifier connects the control module and the bit line selection circuit, and is configured to: connect the selected bit line in response to the second control instruction of the control module, and output a data read signal after the voltage of the selected word line is set to the second selected voltage. The first control instruction, the second control instruction, and the third control instruction are generated in sequence.

[0007] According to some embodiments, the sense amplifier includes: a charge integrator and a secondary amplifier. The charge integrator is configured to: after the selected bit line is turned on, measure the total amount of charge flowing into or out of the selected bit line under the first selected voltage, and convert the total amount of charge into a voltage signal as an initial read signal. The secondary amplifier is connected to the output end of the charge integrator and is configured to: compare the initial read signal with a reference signal to output a data read signal according to the comparison result between the initial read signal and the reference signal.

[0008] According to some embodiments, the second selected voltage is a reference voltage.

[0009] Accordingly, in some examples, the first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; and the first selected voltage is the sum of the reference voltage and the rated voltage.

[0010] Accordingly, in other examples, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

[0011] According to some embodiments, the present disclosure further provides a data reading method for a storage device on another aspect, which is applied to the storage device as described in any of the above embodiments. The data reading method includes the following steps.

[0012] The voltage of each word line is set to a first initial voltage, and the voltage of each bit line is set to a second initial voltage.

[0013] The voltage of the selected bit line is set to a first selected voltage, and the selected bit line is connected to the sense amplifier.

[0014] The voltage of the selected word line is set to a second selected voltage.

[0015] The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line, and the data read signal is used to represent the data stored in the memory cell.

[0016] According to some embodiments, the data reading method of the storage device further includes: after the charge on the bit line is transferred and the sense amplifier outputs the data read signal, performing a recovery write operation on the storage cell to restore the read data in the storage cell.

[0017] According to some embodiments, the data reading method of the memory device further includes: initializing the sense amplifier while turning on the sense amplifier on the selected bit line.

[0018] According to some embodiments, the second selected voltage is a reference voltage.

[0019] Accordingly, in some examples, the first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; and the first selected voltage is the sum of the reference voltage and the rated voltage.

[0020] Accordingly, in other examples, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

[0021] According to some embodiments, the present disclosure further provides an electronic device on another aspect, comprising: a storage device as described in any of the above embodiments.

[0022] The embodiments of the present disclosure may or at least have the following advantages:

[0023] In the embodiment of the present disclosure, a memory cell array is formed by using a memory cell without a transistor, and a word line is used to connect the first electrode of each memory cell of the corresponding row, and a bit line is used to connect the second electrode of each memory cell of the corresponding column. There is no need to set and layout a selection transistor in each memory cell, which is conducive to greatly improving the storage density. In addition, in the embodiment of the present disclosure, through a read-write controller connected to the word line and the bit line, the voltage of each word line can be set to the first initial voltage, the voltage of each bit line can be set to the second initial voltage, and then the voltage of the selected bit line can be set to the first selected voltage, and the selected bit line can be connected to the sense amplifier, and finally the voltage of the selected word line can be set to the second selected voltage, so that the sense amplifier outputs a data read signal according to whether the charge on the bit line has charge transfer. That is, the embodiment of the present disclosure controls the timing of the voltage transmitted by each word line and each bit line through the read-write controller, so that the data reading of the storage device can be effectively realized, while reducing the risk of misreading or missing data of the storage unit. In this way, the embodiment of the present disclosure can ensure and improve the reading accuracy of the stored data without a selection transistor, thereby effectively improving the performance of the storage device and the electronic device. BRIEF DESCRIPTION OF THE DRAWINGS

[0024] In order to more clearly illustrate the technical solutions of the embodiments of the present disclosure, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present disclosure. For ordinary technicians in this field, drawings of other embodiments can be obtained based on these drawings without creative work.

[0025] Figure 1 A schematic diagram of the structure of a storage device provided in some embodiments of the present disclosure;

[0026] Figure 2 A schematic diagram of the structure of a sensing amplifier provided in some embodiments of the present disclosure;

[0027] Figure 3 A schematic diagram of the structure of a charge integrator provided in some embodiments of the present disclosure;

[0028] Figure 4 A schematic diagram of a flow chart of a data reading method of a storage device provided in some embodiments of the present disclosure;

[0029] Figure 5 A schematic diagram of a flow chart of another method for reading data from a storage device provided in some embodiments of the present disclosure;

[0030] Figure 6 This is a flowchart of step S400 provided in some embodiments of the present disclosure.

[0031] Description of reference numerals:

[0032] U-storage unit, BL-bit line, WL-word line, 11-first electrode, 12-second electrode, 13-dielectric layer, 2-read / write controller, 21-control module, 22-word line selection circuit, 23-bit line selection circuit, 24-sense amplifier, 241-charge integrator, 411-operational amplifier, 412-feedback capacitor, 242-secondary amplifier. DETAILED DESCRIPTION

[0033] In order to facilitate understanding of the present disclosure, the present disclosure will be described more fully below with reference to the relevant drawings. Embodiments of the present disclosure are given in the drawings. However, the present disclosure can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present disclosure more thorough and comprehensive.

[0034] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which the present disclosure belongs. The terms used herein in the specification of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the present disclosure.

[0035] References to "embodiments" herein mean that a particular feature, structure, or characteristic described in conjunction with the embodiments may be included in at least one embodiment of the present disclosure. The appearance of the phrase in various places in the specification does not necessarily refer to the same embodiment, nor is it an independent or alternative embodiment that is mutually exclusive with other embodiments. It is explicitly and implicitly understood by those skilled in the art that the embodiments described herein may be combined with other embodiments.

[0036] It is understood that the terms "first", "second", etc. used in this application may be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish a first element from another element. For example, without departing from the scope of this application, a first electrode may be referred to as a second electrode, and similarly, a second electrode may be referred to as a first electrode. Both the first electrode and the second electrode are electrodes, but they are not the same electrode.

[0037] It can be understood that the "coupling" and "connection" in the following embodiments should be understood as "electrical connection", "communication connection", etc. if the coupled or connected circuits, modules, units, etc. have electrical signals or data transmission between each other.

[0038] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, the term "and / or" used in this specification includes any and all combinations of the relevant listed items.

[0039] Semiconductor memory devices are memory devices implemented based on semiconductor materials such as silicon (Si), germanium (Ge), gallium arsenide (GaAs) or indium phosphide (InP). Semiconductor memory devices can be mainly divided into volatile memory devices and non-volatile memory devices. Among them, volatile memory devices are memory devices in which the data stored will be lost when the power is disconnected. Volatile memory devices include, for example, static random access memory (SRAM), dynamic random access memory (DRAM) and synchronous dynamic random access memory (SDRAM). Non-volatile memory devices are memory devices that can retain the data stored therein even when the power is disconnected. Non-volatile memory devices include, for example, read-only memory (ROM), programmable read-only memory (PROM), electrically programmable read-only memory (EPROM), electrically erasable programmable read-only memory (EEPROM), NAND flash memory, NOR flash memory, phase change random access memory (PRAM), magnetic random access memory (MRAM), resistive random access memory (RRAM), ferroelectric random access memory (FRAM), etc.

[0040] In some embodiments, taking a ferroelectric random access memory as an example, the ferroelectric random access memory mainly forms non-volatile storage by applying voltage to change the polarization direction of the ferroelectric medium in its capacitor. Therefore, the data reading of the ferroelectric random access memory is generally destructive reading, that is, if a sufficiently high voltage is applied to the capacitor, if the polarization direction of the ferroelectric medium is opposite to the voltage direction, the polarization direction of the ferroelectric medium will be reversed, thereby generating an instantaneous current for charge transfer, and the storage data of the ferroelectric random access memory is read accordingly; and if the polarization direction of the ferroelectric medium is reversed, a reverse voltage needs to be applied after the data reading is completed to restore the destroyed storage data.

[0041] Based on this, in a ferroelectric memory cell with a selection transistor, such as a single-transistor single-ferroelectric capacitor (1T1C) memory cell, the transistor in the ferroelectric memory cell can be turned on through the word line to implement a read operation after the data read circuit is connected. However, in a ferroelectric memory cell without a selection transistor, such as a single-transistor ferroelectric capacitor (0T1C) memory cell, how to arrange the timing to ensure that the polarization reversal of the ferroelectric medium in the ferroelectric memory cell can be effectively detected while not affecting the unselected ferroelectric memory cells is a problem that needs to be solved.

[0042] In summary, the embodiments of the present disclosure provide a storage device and a data reading method thereof, and an electronic device, which can ensure and improve the accuracy of reading storage data without a selection transistor, and effectively improve the performance of the storage device and the electronic device.

[0043] See also Figure 1 , the storage device provided by the embodiment of the present disclosure includes: a storage cell array, a plurality of word lines WL, a plurality of bit lines BL and a read-write controller 2. The storage cell array includes: a plurality of storage cells U arranged in rows along a first direction (e.g., X direction) and arranged in columns along a second direction (e.g., Y direction). The first direction (e.g., X direction) and the second direction (e.g., Y direction) intersect, for example, orthogonally. The storage cell U includes a first electrode 11, a second electrode 12, and a dielectric layer 13 disposed between the first electrode 11 and the second electrode 12. That is, the storage cell U mentioned in the embodiment of the present disclosure is a storage cell of a zero-transistor single capacitor (0T1C).

[0044] By way of example, the memory cell U is a ferroelectric memory cell, and its dielectric layer 13 is a ferroelectric dielectric layer.

[0045] Illustratively, the material of the first electrode 11 and the second electrode 12 includes metal, such as titanium, titanium nitride, tantalum nitride, platinum, copper, tungsten, titanium tungsten, tungsten nitride and / or ruthenium, as well as other conductive materials and / or combinations thereof.

[0046] By way of example, the material of the ferroelectric dielectric layer includes, but is not limited to, hafnium zirconium oxide (HfZrO, also known as HZO, which includes hafnium, zirconium and oxygen), silicon-doped (Si-doped) hafnium oxide (material containing hafnium, oxygen and silicon), germanium-doped (Ge-doped) hafnium oxide (material containing hafnium, oxygen and germanium), aluminum-doped (Al-doped) hafnium oxide (material containing hafnium, oxygen and aluminum), yttrium-doped (Y-doped) hafnium oxide (material containing hafnium, oxygen and yttrium), lead zirconate titanate (hafnium-containing material, including lead, zirconium and titanium), barium zirconate titanate (material containing barium, zirconium and titanium), and combinations thereof.

[0047] For example, the first direction (e.g., X direction) and the second direction (e.g., Y direction) are both parallel to the substrate. The plurality of memory cells U included in the memory cell array can be distributed in a two-dimensional single layer not only along the first direction (e.g., X direction) and the second direction (e.g., Y direction), but also along a third direction (e.g., Z direction) perpendicular to the substrate. Figure 1 (not shown) are stacked to present a three-dimensional multi-layer distribution.

[0048] For example, Figure 1 As shown in , the first direction (eg, X direction) and the second direction (eg, Y direction) are parallel to and orthogonal to the substrate. A storage unit U is respectively provided at the intersection of the orthogonal projections of any word line WL and each bit line BL in the third direction perpendicular to the substrate.

[0049] In some embodiments of the present disclosure, please continue to refer to Figure 1 The word line WL extends along a first direction (e.g., X direction) and connects the first electrode 11 of each storage unit U in the corresponding row. The bit line BL extends along a second direction (e.g., Y direction) and connects the second electrode 12 of each storage unit U in the corresponding column. The read / write controller 2 is connected to the word line WL and the bit line BL, and is configured to: set the voltage of each word line WL to a first initial voltage, and set the voltage of each bit line BL to a second initial voltage; set the voltage of the selected bit line BL to a first selected voltage, and connect the selected bit line BL to the sense amplifier 24; set the voltage of the selected word line WL to a second selected voltage, so that the sense amplifier 24 outputs a data read signal according to whether the charge on the bit line BL undergoes charge transfer; the data read signal is used to characterize the data stored in the storage unit U.

[0050] In the embodiment of the present disclosure, a memory cell array is formed by using a memory cell U without transistors, and a word line WL is used to connect the first electrode 11 of each memory cell U in the corresponding row, and a bit line BL is used to connect the second electrode 12 of each memory cell U in the corresponding column. It is not necessary to set and layout a selection transistor in each memory cell U, which is conducive to greatly improving the storage density. In addition, in the embodiment of the present disclosure, through the read-write controller 2 connected to the word line WL and the bit line BL, the voltage of each word line WL can be set to the first initial voltage, the voltage of each bit line BL can be set to the second initial voltage, and then the voltage of the selected bit line BL can be set to the first selected voltage, and the selected bit line BL can be connected to the sense amplifier 24, and finally the voltage of the selected word line WL can be set to the second selected voltage, so that the sense amplifier 24 outputs a data read signal according to whether the charge on the bit line BL is transferred. That is, the embodiment of the present disclosure controls the timing of the voltage transmitted by each word line WL and each bit line BL through the read-write controller 2, so that the data reading of the storage device can be effectively realized, and the risk of misreading or missing data of the memory cell U can be reduced. In this way, the embodiments of the present disclosure can ensure and improve the reading accuracy of stored data without a selection transistor, thereby effectively improving the performance of the storage device and the electronic device.

[0051] It can be understood that when the storage unit U is a ferroelectric storage unit, when writing data "1" or data "0", the dielectric layer 13 (i.e., the ferroelectric material) in the ferroelectric storage unit will present different polarization states accordingly: for example, when writing data "1", the dielectric layer 13 in the ferroelectric storage unit is in a first polarization state; for example, when writing data "0", the dielectric layer 13 in the ferroelectric storage unit is in a second polarization state. The first polarization state of the dielectric layer 13 can be reversed to the second polarization state under the action of an external electric field, and the second polarization state of the dielectric layer 13 can be reversed to the first polarization state under the action of an external electric field, and the second polarization state is, for example, the initial polarization state of the ferroelectric material.

[0052] Accordingly, the voltage difference between the second selected voltage and the first selected voltage can be used to invert one polarization state of the dielectric layer 13 in the ferroelectric memory cell, while the other polarization state remains unchanged.

[0053] For example, the voltage difference between the second selected voltage and the first selected voltage can be used to reverse the first polarization state of the dielectric layer 13 while keeping the second polarization state of the dielectric layer 13 unchanged, so that: after providing the first selected voltage to the selected bit line BL and providing the second selected voltage to the selected word line WL, if the data stored in the ferroelectric memory cell is "1", the first polarization state of the dielectric layer 13 in the ferroelectric memory cell can be reversed to the second polarization state; if the data stored in the ferroelectric memory cell is "0", the second polarization state of the dielectric layer 13 in the ferroelectric memory cell remains unchanged.

[0054] On the contrary, by way of example, the voltage difference between the second selected voltage and the first selected voltage can be used to invert the second polarization state of the dielectric layer 13 while keeping the first polarization state of the dielectric layer 13 unchanged, so that: after providing the first selected voltage to the selected bit line BL and providing the second selected voltage to the selected word line WL, if the data stored in the ferroelectric memory cell is "0", the second polarization state of the dielectric layer 13 in the ferroelectric memory cell can be inverted to the first polarization state; if the data stored in the ferroelectric memory cell is "1", the first polarization state of the dielectric layer 13 in the ferroelectric memory cell remains unchanged.

[0055] It should be added that, in some embodiments, the read / write controller 2 is further configured to: perform a recovery write operation on the storage unit U to restore the read data in the storage unit U after the charge on the bit line BL is transferred and the sense amplifier 24 outputs a data read signal.

[0056] Here, it can be understood that if the charge on the bit line BL is transferred, it means that the data written in the original storage unit U has been lost during the reading process. The embodiment of the present disclosure performs a recovery write operation on the storage unit U, which is conducive to repeated reading of the stored data.

[0057] In some embodiments, please refer to Figure 1 The read / write controller 2 includes: a control module 21, a word line selection circuit 22, a bit line selection circuit 23 and a sense amplifier 24. The word line selection circuit 22 connects the control module 21 and each word line WL, and is configured to: provide a first initial voltage to each word line WL in response to a first control instruction of the control module 21, and provide a second selected voltage to the selected word line WL in response to a third control instruction of the control module 21. The bit line selection circuit 23 connects the control module 21 and each bit line BL, and is configured to: provide a second initial voltage to each bit line BL in response to a first control instruction of the control module 21, and provide a first selected voltage to the selected bit line BL in response to a second control instruction of the control module 21. The sense amplifier 24 connects the control module 21 and the bit line selection circuit 23, and is configured to: connect the selected bit line BL in response to the second control instruction of the control module 21, and output a data read signal after the voltage of the selected word line WL is set to the second selected voltage. Among them, the first control instruction, the second control instruction and the third control instruction are generated in sequence.

[0058] By way of example, the control module 21 includes but is not limited to a logic control chip.

[0059] For example, the word line selection circuit 22 and the bit line selection circuit 23 are arranged at the periphery of the memory cell array, for example, the word line selection circuit 22 and the bit line selection circuit 23 can be respectively arranged on both sides of the memory cell array, including two opposite sides or two adjacent sides. The present disclosure embodiment does not specifically limit the circuit structure of the word line selection circuit 22 and the bit line selection circuit 23, as long as the aforementioned functions can be realized. The word line selection circuit 22 and the bit line selection circuit 23 can be formed by connecting, for example, a multi-channel gate transistor.

[0060] Illustratively, the sense amplifier 24 is initialized while turning on the selected bit line.

[0061] For example, see Figure 2 , the sense amplifier 24 includes: a charge integrator 241 and a secondary amplifier 242. The charge integrator 241 is configured to: after the selected bit line BL is turned on, measure the total amount of charge flowing into or out of the selected bit line BL under the first selected voltage, and convert the total amount of charge into a voltage signal as the initial read signal. Here, the first selected voltage is a stable voltage applied to the selected bit line BL; and the total amount of charge on the bit line BL can be effectively sensed after the second selected voltage is applied to the selected word line WL. The secondary amplifier 242 is connected to the output end of the charge integrator 241, and is configured to: compare the initial read signal with a reference signal, so as to output a data read signal according to the comparison result between the initial read signal and the reference signal.

[0062] In the embodiment of the present disclosure, a charge integrator 241 and a secondary amplifier 242 are provided in the sense amplifier 24. The charge integrator 241 can be used to obtain an initial read signal through the selected bit line BL, that is, the charge integrator 241 can measure the total amount of charge flowing into or out of the selected bit line BL under the first selected voltage after the selected bit line BL is turned on, and then the voltage signal (i.e., the read sensing signal) formed by converting the total amount of charge is used as the initial read signal. Afterwards, the embodiment of the present disclosure can output a data read signal according to the comparison result of the initial read signal and the reference signal through the secondary amplifier 242 to read out the data stored in the storage unit U. Due to the above data reading process of the embodiment of the present disclosure, there is no need for the bit line BL to float during the data reading stage, which can prevent the charge change generated by the storage unit U from being shared by the parasitic capacitance of the bit line BL and related circuits such as the peripheral circuit (that is, the parasitic capacitance on the reading path of the storage unit U will not handle charge), so it will not cause too much voltage change on the selected bit line BL connected to the charge integrator 241 and the reading path of the entire storage unit U, which can effectively avoid significant attenuation or decay of the signal, thereby helping to improve the accuracy of storage data reading and enhance the performance of storage devices and electronic devices.

[0063] For some examples, see Figure 3 , the charge integrator 241 includes: an operational amplifier 411 and a feedback capacitor 412. The operational amplifier 411 has a first input terminal Input1, a second input terminal Input2 and an output terminal Output. The feedback capacitor 412 has a first electrode and a second electrode; the first electrode of the feedback capacitor 412 is connected to the second input terminal Input2 of the operational amplifier 411, and the second electrode of the feedback capacitor 412 is connected to the output terminal Output of the operational amplifier 411. Among them, the first input terminal Input1 is connected to the preset voltage terminal; the second input terminal Input2 is configured to connect the selected bit line BL and precharge to a preset voltage in the data reading stage; the output terminal Output is configured to output an initial read signal in the data reading stage.

[0064] For example, the preset voltage of the second input terminal Input2 after precharging is the same as the preset voltage of the preset voltage terminal connected to the first input terminal Input1, and the operation of the operational amplifier 411 can basically lock the voltage of the second input terminal Input2 to the preset voltage.

[0065] For example, the preset voltage of the second input terminal Input2 after pre-charging is the first selected voltage.

[0066] By way of example, the second input terminal Input2 is connected to the selected bit line BL through the bit line selection circuit 23 .

[0067] For example, the initialization of the sense amplifier 24 is achieved by initializing the charge integrator 241. The initialization of the charge integrator 241 can be expressed as precharging, that is, the initialization of the charge integrator 241 can be achieved by a correspondingly connected precharging circuit. Accordingly, when the voltage of the selected word line WL is set to the second selected voltage, the precharging circuit of the charge integrator 241 needs to be disconnected. The embodiment of the present disclosure does not specifically limit the circuit design of the aforementioned precharging circuit, so long as the aforementioned functions can be realized. Optionally, the precharging circuit can be a switching device or other circuit structure connected to a power supply voltage terminal, and the power supply voltage terminal is used to provide a rated high-level voltage.

[0068] In some examples, the secondary amplifier 242 includes but is not limited to a latch amplifier. The circuit design of the secondary amplifier 242 is such that after comparing the initial read signal with the reference signal, it can effectively output a data read signal according to the comparison result between the initial read signal and the reference signal.

[0069] It should be added that, in some embodiments, the initial read signal output by the charge integrator 241 is a voltage signal. Accordingly, the reference signal used for comparison with the initial read signal in the secondary amplifier 242 can adopt a voltage threshold. In this way, the secondary amplifier 242 is convenient for converting the initial read signal into a high level that can represent data "1" or a low level that represents data "0" by determining whether the voltage of the initial read signal crosses the set voltage threshold, so as to simplify the circuit design of the secondary amplifier 242.

[0070] It is worth mentioning that the aforementioned first initial voltage, second initial voltage, first selected voltage and second selected voltage can all be set to match the requirements. The embodiments of the present disclosure exemplarily provide some possible implementation schemes, but are not limited thereto.

[0071] In some embodiments, the second selected voltage provided to the selected word line WL is the reference voltage V1. Accordingly, the first initial voltage, the second initial voltage and the first selected voltage can all be set to match the reference voltage V1.

[0072] In some examples, the first initial voltage V2 is the sum of the reference voltage V1 and two-thirds of the rated voltage Vdd; that is, V2=V1+ The second initial voltage V3 is the sum of the reference voltage V1 and one-third of the rated voltage Vdd; that is: V3 = V1 + The first selected voltage V4 is the sum of the reference voltage V1 and the rated voltage Vdd; that is, V4=V1+Vdd.

[0073] In some other examples, the first initial voltage V2 is the difference between the reference voltage V1 and two-thirds of the rated voltage Vdd; that is, V2=V1- The second initial voltage V3 is the difference between the reference voltage V1 and one third of the rated voltage Vdd; that is, V3 = V1- The first selected voltage V4 is the difference between the reference voltage V1 and the rated voltage Vdd; that is, V4=V1-Vdd.

[0074] For example, the rated voltage Vdd may be set to match the requirement, such as a maximum supply voltage.

[0075] In the disclosed embodiment, the first initial voltage, the second initial voltage, the first selected voltage and the second selected voltage adopt the above scheme, which can make the first initial voltage, the second initial voltage and the first selected voltage present different voltage bias states respectively when the second selected voltage is used as the reference voltage V1, which is beneficial to ensure that the selected storage cell U can have a larger read sensing margin and effectively reduce the voltage disturbance of the selected storage cell U to its adjacent storage cell U, thereby further improving the data reading accuracy of the storage cell U without a selection transistor.

[0076] Some embodiments of the present disclosure also provide a data reading method for a storage device, which can be applied to the storage device described in any of the above embodiments. The data reading method for the storage device also has the technical advantages of the above storage device, which will not be described in detail here.

[0077] In some embodiments, see Figure 4 , the data reading method of the storage device includes the following steps S100~S400.

[0078] S100, setting the voltage of each word line to a first initial voltage, and setting the voltage of each bit line to a second initial voltage.

[0079] S200, setting the voltage of the selected bit line to a first selected voltage, and connecting the selected bit line to a sense amplifier.

[0080] S300, setting the voltage of the selected word line to a second selected voltage.

[0081] S400, the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line, wherein the data read signal is used to represent data stored in the storage unit.

[0082] Illustratively, the memory cell is a ferroelectric memory cell.

[0083] In some embodiments, see Figure 5 , the data reading method of the storage device also includes step S500.

[0084] S500 , after the charges on the bit line are transferred and the sense amplifier outputs a data read signal, a recovery write operation is performed on the memory cell to restore the read data in the memory cell.

[0085] In the embodiment of the present disclosure, if the charge on the bit line has been transferred, it means that the data written in the original storage unit has been lost during the reading process. The embodiment of the present disclosure performs a recovery write operation on the storage unit, which is conducive to the repeated reading of the stored data.

[0086] In some embodiments, please refer to Figure 5, step S200 further includes: initializing the sense amplifier while connecting the selected bit line to the sense amplifier.

[0087] Here, the initialization of the sense amplifier can be performed with reference to the above-mentioned related records and will not be described in detail.

[0088] It is worth mentioning that the aforementioned first initial voltage, second initial voltage, first selected voltage and second selected voltage can all be set to match the requirements. The embodiments of the present disclosure exemplarily provide some possible implementation schemes, but are not limited thereto.

[0089] In some embodiments, the second selected voltage provided to the selected word line WL is the reference voltage V1. Accordingly, the first initial voltage, the second initial voltage, and the first selected voltage may be set to match the reference voltage V1.

[0090] In some examples, the first initial voltage V2 is the sum of the reference voltage V1 and two-thirds of the rated voltage Vdd; that is, V2=V1+ The second initial voltage V3 is the sum of the reference voltage V1 and one-third of the rated voltage Vdd; that is: V3 = V1 + The first selected voltage V4 is the sum of the reference voltage V1 and the rated voltage Vdd; that is, V4=V1+Vdd.

[0091] In some other examples, the first initial voltage V2 is the difference between the reference voltage V1 and two-thirds of the rated voltage Vdd; that is, V2=V1- The second initial voltage V3 is the difference between the reference voltage V1 and one third of the rated voltage Vdd; that is, V3 = V1- The first selected voltage V4 is the difference between the reference voltage V1 and the rated voltage Vdd; that is, V4=V1-Vdd.

[0092] For example, the rated voltage Vdd may be set to match the requirement, such as a maximum supply voltage.

[0093] In the disclosed embodiment, the first initial voltage, the second initial voltage, the first selected voltage and the second selected voltage adopt the above scheme, which can make the voltages corresponding to the first initial voltage, the second initial voltage and the first selected voltage respectively present different voltage bias states when the second selected voltage is used as the reference voltage, which is beneficial to ensure that the selected storage unit U can have a larger read sensing margin and effectively reduce the voltage disturbance of the selected storage unit U to its adjacent storage unit U, thereby further improving the data reading accuracy of the storage unit U without a selection transistor.

[0094] It is necessary to add that Figure 2 and Figure 6 It is understood that, in some embodiments, the sensing amplifier 4 includes: a charge integrator 241 and a secondary amplifier 242. Accordingly, step S400 may include the following steps S410 and S420.

[0095] S410, after the selected bit line is turned on, the charge integrator measures the total amount of charge flowing into or out of the bit line at a first selected voltage, and uses the voltage signal converted from the total amount of charge as an initial read signal.

[0096] S420 , the secondary amplifier compares the initial read signal with a reference signal to output a data read signal according to a comparison result between the initial read signal and the reference signal.

[0097] Here, the data read signal is used to represent the data stored in the memory unit U.

[0098] In the embodiment of the present disclosure, after measuring the total amount of charge flowing into or out of the selected bit line under the first selected voltage, the charge integrator can convert the total amount of charge into a voltage signal (i.e., a read sensing signal) as an initial read signal; the secondary comparator can output a data read signal based on the comparison result of the initial read signal and the reference signal to read out the data stored in the storage unit. Due to the above data reading process of the embodiment of the present disclosure, there is no need for the bit line to float in the data reading stage, which can avoid the charge change generated by the storage unit being shared by the parasitic capacitance of the bit line and related circuits such as the peripheral circuit (i.e., the parasitic capacitance on the storage unit reading path will not absorb and release charge), so it will not cause too much voltage change on the selected bit line connected to the charge integrator and the reading path of the entire storage unit, which can effectively avoid the signal from being greatly attenuated or decayed, thereby helping to improve the accuracy of the storage data reading, so as to improve the performance of the storage device and the electronic device.

[0099] Some embodiments of the present disclosure also provide an electronic device, such as a data storage device, a copier, a network device, a household appliance, an instrument, a mobile phone, a computer, or other device with a data storage function. The electronic device may include the storage device in some of the above embodiments. The electronic device may also include other necessary elements or components, which are not limited in the embodiments of the present disclosure.

[0100] The technical features of the above-described embodiments may be arbitrarily combined. To make the description concise, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0101] The above-described embodiments only express several implementation methods of the present disclosure, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the patent application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present disclosure, and these all belong to the protection scope of the present disclosure. Therefore, the protection scope of the patent of the present disclosure shall be subject to the attached claims.

Claims

1. A storage device, characterized in that: include: A memory cell array, comprising: a plurality of memory cells arranged in rows along a first direction and arranged in columns along a second direction; the memory cells comprising a first electrode, a second electrode and a dielectric layer disposed between the first electrode and the second electrode; the first direction and the second direction intersect; A plurality of word lines; the word lines extend along the first direction and connect the first electrodes of the memory cells in the corresponding row; A plurality of bit lines; the bit lines extend along the second direction and connect the second electrodes of the memory cells in the corresponding columns; A read / write controller is connected to the word line and the bit line and is configured as follows: Setting the voltage of each word line to a first initial voltage, and setting the voltage of each bit line to a second initial voltage; Setting the voltage of the selected bit line to a first selected voltage and connecting the selected bit line to a sense amplifier; Setting the voltage of the selected word line to a second selected voltage so that the sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line; the data read signal is used to represent the data stored in the storage unit; Wherein, the second selected voltage is a reference voltage; wherein, The first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; the first selected voltage is the sum of the reference voltage and the rated voltage; Or, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

2. The storage device according to claim 1, characterized in that The read / write controller is further configured to perform a recovery write operation on the memory cell to restore the read data in the memory cell after the charge on the bit line is transferred and the sense amplifier outputs the data read signal.

3. The storage device according to claim 1, characterized in that: The read-write controller includes: Control module; A word line selection circuit, connected to the control module and each of the word lines, configured to: provide the first initial voltage to each of the word lines in response to a first control instruction of the control module, and provide the second selected voltage to the selected word line in response to a third control instruction of the control module; A bit line selection circuit is connected to the control module and each bit line, and is configured to: provide the second initial voltage to each bit line in response to the first control instruction of the control module, and provide the first selected voltage to the selected bit line in response to the second control instruction of the control module; a sense amplifier connected to the control module and the bit line selection circuit, configured to: connect the selected bit line in response to the second control instruction of the control module, and output the data read signal after the voltage of the selected word line is set to the second selected voltage; The first control instruction, the second control instruction and the third control instruction are generated in sequence.

4. The storage device according to claim 3, characterized in that: The sense amplifier comprises: a charge integrator configured to: after the selected bit line is turned on, measure the total amount of charge flowing into or out of the bit line at the first selected voltage, and convert the total amount of charge into a voltage as an initial read signal; The secondary amplifier is connected to the output end of the charge integrator and is configured to compare the initial read signal with a reference signal to output the data read signal according to the comparison result between the initial read signal and the reference signal.

5. The storage device according to any one of claims 1 to 4, characterized in that: The rated voltage includes the maximum supply voltage.

6. A method for reading data from a storage device, characterized in that: Applicable to a storage device as claimed in any one of claims 1 to 5; The data reading method comprises: Setting the voltage of each word line to a first initial voltage, and setting the voltage of each bit line to a second initial voltage; Setting the voltage of the selected bit line to a first selected voltage and connecting the selected bit line to a sense amplifier; Setting the voltage of the selected word line to a second selected voltage; The sense amplifier outputs a data read signal according to whether charge transfer occurs on the bit line, and the data read signal is used to represent the data stored in the storage unit; Wherein, the second selected voltage is a reference voltage; wherein, The first initial voltage is the sum of the reference voltage and two-thirds of the rated voltage; the second initial voltage is the sum of the reference voltage and one-third of the rated voltage; the first selected voltage is the sum of the reference voltage and the rated voltage; Or, the first initial voltage is the difference between the reference voltage and two-thirds of the rated voltage; the second initial voltage is the difference between the reference voltage and one-third of the rated voltage; and the first selected voltage is the difference between the reference voltage and the rated voltage.

7. The data reading method of the storage device according to claim 6, characterized in that: Also includes: After the charges on the bit line are transferred and the sense amplifier outputs the data read signal, a recovery write operation is performed on the memory cell to restore the read data in the memory cell.

8. The data reading method of the storage device according to claim 6, characterized in that: Also includes: The sense amplifier is initialized while the selected bit line is turned on.

9. The data reading method of the storage device according to claim 6, characterized in that: The rated voltage includes the maximum supply voltage.

10. An electronic device, characterized in that: include: The storage device according to any one of claims 1 to 5.

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