Chip clock domain wiring resource generation method, wiring method, device and equipment

Abstract

The present invention relates to the field of chip design technology, and discloses a method for generating chip clock domain wiring resources, a wiring method, a device and an apparatus, wherein the method for generating chip clock domain wiring resources comprises: obtaining multiple local paths, any complete clock signal transmission path on the chip can be obtained by combining some local paths in the multiple local paths, and each of the local paths spans at least one functional unit block; generating wiring resources for each of the local paths. The present invention greatly improves the speed of the wiring path and reduces the memory required for wiring.

Description

Technical Field

[0001] The present invention relates to the technical field of chip design, and in particular to a method for generating chip clock domain wiring resources, a wiring method, a device and equipment. Background Art

[0002] "Clock Region" (CR) is a concept in digital system design, referring to a group of logic elements or circuits running under the same clock signal.

[0003] There are a large number of logic resources in the Field Programmable Gate Array (FPGA) chip, and these logic resources need clock control. In order to ensure stable data transmission and processing, it is usually necessary to synchronize the clock signal. The clock domain provides a unified clock signal, so that components in the unified clock domain can run synchronously, thereby avoiding timing problems caused by different clock signals. The concept of clock domain is to help FPGA designers better manage clock resources and logic resources, so as to achieve better timing performance and clock distribution during design. Each clock domain has its own clock network, which is independent of the clock networks of other clock domains. Such division can improve the locality of the clock network and reduce the propagation delay of the clock signal, thereby better controlling the timing.

[0004] The traditional chip clock domain routing method is a simple traversal search. Traverse the connection relationship of the starting point, then traverse the points found through these connection relationships, and so on. However, routing using this method takes a long time. Specifically, compared with traditional routing in non-clock domains, the clock domain is characterized by a very large fan-out. A certain output port on the clock domain may be connected to hundreds or thousands of other ports. This is rare in non-clock domain routing, but very common in clock domain routing. The huge fan-out also leads to extremely low efficiency in traversal path search. Most of the searched points are irrelevant to the required connections, which results in slow routing. Summary of the invention

[0005] In view of this, the present invention provides a method for generating chip clock domain wiring resources, a wiring method, a device and equipment to solve the problem of slow chip clock domain wiring speed.

[0006] In a first aspect, the present invention provides a method for generating chip clock domain wiring resources, the method comprising:

[0007] Acquire multiple partial paths, where any complete clock signal transmission path on the chip can be obtained by combining some of the partial paths in the multiple partial paths, and each partial path spans at least one functional unit block;

[0008] Generate routing resources for each local path.

[0009] In the embodiment of the present invention, multiple local paths are obtained in advance, and the principle of obtaining these local paths is to ensure that any complete clock signal transmission path can be spliced ​​by some of the local paths, which means that the segmented local paths are obtained in advance when the wiring resources are generated, and each local path spans at least one functional unit block. Then, when the wiring path is subsequently wired, it is not necessary to select one component at a time like traditional wiring, but to select one path at a time. Selecting one component at a time may require thousands of times or even more, while selecting one path at a time has a limited number of selections, and generally only a few selections are required to splice a complete clock signal transmission path. Therefore, when wiring a clock domain with a high fan-out, the number of invalid selections is greatly reduced, the speed of selecting a wiring path is greatly improved, and the memory required for wiring is also reduced.

[0010] In an optional implementation, obtaining multiple local paths includes:

[0011] For the clock management module, a first partial path is obtained with the input-output functional unit block connected to the clock management module as a starting point and the global clock switch box connected to the clock management module as an end point, and a second partial path is obtained with the clock management module as a starting point and the global clock switch box connected to the clock management module as an end point;

[0012] Obtain a third local path having the global clock switch box as a starting point and the main local clock switch box as an end point;

[0013] Obtaining a fourth local path having the main local clock switch box as a starting point and the switch box as an end point;

[0014] A fifth partial path is obtained, which has the switch box as a starting point and a logic component in the logic component group directly connected to the switch box as an end point.

[0015] In an optional implementation, obtaining a fourth local path with the main local clock switch box as a starting point and the switch box as an end point includes:

[0016] Determine whether the paths connecting the secondary local clock switch boxes and the switch boxes of different main local clock switch boxes are consistent;

[0017] If they are consistent, the fourth local path is obtained for only one main local clock switch box;

[0018] If they are inconsistent, the fourth local path is obtained for each main local clock switch box.

[0019] In an optional implementation, obtaining multiple local paths includes:

[0020] For the clock management module, a first partial path is obtained with the input-output functional unit block connected to the clock management module as a starting point and the global clock switch box connected to the clock management module as an end point, and a second partial path is obtained with the clock management module as a starting point and the global clock switch box connected to the clock management module as an end point;

[0021] Acquire a sixth partial path with the first global clock switch box as a starting point and the second global clock switch box as an end point; wherein the second global clock switch box is a global clock switch box other than the first global clock switch box;

[0022] A seventh local path is obtained by taking the global clock switch box as a starting point, passing through a primary local clock switch box directly connected to the global clock switch box, and then passing through a secondary local clock switch box, with the switch box as a terminal point;

[0023] A fifth partial path is obtained, which has the switch box as a starting point and a logic component in the logic component group directly connected to the switch box as an end point.

[0024] In an optional implementation, for a clock management module, obtaining a first partial path with an input / output functional unit block connected to the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, and obtaining a second partial path with the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point include:

[0025] In the case where the chip includes multiple clock management modules, determining whether the paths connecting the input and output functional unit blocks and the global clock switch box of different clock management modules are consistent;

[0026] If they are consistent, the first partial path and the second partial path are obtained for only one clock management module;

[0027] If they are inconsistent, the first partial path and the second partial path are acquired for the clock management module respectively.

[0028] In a second aspect, the present invention provides a chip clock domain wiring method, the method comprising:

[0029] Acquire wiring resources, where the wiring resources are generated according to the generation method of the first aspect or any corresponding embodiment thereof;

[0030] Get the wiring start point and wiring end point;

[0031] Selecting multiple wiring resources that can connect a wiring start point and a wiring end point by splicing from wiring resources;

[0032] Complete the routing using the selected routing resources.

[0033] In an optional implementation, selecting a plurality of wiring resources that can connect a wiring start point and a wiring end point by splicing from wiring resources includes:

[0034] Selecting a wiring resource corresponding to a first partial path or a second partial path from the wiring resources according to the wiring starting point, wherein the starting point of the first partial path is the input / output functional unit block and the end point is the global clock switch box, and the starting point of the second partial path is the clock management module and the end point is the global clock switch box;

[0035] According to the end point of the selected routing resource corresponding to the first local path or the second local path, a routing resource corresponding to a third local path is selected from the routing resources, wherein the starting point of the third local path is the global clock switch box and the end point is the main local clock switch box;

[0036] According to the end point of the wiring resource corresponding to the selected third local path, a wiring resource corresponding to a fourth local path is selected from the wiring resources, wherein the starting point of the fourth local path is the main local clock switch box and the end point is the switch box;

[0037] According to the end point and the routing end point of the routing resources corresponding to the selected fourth partial path, routing resources corresponding to a fifth partial path are selected from the routing resources, wherein the starting point of the fifth partial path is the switch box and the end point is the logic component in the logic component group.

[0038] In an optional implementation, completing routing using the selected routing resources includes:

[0039] Determine whether the selected wiring resource is a universal wiring resource; when generating wiring resources, if the starting points and end points of multiple local paths are at different positions in the chip, but the functional unit block structures to which the starting points and end points belong are the same and the functional unit block structures passed through are the same, then only one universal wiring resource is generated;

[0040] If so, the general wiring resources are moved to the chip location where the wiring resources are needed.

[0041] In a third aspect, the present invention provides a device for generating chip clock domain wiring resources, the device comprising:

[0042] A local path acquisition module is used to acquire multiple local paths. Any complete clock signal transmission path on the chip can be obtained by combining some of the local paths in the multiple local paths. Each local path spans at least one functional unit block.

[0043] A generation module is used to generate routing resources for each local path.

[0044] In a fourth aspect, the present invention provides a chip clock domain wiring device, the device comprising:

[0045] A wiring resource acquisition module, used to acquire wiring resources, where the wiring resources are generated according to the generation method of the first aspect or any corresponding embodiment thereof;

[0046] A wiring requirement acquisition module is used to obtain the wiring starting point and wiring end point;

[0047] A selection module is used to select a plurality of wiring resources from the wiring resources that can connect the wiring start point and the wiring end point through splicing;

[0048] The routing module is used to complete routing using the selected routing resources.

[0049] In a fifth aspect, the present invention provides a computer device, comprising: a memory and a processor, the memory and the processor are communicatively connected to each other, computer instructions are stored in the memory, and the processor executes the chip clock domain wiring resource generation method of the above-mentioned first aspect or any corresponding embodiment thereof, or executes the chip clock domain wiring method of the above-mentioned second aspect or any corresponding embodiment thereof by executing the computer instructions.

[0050] In a sixth aspect, the present invention provides a computer-readable storage medium having computer instructions stored thereon, the computer instructions being used to enable a computer to execute the chip clock domain routing resource generation method of the first aspect or any corresponding embodiment thereof, or to execute the chip clock domain routing method of the second aspect or any corresponding embodiment thereof. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the specific implementation methods of the present invention or the technical solutions in the prior art, the drawings required for use in the specific implementation methods or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are some implementation methods of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0052] Figure 1 This is a typical structural diagram of an FPGA chip;

[0053] Figure 2 It is a schematic diagram of the structure of the FPGA chip including clock domain related components;

[0054] Figure 3 It is a schematic diagram of the structure of a clock domain;

[0055] Figure 4is a flow chart of a method for generating chip clock domain wiring resources according to an embodiment of the present invention;

[0056] Figure 5 is a schematic diagram of a first partial path and a second partial path according to an embodiment of the present invention;

[0057] Figure 6 is a schematic diagram of a third partial path according to an embodiment of the present invention, which is a third partial path because return is illegal;

[0058] Figure 7 is a schematic flow chart of a chip clock domain wiring method according to an embodiment of the present invention;

[0059] Figure 8 is a structural block diagram of a device for generating chip clock domain wiring resources according to an embodiment of the present invention;

[0060] Fig. 9 is a structural block diagram of a chip clock domain wiring device according to an embodiment of the present invention;

[0061] Fig.10 It is a schematic diagram of the hardware structure of a computer device according to an embodiment of the present invention. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solution and advantages of the embodiments of the present invention clearer, the technical solution in the embodiments of the present invention will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present invention.

[0063] A typical structure of an FPGA, if it does not include clock-related components, is as follows Figure 1 As shown. Figure 1 In the figure, the green blocks are logic component groups (LOG Tile) and the blue blocks are switch boxes (SWH Tile). If we consider the clock domain of the FPGA, then the structure of the FPGA is as follows: Figure 2 As shown. Considering the clock domain, FPGA not only has logic component groups and switch boxes, but also some other functional unit blocks (Tiles) for clock signal transmission, such as the clock management module (CMT, the blue long bar on the far left), the global clock switch box (GCW, the green square, note, not the green LOG Tile), and the local clock switch box (including the main local clock switch box (LCH_ROOT) and the sub-local clock switch box (LCH_LEAF)). It should be noted that the input and output functional unit block (IO Tile) belongs to the logic component group. Figure 2It is marked in white in the figure to highlight the point, not to say that IO is not a LOG Tile.

[0064] Figure 2 As you can see, IO is connected to CMT (black line), CMT is connected to GCW (black line), GCW is connected to the surrounding adjacent GCWs (green line), GCW is also connected to LCH_ROOT in the adjacent clock domain (green line), LCH_ROOT is connected to all LCH_LEAFs in the same clock domain (red line). Figure 2 In the figure, four clock domains are drawn. It can be seen that the two clock domains on the left are directly connected to the CMT, while the two clock domains on the right are not directly connected to the CMT. The CMT must manage these clock domains through the GCW. Similarly, when the FPGA is larger (due to size limitations, Figure 2 Only four clock domains are drawn, and each clock domain contains very few tiles. In fact, there will be more clock domains in an FPGA, and each clock domain contains more tiles). Usually in a row, only one clock domain will be directly connected to the CMT, and the other clock domains in this row are indirectly connected to the CMT through GCW.

[0065] At the same time, it can be found that the leftmost column of GCWs is exclusively occupied by a certain clock domain, because there is no other clock domain on the left of these GCWs; the middle column of GCWs is shared by the left and right clock domains; the rightmost column of GCWs is also exclusively occupied by a certain clock domain, because there is no other clock domain on the right of the GCW. By analogy, when the FPGA is larger, if the GCW at the edge is only connected to one clock domain, it is exclusively occupied by this clock domain; if it is connected to two clock domains, it is shared by the two clock domains.

[0066] The transmission path of the clock signal is:

[0067] 1. Some clock signals are defined by the user, so their transmission paths are:

[0068] FPGA input and output (IO) -> clock management module (CMT Tile) -> a clock domain -> a specific LOG Tile in a clock domain;

[0069] 2. Some clock signals are defined and generated by the FPGA itself, so their transmission paths are:

[0070] Clock management module (CMT Tile) -> a clock domain -> a specific LOG Tile in a clock domain.

[0071] That is to say, there are two starting points for the clock signal, FPGA input IO, or CMT. Among them, IO is also a kind of LOG Tile, while CMT Tile is a special Tile and does not belong to LOG Tile. The user-defined clock signal starts from IO and reaches CMT; while the FPGA's own clock signal starts directly from CMT. After that, the clock signal goes from CMT to GCW. Figure 2 As can be seen in the figure, CMT is connected to some GCWs. GCW is also a tile belonging to the clock domain, located outside the clock domain. A GCW will connect to several different clock domains and other GCWs around it, similar to SWH connecting to several different SWHs around it. After the clock signal reaches the GCW, if it can reach the destination clock domain from this GCW, then it will enter this clock domain; otherwise, it will enter other GCWs until the destination clock domain is found. After reaching the clock domain, the clock signal will first be transmitted from the GCW to the main local clock switch box (LCH_ROOT). LCH_ROOT is connected to several sub-local clock switch boxes (LCH_LEAF), and each sub-local clock switch box is connected to several SWHs, so that one LCH_ROOT manages multiple LCH_LEAFs, and one LCH_LEAF manages multiple SWHs. In this way, one LCH_ROOT manages all SWHs in a clock domain, and thus manages all LOG Tiles.

[0072] For a specific clock domain, see Figure 3 First of all, it should be noted that Figure 3 The routing of non-clock domains is omitted (see Figure 2 In a clock domain, there is a master local clock switch box (LCH_ROOT), Figure 3 In the figure, there are several slave local clock switch boxes (LCH_LEAF), which are indicated by red blocks. Figure 3 It is represented by yellow squares. The clock-related connection relationship is represented by red lines. It can be seen that the main local clock switch box receives the clock signal from the GCW, and connects all the sub-local clock switch boxes (all in this clock domain), schedules all the clocks in the clock domain, and inputs the corresponding clock signal to the sub-local clock switch box. The sub-local clock switch box is connected to several corresponding SWHs. The clock signal starts from LCH_ROOT, passes through LCH_LEAF, reaches the SWH corresponding to the destination logic component, and then reaches LOGTile from SWH (ultimately reaches the destination logic component). This is the clock-related connection relationship within a clock domain. The above path is the section "a certain clock domain -> a specific LOG Tile on a certain clock domain".

[0073] The traditional chip clock domain wiring method is a simple traversal search. Traverse the connection relationship of the starting point, then traverse the points found through these connection relationships, and so on. However, using such a method for wiring is very time-consuming and memory occupies a lot. An embodiment of the present invention provides a method for generating chip clock domain wiring resources, and a method for wiring based on the generated wiring resources, which can greatly reduce the wiring time.

[0074] According to an embodiment of the present invention, an embodiment of a method for generating chip clock domain routing resources is provided. It should be noted that the steps shown in the flowchart of the accompanying drawings can be executed in a computer system such as a set of executable computer instructions, and although the logical order is shown in the flowchart, in some cases, the steps shown or described can be executed in an order different from that shown here.

[0075] In this embodiment, a method for generating chip clock domain wiring resources is provided, which can be used in a computer device that can run an FPGA design tool. Figure 4 is a flow chart of a method for generating chip clock domain routing resources according to an embodiment of the present invention, such as Figure 4 As shown, the process includes the following steps:

[0076] Step S401, obtaining multiple local paths. Any complete clock signal transmission path on the chip can be obtained by combining some local paths among the multiple local paths. Each local path spans at least one functional unit block; the local path can be called a "Pattern".

[0077] In the embodiment of the present invention, the complete clock signal transmission path is generally a path without a return path, and accordingly, when obtaining a partial path, a path with a return path will not be obtained. However, it is not excluded that in some cases, the possibility of allowing a return path to appear is allowed.

[0078] Step S402: Generate routing resources for each local path. Specifically, these routing resources can be saved with the starting point and the end point of the path as indexes and the path as a value, and can be saved in a file. These routing resources can be called pattern-based routing resources.

[0079] In the embodiment of the present invention, multiple local paths are obtained in advance, and the principle of obtaining these local paths is to ensure that any complete clock signal transmission path can be spliced ​​by some of the local paths, which means that the segmented local paths are obtained in advance when the wiring resources are generated, and each local path spans at least one functional unit block. Then, when the wiring path is subsequently wired, it is not necessary to select one component at a time like traditional wiring, but to select one path at a time. Selecting one component at a time may require thousands of times or even more, while selecting one path at a time has a limited number of selections, and generally only a few selections are required to splice a complete clock signal transmission path. Therefore, when wiring a clock domain with a high fan-out, the number of invalid selections is greatly reduced, the speed of selecting a wiring path is greatly improved, and the memory required for wiring is also reduced.

[0080] A complete clock signal transmission path is obtained by combining multiple local paths. In other words, a complete clock signal transmission path can be divided into multiple local paths. There is no limit to the division method of multiple local paths, as long as it can meet the needs of subsequent splicing into complete clock signal transmission paths. However, different division methods require different numbers of wiring resources to be generated, and the time required for subsequent wiring is also different. Generally speaking, the larger the granularity of the division of the local path, the larger the number of wiring resources generated, and the less time required for subsequent wiring, and vice versa.

[0081] Based on the above, a complete clock signal transmission path is input-output functional unit block (IO)->clock management module (CMT)->one or more global clock switch boxes (GCW)->main local clock switch box (LCH_ROOT)->sub-local clock switch box (LCH_LEAF)->switch box (SWH)->logic component group (LOG Tile)->destination logic component, or clock management module (CMT)->one or more global clock switch boxes (GCW)->main local clock switch box (LCH_ROOT)->sub-local clock switch box (LCH_LEAF)->switch box (SWH)->logic component group (LOG Tile)->destination logic component. The only difference between the two is that one goes from IO through CMT to GCW, or from CMT as the starting point to GCW.

[0082] The following example illustrates the method of dividing the local path.

[0083] In some optional specific implementations, step S401, i.e., obtaining multiple local paths, includes:

[0084] Step S4011, for the clock management module (CMT), a first partial path with an input / output functional unit block connected to the clock management module (CMT) as a starting point and a global clock switch box (GCW) connected to the clock management module (CMT) as an end point is obtained, and a second partial path with the clock management module (CMT) as a starting point and a global clock switch box connected to the clock management module (CMT) as an end point is obtained;

[0085] The global clock switch box (GCW) as the end point here may be the global clock switch box (GCW) adjacent to the clock management module (CMT), or it may not be. However, both the first local path and the second local path include at least the global clock switch box adjacent to the clock management module as the local path of the end point. This is to meet the routing requirements of the destination clock domain, that is, the clock domain adjacent to the clock management module.

[0086] See also Figure 5 (The specific structure of the Tile inside is not shown in the figure). The starting point of a complete clock signal transmission path must be the output of a certain logic component, and the end point must be the input of a certain logic component. Figure 5 In the example, the starting point of the first partial path and the second partial path is also the starting point of the clock signal transmission path, so the starting point of the first partial path and the second partial path is the output of a logic component in the input / output functional unit block (IO) or the clock management module (CMT). However, the end point of the first partial path and the second partial path is not the end point of the clock signal transmission path, so, Figure 5 The end point of the first partial path and the second partial path is an input port of GCW, rather than the input of a logic device in GCW.

[0087] If the FPGA chip has multiple clock management modules (CMTs), and the connection paths of these clock management modules and the input and output functional unit blocks and the global clock switch box are consistent, then only the first partial path and the second partial path need to be obtained for one of the clock management modules (CMTs). Otherwise, the first partial path and the second partial path need to be obtained for different clock management modules (CMTs).

[0088] Step S4012, obtaining a third local path with the global clock switch box (GCW) as a starting point and the main local clock switch box (LCH_ROOT) as an end point;

[0089] Specifically, the starting point of the third local path is the input port of the global clock switch box (GCW), and then passes through the global clock switch box (GCW). At this time, there are two possibilities:

[0090] 1. The clock domain corresponding to this GCW is the clock domain where the target endpoint is located. At this time, after passing through the GCW, it will directly reach the input port of the main local clock switch box (LCH_ROOT) of the target clock domain, and this local path ends here.

[0091] 2. This GCW is not the GCW of the target clock domain. At this time, after crossing this GCW, you need to find other GCWs and cross the next GCW. Repeat this operation until you find the GCW corresponding to the target, and finally find the input port of the main local clock switch box (LCH_ROOT) of the target clock domain. In this process, the traversal operation will not search for paths with return. Please refer to Figure 6 The third local path may start from the input port of the GCW connected to the CMT, reach the output port of a GCW, and finally reach the input port of the master local clock switch box (LCH_ROOT) of the target clock domain. It is necessary to ensure that there is no return in this path.

[0092] Since a GCW will connect all the surrounding GCWs, in traditional wiring, the process of finding another GCW from a GCW will inevitably turn around. In order to avoid this situation, traditional wiring must judge the relationship between each point and the path when traversing each point to exclude the turning points, and such judgment will consume a lot of time. The wiring resource generation method proposed in the embodiment of the present invention generates wiring resources based on the path, and the path of the generated wiring resources does not turn around, so it is not easy to obtain the turning path in the subsequent wiring process, thereby saving a lot of time and improving the wiring speed.

[0093] Step S4013, obtaining a fourth local path with the main local clock switch box (LCH_ROOT) as the starting point and the switch box as the end point;

[0094] One LCH_ROOT will connect to several LCH_LEAFs, and one LCH_LEAF will connect to several SWHs. Therefore, one LCH_ROOT can manage many SWHs, and the area where these SWHs are located is a clock domain. In other words, one LCH_ROOT can manage several LCH_LEAFs, and then manage more SWHs, thereby managing an entire clock domain.

[0095] Specifically, for a master local clock switch box (LCH_ROOT), all its input ports can be used as the starting point, and then for each input port, traversal is performed until all input ports of all SWHs in the same clock domain are traversed, so that all fourth local paths with the master local clock switch box (LCH_ROOT) as the starting point can be obtained.

[0096] Wherein, obtaining a fourth local path with the main local clock switch box (LCH_ROOT) as a starting point and the switch box as an end point includes:

[0097] Determine whether the paths connecting the sub-local clock switch boxes and switch boxes of different main local clock switch boxes (LCH_ROOT) are consistent;

[0098] If they are consistent, the fourth local path is obtained only for one main local clock switch box (LCH_ROOT); and the general wiring resources are generated when the wiring resources are generated based on the fourth local path.

[0099] If they are inconsistent, the fourth local path is obtained for each main local clock switch box (LCH_ROOT).

[0100] Generally, LCH_ROOT, LCH_LEAF, switch box and the connection relationship between them are the same, so it is only necessary to extract the wiring resources for one LCH_ROOT and several LCH_LEAFs and switch boxes connected to it, which greatly reduces the memory space required for wiring resource storage.

[0101] Step S4014, obtaining a fifth partial path with the switch box as a starting point and the logic component in the logic component group directly connected to the switch box as an end point.

[0102] When describing the paths in the above text, the granularity is mostly based on the functional unit block (Tile). The specific starting point and terminal can be the external input port or external output port of the functional unit block, which can be selected according to the actual situation.

[0103] It should be noted that the fifth local path, i.e., SWH->LOG, has the same routing resources as the non-clock domain routing. They all start from the input port of SWH, pass through SWH, and finally reach the input of a logic component in LOG. Therefore, this section can reuse the routing resources of the non-clock domain routing without having to be generated repeatedly.

[0104] In some other optional specific implementations, obtaining multiple local paths includes:

[0105] For the clock management module (CMT), a first partial path is obtained with the input-output functional unit block connected to the clock management module (CMT) as a starting point and the global clock switch box (GCW) connected to the clock management module (CMT) as an end point, and a second partial path is obtained with the clock management module (CMT) as a starting point and the global clock switch box connected to the clock management module (CMT) as an end point;

[0106] Acquire a sixth partial path with the first global clock switch box (GCW) as a starting point and the second global clock switch box as an end point; wherein the second global clock switch box is a global clock switch box other than the first global clock switch box (GCW);

[0107] That is, the first global clock switch box, one or more global clock switch boxes in the middle, and the second global clock switch box are connected to form a sixth local path. Specifically, all input ports of the GCW connected to the CMT can be traversed, and these ports are used as the starting points of the path. These starting points are traversed to eventually find all paths with the output ports of the GCW as the end points. It should be noted that turning back is not allowed during the traversal process.

[0108] A seventh local path is obtained by taking the global clock switch box as a starting point, passing through the main local clock switch box (LCH_ROOT) directly connected to the global clock switch box, and then passing through the sub-local clock switch box, with the switch box as the end point;

[0109] A fifth partial path is obtained, which has the switch box as a starting point and a logic component in the logic component group directly connected to the switch box as an end point.

[0110] In some optional specific implementations, for a clock management module (CMT), obtaining a first local path with an input / output functional unit block connected to the clock management module (CMT) as a starting point and a global clock switch box (GCW) connected to the clock management module (CMT) as an end point, and obtaining a second local path with the clock management module (CMT) as a starting point and a global clock switch box connected to the clock management module (CMT) as an end point includes:

[0111] In the case where the chip includes multiple clock management modules, determining whether the paths connecting the input and output functional unit blocks and the global clock switch box of different clock management modules are consistent;

[0112] If they are consistent, the first partial path and the second partial path are obtained for only one clock management module; when routing resources are generated based on the first partial path and the second partial path, universal routing resources are generated.

[0113] If they are inconsistent, the first partial path and the second partial path are obtained for the clock management module respectively. Of course, if the paths connecting the input and output functional unit blocks and the global clock switch box of some clock management modules are consistent, then for these clock management modules, only the first partial path and the second partial path need to be obtained for one of the clock management modules.

[0114] For a clock management module (CMT), the connection relationship of each input and output functional unit block (IO) connected to it is different. Therefore, for a CMT and its corresponding IOs, it is impossible to reuse the wiring resources starting from IO by translation. Therefore, the embodiment of the present invention will traverse all IOs connected to this CMT to find the port that can be used as the starting point, that is, the output port of all logic components. With this output port as the starting point, all paths ending at the input port of GCW are found through traversal search method.

[0115] However, when the chip is large, there may be multiple CMTs. At this time, the paths between each CMT and its connected IO and GCW may be the same. At this time, it is only necessary to generate the routing resources of the first partial path and the second partial path for one CMT. When in use, if other CMT-related paths are needed, they can be reused by shifting the routing resources.

[0116] Generate general wiring resources, and greatly reduce the memory space required for wiring resource storage while meeting wiring requirements (specifically, this can be done through translation).

[0117] In other optional specific implementations, the first local path is IO->CMT->GCW or CMT->GCW, the second local path is GCW->GCW, the third local path is GCW->LCH_ROOT, the fourth local path is LCH_ROOT->LCH_LEAF, and the fifth local path is LCH_LEAF->SWH->LOG Tile->Logic Components. The fifth local path can also be split into two local paths: LCH_LEAF->SWH and SWH->LOG Tile->Logic Components. IO->CMT->GCW in the first local path can also be split into two local paths: IO->CMT and CMT->GCW.

[0118] In this embodiment, a chip clock domain routing method is provided, which can be used in a computer device on which an FPGA design tool can be run. Figure 7 is a flow chart of a chip clock domain wiring method according to an embodiment of the present invention. Figure 7 As shown, the process includes the following steps:

[0119] Step S701, obtaining wiring resources, where the wiring resources are generated according to the generation method provided in the above embodiment;

[0120] Step S702, obtaining the routing start point and routing end point; for routing on the clock domain, the starting point must be the output of a logic component in the input / output functional unit block (IO Tile) or the clock management module (CMT), and the end point must be the input of a logic component on the logic component group (LOG Tile).

[0121] Step S703, selecting a plurality of wiring resources from the wiring resources that can connect the wiring start point and the wiring end point by splicing;

[0122] Step S704, completing routing using the selected routing resources.

[0123] The chip clock domain wiring method provided in this embodiment obtains pre-generated wiring resources. The wiring obtains multiple local paths in advance when it is generated, and the principle of obtaining these local paths is to ensure that any complete clock signal transmission path can be spliced ​​by some of the local paths. This means that the segmented local paths are obtained in advance when the wiring resources are generated, and each local path spans at least one functional unit block. Then, when the wiring path is subsequently wired, it is not necessary to select one component at a time like traditional wiring, but to select one path at a time. Selecting one component at a time may require thousands of times or even more, while selecting one path at a time has a limited number of selections, and generally only a few selections are required to splice a complete clock signal transmission path. Therefore, when wiring a clock domain with a high fan-out, the number of invalid selections is greatly reduced, the speed of selecting a wiring path is greatly improved, and the memory required for wiring is also reduced.

[0124] In some optional specific implementations, multiple wiring resources that can connect a wiring start point and a wiring end point by splicing are selected from wiring resources, including:

[0125] The wiring resources corresponding to the first partial path or the second partial path are selected from the wiring resources according to the wiring starting point, the starting point of the first partial path is the input-output functional unit block and the end point is the global clock switch box, the starting point of the second partial path is the clock management module and the end point is the global clock switch box; the wiring starting point is the output of a logic component in the input-output functional unit block (IOTile) or the clock management module (CMT), the starting point of the first partial path is the input-output functional unit block, and the starting point of the second partial path is the clock management module.

[0126] According to the end point of the wiring resources corresponding to the selected first local path or the second local path, the wiring resources corresponding to the third local path are selected from the wiring resources, the starting point of the third local path is the global clock switch box, and the end point is the main local clock switch box; here, the end point of the first local path or the second local path and the starting point of the third local path are the same input port of the same global clock switch box.

[0127] According to the end point of the wiring resource corresponding to the selected third local path, the wiring resource corresponding to the fourth local path is selected from the wiring resources, the starting point of the fourth local path is the main local clock switch box, and the end point is the switch box; here, the end point of the third local path and the starting point of the fourth local path are the same input port of the same main local clock switch box.

[0128] According to the end point of the wiring resource corresponding to the selected fourth partial path and the wiring end point, a wiring resource corresponding to the fifth partial path is selected from the wiring resources, and the starting point of the fifth partial path is the switch box and the end point is the logic component in the logic component group. The end point of the fourth partial path and the starting point of the fifth partial path are the same switch box, and are generally the same input port. The wiring end point and the end point of the fifth partial path are the same input of the same logic component in the same logic component group.

[0129] For the case where the wiring resources are generated based on the first local path, the second local path, the sixth local path, the seventh local path and the fifth local path, the selection of wiring resources is similar to the above. The wiring resources corresponding to the first local path or the second local path are selected according to the wiring starting point, and then the wiring resources corresponding to the sixth local path whose starting point is consistent with the end point of the selected wiring resources are selected, and then the wiring resources corresponding to the seventh local path whose starting point is consistent with the end point of the most recently selected wiring resource are selected, and finally, the wiring resources corresponding to the fifth local path whose starting point is consistent with the end point of the most recently selected wiring resource and whose end point is consistent with the wiring end point are selected.

[0130] Specifically, assume that the wiring start point is S and the wiring end point is E.

[0131] First, among the wiring resources corresponding to the first partial path or the wiring resources corresponding to the second partial path, all wiring resources starting from S are selected, and this group of wiring resources is called "the first group of wiring resources". It should be noted that when saving wiring resources, not only can the wiring resources indexed by the two points "starting point and end point" be saved, but also another wiring resource indexed by the "starting point" can be saved separately, so that all wiring resources starting from this point can be directly found according to the starting point without traversing the wiring resources.

[0132] If the FPGA chip has multiple clock management modules (CMTs), then this section of routing resources may need to be shifted. Check whether the coordinates of S in the chip are consistent with the coordinates of the starting point in the routing resources. If they are not consistent, then shift all routing resources in the first group of routing resources to the position of S. At this point, the first section of the path is found.

[0133] Traverse the first group of routing resources and collect all the end points of this group of routing resources. Assume that these end points are: point 00, point 01, ..., point 0n. Take these points as the starting point and select all the second segment routing resources starting from these points. These routing resources are referred to as "superset of the second group of routing resources" hereinafter.

[0134] The routing resources in the "superset of the second group of routing resources" can definitely be spliced ​​with some routing resources in the "first group of routing resources" (because the starting point of some routing resources in the first group of routing resources is the end point of some routing resources in the superset of the second group of routing resources). At the same time, the end point of this section of routing resources is the GCW, and this GCW determines which clock domains this section of routing resources can reach. From the "superset of the second group of routing resources", select the routing resources that can reach the target clock domain, and these routing resources are the "second group of routing resources".

[0135] Similar to the first group of routing resources, these routing resources also need to be moved to the appropriate locations.

[0136] Similarly, collect all the endpoints of "Group 2 wiring resources", use these points as the starting point, find "Segment 3 wiring resources" and translate. Finally, use endpoint E as the end point, and take out the wiring resources with end point E from the non-clock domain wiring resources and translate.

[0137] In this way, all the required 4 sections of routing resources are obtained, and each section has several qualified routing resources. These 4 sections of routing resources are spliced ​​together to form a complete path from the starting point S to the end point E. From these complete paths, the best path is selected to complete a clock domain routing.

[0138] For other routing resources generated using different local path division methods, the routing method is similar. Starting from the routing starting point, several routing resources are selected in turn to connect to the routing end point. It will not be repeated here.

[0139] In some optional specific implementations, the selected routing resources are used to complete routing, including:

[0140] Determine whether the selected wiring resource is a universal wiring resource; when generating wiring resources, if the starting points and end points of multiple local paths are at different positions in the chip, but the functional unit block structures to which the starting points and end points belong are the same and the functional unit block structures passed through are the same, then only one universal wiring resource is generated;

[0141] Specifically for ports and components, when generating routing resources, only one common resource will be generated when two paths meet the following conditions: the absolute positions of the starting point and the end point in the chip are different, but the functional unit block structures to which the starting point and the end point belong are the same, the functional unit block structures passed in the middle are the same, and the ports at the starting point and the end point, as well as the components and ports passed in the middle, have the same number in the functional unit blocks to which they belong.

[0142] If so, the general wiring resources are moved to the chip location where the wiring resources are needed.

[0143] As mentioned above, if the FPGA chip has multiple clock management modules (CMTs), then only one of the clock management modules (CMTs) may generate routing resources corresponding to the first local path and the second local path. This is the general routing resource, which may need to be shifted during routing. Specifically, it can be determined by judging whether the positions of the starting point and the end point of the routing resource on the chip are consistent with the positions required for routing. If they are consistent, no translation is required, and if they are inconsistent, translation is required. The same is true for other routing resources. For example, the routing resources corresponding to the fourth local path, the routing resources corresponding to the fifth local path, and other routing resources may generate general routing resources.

[0144] In addition, in some specific implementations, when selecting multiple wiring resources from the wiring resources that can be connected to the wiring starting point and the wiring end point through splicing, there may be more than one combination of multiple wiring resources that can be connected to the wiring starting point and the wiring end point through splicing, that is, there are multiple different wiring resource combinations that can achieve the connection between the wiring starting point and the wiring end point through splicing.

[0145] In the embodiment of the present invention, when selecting wiring resources for wiring, since the selection can be made one path at a time, generally only a few selections are needed to realize the connection between the wiring start point and the wiring end point through splicing, and the time required is greatly reduced. Therefore, it does not take a lot of time to find all the wiring resource combinations that can connect the wiring start point and the wiring end point through splicing, or at least a plurality of such wiring resource combinations can be found. Therefore, when the clock domain is wired, these wiring resource combinations can be evaluated according to a preset evaluation method to obtain evaluation results, and then the optimal wiring resource combination can be selected for wiring, thereby improving the wiring quality, reducing conflicts, and improving the routing rate.

[0146] In this embodiment, a device for generating chip clock domain wiring resources is also provided, which is used to implement the above embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware for a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0147] This embodiment provides a device for generating chip clock domain wiring resources, such as Figure 8 As shown, including:

[0148] The local path acquisition module 801 is used to acquire multiple local paths. Any complete clock signal transmission path on the chip can be obtained by combining some of the local paths in the multiple local paths. Each local path spans at least one functional unit block.

[0149] The generating module 802 is used to generate routing resources for each local path.

[0150] In some optional implementations, the local path acquisition module 801 includes:

[0151] A first path acquisition unit is used to acquire, for the clock management module, a first partial path having an input / output functional unit block connected to the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, and to acquire a second partial path having the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point;

[0152] A third path acquisition unit, used to acquire a third local path with the global clock switch box as a starting point and the main local clock switch box as an end point;

[0153] A fourth path acquisition unit, used to acquire a fourth local path with the main local clock switch box as a starting point and the switch box as an end point;

[0154] The fifth path acquisition unit is used to acquire a fifth partial path with the switch box as a starting point and the logic component in the logic component group directly connected to the switch box as an end point.

[0155] In some optional implementations, the fourth path acquisition unit includes:

[0156] The first judgment subunit is used to judge whether the paths connecting the auxiliary local clock switch boxes and the switch boxes of different main local clock switch boxes are consistent;

[0157] The first local path acquisition subunit is used for different main local clock switch boxes. When the paths connecting the sub-local clock switch boxes and the switch boxes are consistent, the fourth local path is only acquired for one main local clock switch box; when the paths connecting the sub-local clock switch boxes and the switch boxes are inconsistent for different main local clock switch boxes, the fourth local paths are respectively acquired for the main local clock switch boxes.

[0158] In some optional implementations, the local path acquisition module 801 includes:

[0159] A first path acquisition unit is used to acquire, for the clock management module, a first partial path having an input / output functional unit block connected to the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, and to acquire a second partial path having the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point;

[0160] A sixth path acquisition unit, configured to acquire a sixth partial path with the first global clock switch box as a starting point and the second global clock switch box as an end point; wherein the second global clock switch box is a global clock switch box other than the first global clock switch box;

[0161] a seventh path acquisition unit, for acquiring a seventh local path having the global clock switch box as a starting point, passing through a primary local clock switch box directly connected to the global clock switch box, and then passing through a secondary local clock switch box, with the switch box as a terminal;

[0162] The fifth path acquisition unit is used to acquire a fifth partial path with the switch box as a starting point and the logic component in the logic component group directly connected to the switch box as an end point.

[0163] In some optional implementations, the first path acquisition unit includes:

[0164] A second judgment subunit is used to judge whether the paths connecting the input and output functional unit blocks and the global clock switch box of different clock management modules are consistent when the chip includes multiple clock management modules;

[0165] The second local path acquisition sub-unit is used for different clock management modules. When the paths connecting the input-output functional unit block and the global clock switch box are consistent, the first local path and the second local path are only acquired for one clock management module; when different clock management modules have inconsistent paths connecting the input-output functional unit block and the global clock switch box, the first local path and the second local path are acquired for each clock management module.

[0166] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0167] The chip clock domain wiring resource generation device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0168] In this embodiment, a chip clock domain wiring device is also provided, which is used to implement the above-mentioned embodiments and preferred implementation modes, and the descriptions that have been made will not be repeated. As used below, the term "module" can implement a combination of software and / or hardware of a predetermined function. Although the devices described in the following embodiments are preferably implemented in software, the implementation of hardware, or a combination of software and hardware, is also possible and conceivable.

[0169] This embodiment provides a chip clock domain wiring device, such as Fig. 9 As shown, including:

[0170] A wiring resource acquisition module 901 is used to acquire wiring resources, where the wiring resources are generated according to any of the chip clock domain wiring resource generation methods described in the above embodiments;

[0171] The wiring requirement acquisition module 902 is used to obtain the wiring start point and the wiring end point;

[0172] A selection module 903 is used to select a plurality of wiring resources from the wiring resources that can connect the wiring start point and the wiring end point through splicing;

[0173] The routing module 904 is used to complete routing using the selected routing resources.

[0174] In some optional implementations, the selection module 903 includes:

[0175] A first selection unit is used to select a wiring resource corresponding to a first partial path or a second partial path from the wiring resources according to a wiring starting point, wherein the starting point of the first partial path is the input / output functional unit block and the end point is the global clock switch box, and the starting point of the second partial path is the clock management module and the end point is the global clock switch box;

[0176] A second selection unit is used to select a wiring resource corresponding to a third local path from the wiring resources according to an end point of the wiring resource corresponding to the selected first local path or the second local path, wherein the starting point of the third local path is the global clock switch box and the end point is the main local clock switch box;

[0177] A third selection unit is used to select a wiring resource corresponding to a fourth local path from the wiring resources according to an end point of the wiring resource corresponding to the selected third local path, wherein the starting point of the fourth local path is the main local clock switch box and the end point is the switch box;

[0178] The fourth selection unit is used to select the wiring resources corresponding to the fifth partial path from the wiring resources according to the end point and the wiring end point of the wiring resources corresponding to the selected fourth partial path, wherein the starting point of the fifth partial path is the switch box and the end point is the logic component in the logic component group.

[0179] In some optional implementations, the wiring module 904 includes:

[0180] A judgment unit, used to judge whether the selected wiring resource is a universal wiring resource; when generating wiring resources, if the starting points and end points of multiple local paths are at different positions in the chip, but the functional unit block structures to which the starting points and end points belong are the same and the functional unit block structures passed through are the same, only one universal wiring resource is generated;

[0181] The translation unit is used to translate the general wiring resource to the chip position where the wiring resource is needed when the wiring resource is a general wiring resource.

[0182] The further functional description of each of the above modules and units is the same as that of the above corresponding embodiments and will not be repeated here.

[0183] The chip clock domain wiring device in this embodiment is presented in the form of a functional unit, where the unit refers to an ASIC (Application Specific Integrated Circuit) circuit, a processor and memory that executes one or more software or fixed programs, and / or other devices that can provide the above functions.

[0184] The embodiment of the present invention also provides a computer device having the above Figure 8 The chip clock domain wiring resource generation device shown and / or the above Fig. 9 The chip clock domain routing device is shown.

[0185] See also Fig.10 , Fig.10 is a schematic diagram of the structure of a computer device provided by an optional embodiment of the present invention, such as Fig.10As shown, the computer device includes: one or more processors 10, a memory 20, and interfaces for connecting various components, including high-speed interfaces and low-speed interfaces. Various components are connected to each other using different buses for communication, and can be installed on a common mainboard or installed in other ways as needed. The processor can process the instructions executed in the computer device, including instructions stored in or on the memory to display the graphical information of the GUI on an external input / output device (such as, a display device coupled to the interface). In some optional embodiments, if necessary, multiple processors and / or multiple buses can be used together with multiple memories and multiple memories. Similarly, multiple computer devices can be connected, and each device provides some necessary operations (for example, as a server array, a group of blade servers, or a multi-processor system). Fig.10 A processor 10 is taken as an example.

[0186] The processor 10 may be a central processing unit, a network processor or a combination thereof. The processor 10 may further include a hardware chip. The hardware chip may be a dedicated integrated circuit, a programmable logic device or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general purpose array logic or any combination thereof.

[0187] The memory 20 stores instructions executable by at least one processor 10, so that at least one processor 10 executes the method shown in the above embodiment.

[0188] The memory 20 may include a program storage area and a data storage area, wherein the program storage area may store an operating system, an application required for at least one function; the data storage area may store data created according to the use of the computer device, etc. In addition, the memory 20 may include a high-speed random access memory, and may also include a non-transient memory, such as at least one disk storage device, a flash memory device, or other non-transient solid-state storage device. In some optional embodiments, the memory 20 may optionally include a memory remotely arranged relative to the processor 10, and these remote memories may be connected to the computer device via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0189] The memory 20 may include a volatile memory, such as a random access memory; the memory may also include a non-volatile memory, such as a flash memory, a hard disk or a solid state drive; the memory 20 may also include a combination of the above types of memory.

[0190] The computer device also includes an input device 30 and an output device 40. The processor 10, the memory 20, the input device 30 and the output device 40 may be connected via a bus or other means. Fig.10 The example of connecting through bus is taken in the following.

[0191] The input device 30 can receive input digital or character information, and generate key signal input related to the user settings and function control of the computer device, such as a touch screen, a keypad, a mouse, a track pad, a touch pad, an indicator bar, one or more mouse buttons, a trackball, a joystick, etc. The output device 40 may include a display device, an auxiliary lighting device (e.g., an LED) and a tactile feedback device (e.g., a vibration motor), etc. The above-mentioned display device includes but is not limited to a liquid crystal display, a light emitting diode, a display and a plasma display. In some optional embodiments, the display device can be a touch screen.

[0192] The computer device also includes a communication interface, which is used for the computer device to communicate with other devices or a communication network.

[0193] The embodiment of the present invention also provides a computer-readable storage medium. The method according to the embodiment of the present invention can be implemented in hardware, firmware, or can be implemented as a computer code that can be recorded in a storage medium, or can be implemented as a computer code that is originally stored in a remote storage medium or a non-temporary machine-readable storage medium and will be stored in a local storage medium through a network download, so that the method described herein can be stored in such software processing on a storage medium using a general-purpose computer, a dedicated processor, or programmable or dedicated hardware. Among them, the storage medium can be a magnetic disk, an optical disk, a read-only storage memory, a random access memory, a flash memory, a hard disk or a solid-state hard disk, etc.; further, the storage medium can also include a combination of the above types of memories. It can be understood that a computer, a processor, a microprocessor controller, or programmable hardware includes a storage component that can store or receive software or computer code. When the software or computer code is accessed and executed by a computer, a processor, or hardware, the method shown in the above embodiment is implemented.

[0194] Although the embodiments of the present invention have been described in conjunction with the accompanying drawings, those skilled in the art may make various modifications and variations without departing from the spirit and scope of the present invention, and such modifications and variations are all within the scope defined by the appended claims.

Claims

1. A method for generating chip clock domain wiring resources, characterized in that: The method comprises: Acquire multiple partial paths, where any complete clock signal transmission path on the chip can be obtained by combining some of the partial paths among the multiple partial paths, and each of the partial paths spans at least one functional unit block; generating a routing resource for each of the local paths; The obtaining of multiple local paths includes: For a clock management module, a first partial path is obtained with an input / output functional unit block connected to the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, and a second partial path is obtained with the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point; Obtain a third local path having the global clock switch box as a starting point and the main local clock switch box as an end point; Acquire a fourth local path with the master local clock switch box as a starting point and the switch box as an end point; A fifth partial path is obtained, which has the switch box as a starting point and a logic component in a logic component group directly connected to the switch box as an end point.

2. The method according to claim 1, characterized in that The step of obtaining a fourth local path with the main local clock switch box as a starting point and the switch box as an end point comprises: Determine whether the paths connecting the different master local clock switch boxes to the slave local clock switch boxes and the switch boxes are consistent; If they are consistent, obtaining the fourth local path for only one of the master local clock switch boxes; If they are inconsistent, the fourth local path is obtained for each of the master local clock switch boxes.

3. The method according to claim 1, characterized in that The obtaining of multiple local paths includes: For a clock management module, a first partial path is obtained with an input / output functional unit block connected to the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, and a second partial path is obtained with the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point; Acquire a sixth partial path with the first global clock switch box as a starting point and the second global clock switch box as an end point; wherein the second global clock switch box is a global clock switch box other than the first global clock switch box; A seventh local path is obtained by taking the global clock switch box as a starting point, passing through a main local clock switch box directly connected to the global clock switch box, and then passing through a secondary local clock switch box, with the switch box as an end point; A fifth partial path is obtained, which has the switch box as a starting point and a logic component in a logic component group directly connected to the switch box as an end point.

4. The method according to any one of claims 1 to 3, characterized in that For the clock management module, obtaining a first partial path with an input / output functional unit block connected to the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, and obtaining a second partial path with the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, includes: In the case where the chip includes multiple clock management modules, determining whether the paths connecting the input and output functional unit blocks and the global clock switch box of different clock management modules are consistent; If they are consistent, obtaining the first partial path and the second partial path for only one clock management module; If they are inconsistent, the first partial path and the second partial path are acquired for the clock management module respectively.

5. A chip clock domain wiring method, characterized in that: The method comprises: Acquire wiring resources, where the wiring resources are generated according to the generation method described in any one of claims 1 to 4; Get the wiring start point and wiring end point; Selecting a plurality of the wiring resources from the wiring resources that can connect the wiring start point and the wiring end point by splicing; Routing is completed using the selected routing resources.

6. The method according to claim 5, characterized in that The selecting, from the wiring resources, a plurality of wiring resources capable of connecting the wiring start point and the wiring end point through splicing, comprises: Selecting a wiring resource corresponding to a first partial path or a second partial path from the wiring resources according to the wiring starting point, wherein the starting point of the first partial path is an input / output functional unit block and the end point is a global clock switch box, and the starting point of the second partial path is a clock management module and the end point is a global clock switch box; According to the selected end point of the wiring resource corresponding to the first local path or the second local path, a wiring resource corresponding to a third local path is selected from the wiring resources, wherein the starting point of the third local path is the global clock switch box and the end point is the main local clock switch box; According to the end point of the selected wiring resource corresponding to the third local path, a wiring resource corresponding to a fourth local path is selected from the wiring resources, wherein the starting point of the fourth local path is the main local clock switch box and the end point is the switch box; According to the end point of the selected wiring resource corresponding to the fourth partial path and the wiring end point, a wiring resource corresponding to a fifth partial path is selected from the wiring resources, wherein the starting point of the fifth partial path is the switch box and the end point is the logic component in the logic component group.

7. The method according to claim 5 or 6, characterized in that: The using the selected routing resources to complete routing includes: Determine whether the selected wiring resource is a universal wiring resource; when generating wiring resources, if the starting points and end points of multiple local paths are at different positions in the chip, but the functional unit block structures to which the starting points and end points belong are the same and the functional unit block structures passed through are the same, then only one universal wiring resource is generated; If so, the general wiring resource is moved to the chip position where the wiring resource is needed.

8. A device for generating chip clock domain wiring resources, characterized in that: The device comprises: A local path acquisition module, used to acquire multiple local paths, any complete clock signal transmission path on the chip can be obtained by combining some of the local paths in the multiple local paths, and each of the local paths spans at least one functional unit block; A generating module, used for generating routing resources for each of the local paths; Wherein, the local path acquisition module includes: A first path acquisition unit is used to acquire, for a clock management module, a first partial path having an input / output functional unit block connected to the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point, and to acquire a second partial path having the clock management module as a starting point and a global clock switch box connected to the clock management module as an end point; A third path acquisition unit, used to acquire a third local path with the global clock switch box as a starting point and the main local clock switch box as an end point; A fourth path acquisition unit, used to acquire a fourth local path with the master local clock switch box as a starting point and the switch box as an end point; The fifth path acquisition unit is used to acquire a fifth partial path with the switch box as a starting point and a logic component in a logic component group directly connected to the switch box as an end point.

9. A chip clock domain wiring device, characterized in that: The device comprises: A wiring resource acquisition module, used to acquire wiring resources, wherein the wiring resources are generated according to the generation method according to any one of claims 1 to 4; A wiring requirement acquisition module is used to obtain the wiring starting point and wiring end point; A selection module, configured to select, from the wiring resources, a plurality of wiring resources capable of connecting the wiring start point and the wiring end point through splicing; A routing module is used to complete routing using the selected routing resources.

10. A computer device, characterized in that: include: A memory and a processor, wherein the memory and the processor are communicatively connected to each other, the memory stores computer instructions, and the processor executes the chip clock domain routing resource generation method described in any one of claims 1 to 4, or executes the chip clock domain routing method described in any one of claims 5 to 7 by executing the computer instructions.

11. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores computer instructions, and the computer instructions are used to enable a computer to execute the method for generating chip clock domain wiring resources according to any one of claims 1 to 4, or to execute the chip clock domain wiring method according to any one of claims 5 to 7.

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