A GaN intelligent power chip with over-temperature protection capability and a preparation method thereof

Abstract

The present invention relates to a GaN intelligent power chip with over-temperature protection capability and a preparation method thereof. The GaN intelligent power chip comprises: a two-dimensional electron gas structure, a first isolation groove, a second isolation groove, a cathode, an anode, a first ohmic contact electrode, a second ohmic contact electrode and a plurality of power device electrodes; the first isolation groove and the second isolation groove are arranged in the two-dimensional electron gas structure to isolate the two-dimensional electron gas channel in the two-dimensional electron gas structure to form a power device area, an ohmic contact resistance area and a diode temperature sensor area; the cathode and the anode are arranged in the diode temperature sensor area at intervals; the first ohmic contact electrode and the second ohmic contact electrode are arranged in the ohmic contact resistance area at intervals; a plurality of power device electrodes are distributed in the power device area; the cathode, the second ohmic contact electrode and the voltage control electrodes in the plurality of power device electrodes are connected in parallel. The GaN intelligent power chip can quickly sense the junction temperature of a HEMT device and protect the device in time.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor intelligent power modules, and in particular relates to a GaN intelligent power chip with over-temperature protection capability and a preparation method thereof. Background Art

[0002] In recent years, GaN materials have attracted extensive attention and applications in the field of power electronics due to their advantages such as large bandgap, high breakdown electric field, fast response speed, radiation resistance and high temperature resistance. High electron mobility transistor (HEMT) devices made of them have gradually become the first choice in high-frequency and high-power applications due to their excellent switching characteristics and voltage resistance. GaN-based HEMT devices are core devices for high-frequency power conversion applications. In recent years, they have been widely used in fast chargers, electric vehicles, space radars and other fields. However, new applications have higher reliability requirements for GaN-based HEMT devices, and the reliability problems caused by device degradation cannot be ignored. The most common is the impact of long-term high operating temperature on the performance of GaN-based HEMT devices. When HEMT devices are working, frequent switching conversions will cause the heterojunction temperature to rise rapidly, and the carrier mobility of the two-dimensional electron gas (2DEG) channel will deteriorate due to the influence of temperature. Long-term operation at high temperatures may cause device degradation and reduced life, and serious safety problems.

[0003] In order to reduce or avoid device failures caused by high temperatures, in practical applications, a feedback protection circuit can be designed through board-level circuits to prevent GaN-based power devices from having reliability problems due to excessive temperatures. However, this method has several disadvantages: 1. Slow response speed, unable to immediately shut down when the HEMT temperature rises; 2. Low integration, high design and production costs, large board-level circuit size, which does not conform to the design trend of power chips; 3. Additional power consumption and a series of parasitic crosstalk will be generated, which is not conducive to efficient operation of power modules and energy conservation. Summary of the invention

[0004] In order to solve the above problems existing in the prior art, the present invention provides a GaN smart power chip with over-temperature protection capability and a preparation method thereof. The technical problem to be solved by the present invention is achieved through the following technical solutions:

[0005] The embodiment of the present invention provides a GaN smart power chip with over-temperature protection capability, comprising: a two-dimensional electron gas structure, a first isolation groove, a second isolation groove, a cathode, an anode, a first ohmic contact electrode, a second ohmic contact electrode and a plurality of power device electrodes, wherein:

[0006] The first isolation groove and the second isolation groove are arranged in the two-dimensional electron gas structure to isolate the two-dimensional electron gas channel in the two-dimensional electron gas structure, so that the two-dimensional electron gas structure forms a power device region, an ohmic contact resistance region and a diode temperature sensor region which are arranged in sequence laterally;

[0007] The cathode and the anode are arranged at intervals in the diode temperature sensor region and are located above the two-dimensional electron gas channel; the first ohmic contact electrode and the second ohmic contact electrode are arranged at intervals in the ohmic contact resistance region and are located above the two-dimensional electron gas channel; the plurality of power device electrodes are distributed in the power device region and are located above the two-dimensional electron gas channel;

[0008] The anode is used to input power supply voltage; the cathode is connected to the second ohmic contact electrode through an interconnecting metal wire, and the interconnected electrode is connected to the voltage control electrode in the plurality of power device electrodes through an interconnecting metal wire; the first ohmic contact electrode is used for grounding.

[0009] In one embodiment of the present invention, the two-dimensional electron gas structure includes a substrate, a nucleation layer, a buffer layer, a channel layer and a barrier layer stacked in sequence from bottom to top, wherein:

[0010] The channel layer and the barrier layer form a two-dimensional electron gas channel.

[0011] In one embodiment of the present invention, both the first isolation groove and the second isolation groove extend to the surface of the buffer layer;

[0012] The first ohmic contact electrode, the second ohmic contact electrode, and the cathode all extend to the surface of the channel layer;

[0013] The anode is located on the surface of the barrier layer.

[0014] In one embodiment of the present invention, the power device comprises a HEMT power device, and accordingly, the plurality of power device electrodes comprises a source electrode, a drain electrode and a gate electrode, wherein:

[0015] The source electrode, the gate electrode and the drain electrode are sequentially arranged in intervals in the power device region;

[0016] The gate electrode, the cathode, and the second ohmic contact electrode are connected in parallel through the interconnection metal line.

[0017] In one embodiment of the present invention, the source electrode and the drain electrode both extend to the surface of the channel layer;

[0018] The gate electrode is located on the surface of the barrier layer.

[0019] In one embodiment of the present invention, a partial P-type GaN layer is also included, wherein:

[0020] The portion of the P-type GaN layer is located on the surface of the barrier layer between the source electrode and the drain electrode, and the gate electrode is located on the portion of the P-type GaN layer.

[0021] In one embodiment of the present invention, a passivation layer is further included, wherein:

[0022] The passivation layer covers a surface of the first isolation groove, a surface of the second isolation groove, a surface of the barrier layer, and a portion of the surface of the portion of the P-type GaN layer;

[0023] The anode overlaps the passivation layer.

[0024] In one embodiment of the present invention, the cathode material is ohmic metal, including one or more of Ti, Al, Ni, and Au;

[0025] The material of the anode is Schottky metal, including one or more of TiN, Ti, and Al;

[0026] The materials of the first ohmic contact electrode and the second ohmic contact electrode both include one or more of Ti, Al, Ni, and Au;

[0027] The source electrode and the drain electrode are made of ohmic metal, including one or more of Ti, Al, Ni, and Au;

[0028] The gate electrode is made of Schottky metal, including one or more of TiN, Ti, and Al;

[0029] The material of the interconnection metal line includes Cu;

[0030] The material of the part of the P-type GaN layer includes Mg + Ion-doped GaN, hole doping concentration is 10 17 -10 18 cm -3 , thickness is 60-80nm;

[0031] The material of the passivation layer includes Si3N4, and the thickness is 100-150nm.

[0032] Another embodiment of the present invention provides a method for preparing a GaN smart power chip with over-temperature protection capability, comprising the steps of:

[0033] S1. Preparation of two-dimensional electron gas structure;

[0034] S2, etching the two-dimensional electron gas structure to below the two-dimensional electron gas channel to form a first isolation groove and a second isolation groove, so as to isolate the two-dimensional electron gas structure into a power device region, an ohmic contact resistance region, and a diode temperature sensor region which are sequentially arranged laterally;

[0035] S3, depositing a passivation layer on the surface of the two-dimensional electron gas structure, the surface of the first isolation groove and the surface of the second isolation groove;

[0036] S4, preparing a metal electrode above the two-dimensional electron gas channel of the two-dimensional electron gas structure to form a cathode and an anode spaced apart in the diode temperature sensor region, a first ohmic contact electrode and a second ohmic contact electrode spaced apart in the ohmic contact resistance region, and a plurality of power device electrodes distributed in the power device region, wherein the anode (5) is used to input a power supply voltage, and the first ohmic contact electrode (6) is used to be grounded;

[0037] S5. Use interconnecting metal wires to connect the cathode to the second ohmic contact electrode, and connect the connected electrode to a voltage control electrode among the plurality of power device electrodes.

[0038] In one embodiment of the present invention, step S4 includes:

[0039] S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer, and etching the passivation layer and the two-dimensional electron gas structure in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves;

[0040] S42, depositing ohmic metal in the plurality of ohmic metal electrode grooves and performing annealing to form a cathode disposed in the diode temperature sensor region, a first ohmic contact electrode and a second ohmic contact electrode disposed in the ohmic contact resistor region at intervals, and a plurality of ohmic metal electrodes distributed in the power device region;

[0041] S43, defining a plurality of Schottky metal electrode regions on the surface of the passivation layer, and etching the passivation layer in the Schottky metal electrode regions to form a plurality of Schottky metal electrode grooves;

[0042] S44, depositing Schottky metal in the plurality of Schottky metal electrode grooves to form an anode spaced apart from the cathode in the diode temperature sensor region and a Schottky electrode in the power device region.

[0043] Compared with the prior art, the present invention has the following beneficial effects:

[0044] The present invention arranges an anode, a cathode, a first ohmic contact electrode, a second ohmic contact electrode and a plurality of power device electrodes on a two-dimensional electron gas structure, and connects the cathode, the second ohmic contact electrode and a voltage control electrode of the power device in parallel. By utilizing the characteristic that the temperature rise rate of the temperature sensor diode is higher than the resistance temperature rise rate of the ohmic contact electrode, when the junction temperature is low, the voltage of the voltage control electrode in the power device is adjusted to be greater than the threshold voltage of the power device, so that the power device works normally. After the junction temperature rises to a critical temperature, the divided voltage of the second ohmic contact electrode, i.e., the voltage of the voltage control electrode, is pulled down to be less than the threshold voltage of the power device, thereby shutting down the device and stopping working, thereby protecting the power device. When the junction temperature drops below the critical temperature, the voltage of the voltage control electrode is pulled up to a value greater than the threshold voltage of the power device, the power device is turned on again, and the power chip resumes normal operation. Therefore, the GaN intelligent power chip integrates the power device with the ohmic contact electrode and the diode temperature sensor on the same epitaxial wafer. The temperature sensor can quickly sense the junction temperature of the HEMT device and respond quickly. The shutdown operation can be performed the instant the junction temperature is higher than the critical voltage, thereby protecting the device in time and preventing device damage caused by untimely temperature detection. Compared with traditional board-level integrated circuits, it has the advantages of low parasitic crosstalk, small chip size, high integration, low manufacturing cost, and low power loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0045] Figure 1 A schematic diagram of the three-dimensional structure of a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention;

[0046] Figure 2 A schematic diagram of a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention

[0047] Figure 3 A schematic flow chart of a method for preparing a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention;

[0048] Figure 4a-Figure 4i A schematic diagram of a process of preparing a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention. DETAILED DESCRIPTION

[0049] The present invention is further described in detail below with reference to specific embodiments, but the embodiments of the present invention are not limited thereto.

[0050] Embodiment 1

[0051] See also Figure 1 and Figure 2 , Figure 1A schematic diagram of the three-dimensional structure of a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention, Figure 2 A schematic front view of a GaN smart power chip with over-temperature protection capability provided in an embodiment of the present invention.

[0052] The GaN smart power chip of this embodiment realizes two functions, from left to right: 1. lateral power device, such as lateral power HEMT device; 2. over-temperature protection smart circuit part, including two ohmic contact resistors and GaN lateral diode temperature sensor. The GaN smart power chip specifically includes: two-dimensional electron gas structure 1, first isolation groove 2, second isolation groove 3, cathode 4, anode 5, first ohmic contact electrode 6, second ohmic contact electrode 7 and several power device electrodes. Among them, the first isolation groove 2 and the second isolation groove 3 are arranged in the two-dimensional electron gas structure 1 to isolate the two-dimensional electron gas channel in the two-dimensional electron gas structure 1, so that the two-dimensional electron gas structure 1 forms a power device area, an ohmic contact resistance area and a diode temperature sensor area which are arranged in sequence horizontally; the cathode 4 and the anode 5 are arranged in the diode temperature sensor area at intervals and are located above the two-dimensional electron gas channel; the first ohmic contact electrode 6 and the second ohmic contact electrode 7 are arranged in the ohmic contact resistance area at intervals and are located above the two-dimensional electron gas channel; a plurality of power device electrodes are distributed in the power device area and are located above the two-dimensional electron gas channel; the anode 5 is used to input the power supply voltage; the cathode 4 is connected to the second ohmic contact electrode 7 through an interconnecting metal wire, and the interconnected electrode is connected to the voltage control electrode in the plurality of power device electrodes through an interconnecting metal wire; the first ohmic contact electrode 6 is used for grounding.

[0053] Specifically, the bottoms of the first isolation groove 2 and the second isolation groove 3 extend to below the two-dimensional electron gas channel in the two-dimensional electron gas structure 1, isolating the two-dimensional electron gas channel, so that the two-dimensional electron gas structure 1 forms an electrically isolated power device region, an ohmic contact resistance region and a diode temperature sensor region, and these three regions are arranged horizontally in sequence.

[0054] Specifically, the cathode 4, the anode 5, the first ohmic contact electrode 6, the second ohmic contact electrode 7 and several power device electrodes are all located above the two-dimensional electron gas channel. It can be understood that the bottom of each electrode can be located on the surface of the two-dimensional electron gas structure 1, or can extend to the inside of the two-dimensional electron gas structure 1 and be located at any position above the two-dimensional electron gas channel. Exemplarily, the bottoms of the cathode 4, the first ohmic contact electrode 6, the second ohmic contact electrode 7 and some power device electrodes extend to the inside of the two-dimensional electron gas structure 1 and are located above the two-dimensional electron gas channel, and the bottoms of the anode 5 and the remaining power device electrodes are located on the surface of the two-dimensional electron gas structure 1.

[0055] Specifically, interconnecting metal wires are disposed above the anode 5 and the first ohmic contact electrode 6 to achieve connection with an external circuit.

[0056] In this embodiment, an anode, a cathode, a first ohmic contact electrode, a second ohmic contact electrode and a plurality of power device electrodes are arranged on the two-dimensional electron gas structure, and the cathode, the second ohmic contact electrode and the voltage control electrode of the power device are connected in parallel. By utilizing the characteristic that the temperature rise rate of the temperature sensor diode is higher than the temperature rise rate of the ohmic contact resistance, when the junction temperature is low, the voltage of the voltage control electrode in the power device is adjusted to be greater than the threshold voltage of the power device, so that the power device works normally. After the junction temperature rises to the critical temperature, the voltage division of the second ohmic contact electrode, i.e., the voltage of the voltage control electrode, is pulled down to be less than the threshold voltage of the power device, thereby shutting down the device and stopping working, thereby protecting the power device. When the junction temperature drops below the critical temperature, the voltage of the voltage control electrode is pulled up to a value greater than the threshold voltage of the power device, the power device is turned on again, and the power chip resumes normal operation. Therefore, the GaN intelligent power chip integrates the power device with the ohmic contact electrode and the diode temperature sensor on the same epitaxial wafer. The temperature sensor can quickly sense the junction temperature of the HEMT device and respond quickly. The shutdown operation can be performed when the junction temperature is higher than the critical voltage, protecting the device in time and preventing device damage caused by untimely temperature detection. Compared with traditional board-level integrated circuits, it has the advantages of low parasitic crosstalk, small chip size, high integration, low manufacturing cost, and low power loss.

[0057] In a specific embodiment, the two-dimensional electron gas structure 1 includes a substrate 101 , a nucleation layer 102 , a buffer layer 103 , a channel layer 104 and a barrier layer 105 stacked in sequence from bottom to top, wherein a two-dimensional electron gas channel is formed between the channel layer 104 and the barrier layer 105 .

[0058] Specifically, the substrate 101 is made of P-type (1, 1, 1) crystal orientation silicon material; the nucleation layer 102, the buffer layer 103, the channel layer 104 and the barrier layer 105 are made of AlN material, AlGaN material, GaN material and AlGaN material respectively. A two-dimensional electron gas channel is formed between the GaN channel layer 104 and the AlGaN barrier layer 105; accordingly, the first isolation groove 2 and the second isolation groove 3 separate the two-dimensional electron gas channel, which can extend to the inside of the GaN channel layer 104 or to the surface of the GaN buffer layer 103; the first ohmic contact electrode 6, the second ohmic contact electrode 7 and the cathode 4 are located above the two-dimensional electron gas channel, which can extend to the inside of the AlGaN barrier layer 105 or to the surface of the GaN channel layer 104; the anode 5 is located above the two-dimensional electron gas channel, which can be located on the surface of the AlGaN barrier layer 105.

[0059] In a specific embodiment, the power device includes a HEMT power device, and accordingly, the plurality of power device electrodes include a source electrode 8, a drain electrode 9, and a gate electrode 10. The source electrode 8, the gate electrode 10, and the drain electrode 9 are sequentially arranged in the power device region; the gate electrode 10, the cathode 4, and the second ohmic contact electrode 7 are connected in parallel through interconnecting metal wires.

[0060] Furthermore, the source electrode 8, the drain electrode 9 and the gate electrode 10 are all located above the two-dimensional electron gas channel. The source electrode 8 and the drain electrode 9 may extend to the surface of the GaN channel layer 104, or may extend to the inside of the AlGaN barrier layer 105. The gate electrode 10 may be located on the surface of the AlGaN barrier layer 105.

[0061] It should be noted that the power device of the present invention is not limited to HEMT power devices, but may also include other types of power devices, such as GaN GIT devices.

[0062] In a specific embodiment, the GaN smart power chip further includes a partial P-type GaN layer 11 , wherein the partial P-type GaN layer 11 is located on the surface of the barrier layer 105 between the source electrode 8 and the drain electrode 9 , and the gate electrode 10 is located on the partial P-type GaN layer 11 .

[0063] Specifically, the material of the part of the P-type GaN layer 11 includes Mg + Ion-doped GaN, hole doping concentration is 10 17 -10 18 cm -3 , thickness is 60-80nm.

[0064] In a specific embodiment, the GaN smart power chip also includes a passivation layer 12, wherein the passivation layer 12 covers the surface of the first isolation groove 2, the surface of the second isolation groove 3, the surface of the barrier layer 105 and a portion of the surface of the P-type GaN layer 11; the anode 5 overlaps the passivation layer 12.

[0065] Specifically, the passivation layer 12 covers the upper surface of the barrier layer 105, part of the upper surface of the P-type GaN layer 11 except the gate electrode 10, the bottom and side walls of the first isolation groove 2, and the bottom and side walls of the second isolation groove 3. The material includes Si3N4 with a thickness of 100-150nm.

[0066] Furthermore, the electrode structure of the above-mentioned GaN smart power chip can be realized by electrode grooves, including a cathode groove, an anode groove, a first ohmic contact electrode groove, a second ohmic contact electrode groove, a source electrode groove, a drain electrode groove, and a gate electrode groove.

[0067] Specifically, the anode groove is located on one side of the diode temperature sensor region, and the groove depth is equal to the thickness of the passivation layer 12; the anode 5 is a T-shaped anode, and an anode Schottky metal is used. The anode Schottky metal fills the anode groove and overlaps the passivation layer 12 around the anode groove, and the top of the T-shaped anode metal covers the passivation layer 12. The cathode groove is located on the other side of the diode temperature sensor region away from the anode groove, and the groove depth is equal to the sum of the thickness of the passivation layer 12 and the barrier layer 105; the cathode 4 is a rectangular cathode, and a cathode ohmic metal is used. The cathode ohmic metal fills the cathode groove and overlaps the passivation layer 12 around the cathode groove. The first ohmic contact electrode groove and the second ohmic contact electrode groove are located on both lateral sides of the ohmic contact resistance area and are separated by a certain distance. The distance between the two sides is determined by the designed resistance value. The larger the designed resistance value, the larger the distance. The groove depth is equal to the sum of the thickness of the passivation layer 12 and the barrier layer 105. The first ohmic contact electrode 6 adopts ohmic contact metal, which fills the first ohmic contact electrode groove and overlaps the passivation layer 12 around the groove, and is used to connect the ground terminal. The second ohmic contact electrode 7 adopts ohmic contact metal, which fills the second ohmic contact electrode groove and overlaps the passivation layer 12 around the groove, and is connected to the rectangular cathode 4 of the high-sensitivity lateral GaN temperature sensor through an interconnecting metal wire. The source electrode groove and the drain electrode groove are located on both sides of the part of the P-type GaN layer 11 in the power device area in different opposite directions, and the source electrode groove is close to the part of the P-type GaN layer 11, and the drain electrode groove is far away from the part of the P-type GaN layer 11. The groove depth is equal to the sum of the thickness of the passivation layer 12 and the barrier layer 105; the source and drain electrodes are both made of ohmic contact metal, which fills the source electrode groove and the drain electrode groove and overlaps the passivation layer 12 around the groove. The gate groove is located above the part of the P-type GaN layer 11 in the power HEMT table area, and the groove depth is less than the thickness of the passivation layer 12; the gate electrode is a gate Schottky metal, which fills the gate groove and overlaps the passivation layer 12 around the gate groove, and is connected in parallel with the second ohmic contact electrode 7 and the cathode 4 of the temperature sensor diode.

[0068] In this embodiment, the electrode overlaps the passivation layer around the groove, which means that the width of the top of the electrode is greater than the width of the bottom, and the top covers the passivation layer around the groove.

[0069] Exemplarily, the material of the cathode 4 is ohmic metal, including one or more of Ti, Al, Ni, and Au; the material of the anode 5 is Schottky metal, including one or more of TiN, Ti, and Al; the materials of the first ohmic contact electrode 6 and the second ohmic contact electrode 7 both include one or more of Ti, Al, Ni, and Au; the material of the source electrode 8 and the drain electrode 9 is ohmic metal, including one or more of Ti, Al, Ni, and Au; the material of the gate electrode 10 is Schottky metal, including one or more of TiN, Ti, and Al; the material of the interconnecting metal wire includes Cu.

[0070] This embodiment does not limit the thickness of each structural layer of the GaN intelligent power chip, and the thickness can be selected according to the actual performance requirements for the T-type anode GaN Schottky temperature sensor.

[0071] The GaN intelligent power chip of this embodiment connects the gate electrode of the HEMT to the second ohmic contact electrode and the temperature sensor cathode in parallel. In the protection circuit, the temperature sensor diode voltage division and the ohmic contact resistance voltage division are affected differently by temperature, so that the HEMT gate electrode voltage is consistent with the resistance voltage division of the second ohmic contact electrode. The ohmic contact resistance value is designed according to the required threshold voltage, so that the power HEMT can be turned on and work normally at normal temperature. Because the voltage division of the ohmic contact resistance decreases with the increase of temperature, the critical temperature value is designed according to the working conditions of the HEMT, and the proportion of the ohmic contact resistance value in the total branch impedance is adjusted, so that after the junction temperature exceeds the critical temperature, the HEMT gate voltage is reduced to below the threshold voltage, the device is turned off, and stops working; after the junction temperature is cooled to below the critical temperature, the HEMT gate voltage increases to above the threshold voltage, the device is turned on, and resumes working. It can be understood that this embodiment uses the characteristic that the temperature rise rate of the GaN temperature sensor diode is higher than the temperature rise rate of the resistor, and adjusts the device gate voltage to meet the normal working conditions greater than the power HEMT threshold voltage when the junction temperature is low. After the junction temperature rises to the critical temperature, the divided voltage of the second ohmic contact electrode, i.e., the gate voltage of the HEMT, is pulled down to a voltage lower than the threshold voltage of the power HEMT, thereby shutting down the device and stopping working, thus protecting the power device. When the junction temperature drops below the critical temperature, the gate voltage of the HEMT is pulled up to a voltage higher than the threshold voltage of the power HEMT, the power HEMT is turned on again, and the power chip resumes normal operation.

[0072] The GaN smart power chip of this embodiment is integrated with the power HEMT on the same epitaxial wafer. The temperature sensor can quickly sense the junction temperature of the HEMT device and achieve rapid response; it can perform a shutdown operation when the junction temperature is higher than the critical voltage, protecting the device in time and preventing device damage caused by untimely temperature detection.

[0073] Compared with traditional board-level circuit integration, the GaN smart power chip of this embodiment has the advantages of low parasitic crosstalk, small chip size, high integration, low manufacturing cost, and low power loss, and is suitable for industrial production.

[0074] In summary, the GaN smart power chip of this embodiment has the following advantages: 1. It can realize an intelligent protection mechanism that can shut down in time after the operating temperature exceeds the critical temperature, and resume turning on after the operating temperature drops to the critical temperature; 2. It can respond quickly to temperature, and shut down the device and stop working when the junction temperature exceeds the critical temperature; 3. High integration; 4. Low power loss and small parasitic effect.

[0075] Embodiment 2

[0076] Based on Example 1, see Figure 3 and Figure 4a-Figure 4i , Figure 3 A schematic diagram of a process for preparing a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention, Figure 4a-Figure 4i A schematic diagram of a process for preparing a GaN smart power chip with over-temperature protection capability provided by an embodiment of the present invention. The preparation method comprises the following steps:

[0077] S1. Prepare a two-dimensional electron gas structure 1.

[0078] Specifically, the two-dimensional electron gas structure 1 includes a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104 and a barrier layer 105 stacked in sequence from bottom to top, wherein a two-dimensional electron gas channel is formed between the channel layer 104 and the barrier layer 105. The substrate 101 is made of P-type (1, 1, 1) crystal orientation silicon material; the nucleation layer 102, the buffer layer 103, the channel layer 104 and the barrier layer 105 are made of AlN material, AlGaN material, GaN material and AlGaN material, respectively. Figure 4a As shown. For example, the buffer layer 103 is made of Al 0.3 Ga 0.7 N material, the barrier layer 105 is made of Al 0.2 Ga 0.8 N material.

[0079] Step S1 specifically includes:

[0080] S11. A low-temperature AlN nucleation layer is epitaxially grown on the upper surface of the Si material substrate 101 using a metal-organic chemical vapor deposition (MOCVD) technique, and then a high-temperature AlN nucleation layer is epitaxially grown on the upper surface of the low-temperature AlN nucleation layer, and the two together form a nucleation layer 102; the thickness of the low-temperature AlN nucleation layer may be 30 nm, and the thickness of the high-temperature AlN nucleation layer may be 170 nm.

[0081] S12, using trimethylaluminum as an aluminum source, trimethylgallium as a gallium source, and ammonia as an ammonia source, an undoped Al is deposited on the surface of the nucleation layer 102 by MOCVD technology. 0.3 Ga 0.7 N buffer layer 103, the thickness of the buffer layer 103 is 5 μm.

[0082] S13, using trimethylgallium as a gallium source and ammonia as an ammonia source, an undoped GaN channel layer 104 is deposited on the upper surface of the buffer layer 103 by using MOCVD technology, and the thickness of the channel layer 104 is 200 nm.

[0083] S14, using trimethylgallium as a gallium source, trimethylaluminum as an aluminum source, and ammonia as an ammonia source, an undoped Al2O3 layer is deposited on the upper surface of the channel layer 104 by MOCVD technology. 0.2 Ga 0.8 N barrier layer 105; the thickness of the barrier layer 105 is 15 nm.

[0084] Further, after the barrier layer 105 is prepared, a partial P-type GaN layer 11 may be prepared on the upper surface of the barrier layer 105, or the partial P-type GaN layer 11 may not be prepared. The following steps are described by taking the preparation of the partial P-type GaN layer 11 as an example.

[0085] The method for preparing the partial P-type GaN layer 11 includes:

[0086] First, a Mg+-doped GaN layer is epitaxially grown on the upper surface of the barrier layer 105 by using MOCVD technology. The epitaxially grown Mg+-doped GaN layer is annealed at high temperature to form a P-type GaN layer. The thickness of the P-type GaN layer is 60nm-80nm, and the hole doping concentration of the P-type GaN layer is 10 17 -10 18 cm -3 .

[0087] Then, a P-GaN region under the HEMT gate is defined on one side of the surface of the P-GaN layer, a photoresist is spin-coated and exposed and developed, and the P-GaN layer outside the defined P-GaN region is etched downward by plasma (ICP) slow etching until the etching depth extends to the barrier layer 105, thereby forming a partial P-GaN layer 11, as shown in FIG. Figure 4b shown.

[0088] S2, etching the two-dimensional electron gas structure 1 to below the two-dimensional electron gas channel to form a first isolation groove 2 and a second isolation groove 3, so as to isolate the two-dimensional electron gas structure 1 into a power device region, an ohmic contact resistance region and a diode temperature sensor region which are arranged laterally in sequence. Specifically comprising the steps of:

[0089] Specifically, a power device region, an ohmic contact resistance region, and a diode temperature sensor region are defined on the surface of the current sample, and then a photoresist is spin-coated and exposed and developed, and the AlGaN barrier layer 105 and the GaN channel layer 104 outside the defined region are etched downward by plasma (ICP) until the etching depth extends to the buffer layer 103, as shown in FIG. Figure 4c shown.

[0090] S3 , depositing a passivation layer 12 on the surface of the two-dimensional electron gas structure 1 , the surface of the first isolation groove 2 , and the surface of the second isolation groove 3 .

[0091] Specifically, the barrier layer 105 on the surface of the current sample, i.e., the area where the P-type GaN layer is etched away, the upper surface of a portion of the P-type GaN layer 11, the bottom and side of the first isolation groove 2, and the bottom and side of the second isolation groove 3, are deposited using PECVD technology with silane as a silicon source and ammonia as an ammonia source, so that the thickness of the passivation layer 12 reaches 100-150nm. After the passivation layer 12 is deposited, it covers the upper surface of the P-type GaN layer, as shown in FIG. Figure 4d As shown. Exemplarily, the passivation layer 12 may be a Si3N4 passivation layer.

[0092] S4. Prepare a metal electrode above the two-dimensional electron gas channel of the two-dimensional electron gas structure 1 to form a cathode 4 and an anode 5 spaced apart in the diode temperature sensor region, a first ohmic contact electrode 6 and a second ohmic contact electrode 7 spaced apart in the ohmic contact resistance region, and a plurality of power device electrodes distributed in the power device region.

[0093] Exemplarily, taking the power device as a HEMT device, and the plurality of power device electrodes including a source electrode 8, a drain electrode 9 and a gate electrode 10 as an example, step S4 specifically includes the following steps:

[0094] S41 , defining a plurality of ohmic metal electrode regions on the surface of the passivation layer 12 , and etching the passivation layer 12 and the two-dimensional electron gas structure 1 in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves.

[0095] Specifically, first, on the passivation layer 12 on the surface of the current sample, the source electrode groove region, the drain electrode groove region, the cathode groove region, the first ohmic contact electrode groove region, and the second ohmic contact electrode groove region of the HEMT device are defined. Then, photoresist is spin-coated on the surface of the current sample and exposed and developed, and the passivation layer 12 outside the defined region is etched downward by reactive ion etching (RIE) until the etching depth extends to the channel layer 104, and the photoresist is removed, such as Figure 4e shown.

[0096] S42, depositing ohmic metal in a plurality of ohmic metal electrode grooves and performing annealing to form a cathode 4 arranged in the diode temperature sensor area, a first ohmic contact electrode 6 and a second ohmic contact electrode 7 arranged at intervals in the ohmic contact resistance area, and a plurality of ohmic metal electrodes distributed in the power device area.

[0097] Specifically, first, on the surface of the current sample, define the source electrode region and drain electrode region of the HEMT device, the cathode region of the temperature sensor, the first ohmic contact electrode region, and the second ohmic contact electrode region. Then, spin-coat a double layer of photoresist and expose and develop it, and use electron beam evaporation technology to deposit Ti, Al, Ni and Au from bottom to top to prepare ohmic contacts. The thickness of each metal layer is 20nm, 140nm, 50nm and 40nm, respectively. Next, the deposited ohmic metal is subjected to a rapid thermal annealing process to form an ohmic contact electrode; illustratively, the rapid thermal annealing temperature is 850°C and the time is 30 seconds. Finally, remove the photoresist on the surface of the sample to form a cathode 4, a first ohmic contact electrode 6, a second ohmic contact electrode 7, a source electrode 8 and a drain electrode 9, as shown Figure 4f shown.

[0098] S43, defining a plurality of Schottky metal electrode regions on the surface of the passivation layer 12, and etching the passivation layer 12 in the Schottky metal electrode regions to form a plurality of Schottky metal electrode grooves;

[0099] Specifically, first, a gate electrode groove region of the HEMT device and an anode groove region of the temperature sensor diode are defined on the surface of the current sample, wherein the gate electrode groove region is located on the surface of a portion of the P-type GaN layer 11, and the anode groove region is located on the surface of the passivation layer 12 away from the cathode in the temperature sensor diode region. Then, a photoresist is spin-coated and exposed and developed, and the passivation layer 12 defining the gate groove region and the anode groove region is etched downward by reactive ion etching (RIE), and the etching depth extends to the surface of the portion of the P-type GaN layer 11 and the surface of the barrier layer 105, respectively. Finally, the photoresist on the surface of the sample is removed to form a gate electrode groove and an anode groove, such as Figure 4g shown.

[0100] S44, depositing Schottky metal in a plurality of Schottky metal electrode grooves to form an anode 5 spaced apart from the cathode 4 in the diode temperature sensor region and a Schottky electrode in the power device region.

[0101] Specifically, first, define the gate electrode region of the HEMT device and the anode region of the temperature sensor diode. Then, spin-coat a double-layer photoresist and expose and develop it. Use magnetron sputtering technology to sputter TiN, Ti, Al and TiN metals from bottom to top to prepare the Schottky contact gate and T-type anode. The thickness of each metal layer is 30nm, 20nm, 220nm and 30nm respectively. Finally, remove the photoresist on the surface of the sample to form a gate electrode 10 and an anode 5, as shown in FIG. Figure 4h shown.

[0102] S5. Connect the cathode 4 to the second ohmic contact electrode 7 using interconnecting metal wires, and connect the connected electrodes to voltage control electrodes among the electrodes of the power devices.

[0103] Specifically, the cathode 4 of the temperature sensor diode is connected in series with the second ohmic contact electrode 7 through interconnection metal wires, and the gate electrode 10 of the HEMT device, the second ohmic contact electrode 7, and the cathode 4 of the temperature sensor diode are connected in parallel, so as to complete the preparation of the GaN smart power chip with over-temperature protection capability. Figure 4i shown.

[0104] The preparation method of the GaN intelligent power chip of this embodiment is highly consistent with the existing power HEMT preparation process, which can reduce production costs. The designed protection circuit can be horizontally integrated with the power HEMT in the same epitaxial wafer, and no additional process steps are required. The manufactured GaN intelligent power chip can realize an intelligent protection mechanism that is shut down in time after the operating temperature exceeds the critical temperature, and resumes turning on after the operating temperature drops to the critical temperature; it can respond quickly to temperature, and shut down the device and stop working when the junction temperature exceeds the critical temperature; compared with traditional board-level integrated circuits, it has the advantages of low parasitic crosstalk, low power loss, small chip size, high integration, simple process steps, and low manufacturing cost, which is very suitable for industrial production.

[0105] The above contents are further detailed descriptions of the present invention in combination with specific preferred embodiments, and it cannot be determined that the specific implementation of the present invention is limited to these descriptions. For ordinary technicians in the technical field to which the present invention belongs, several simple deductions or substitutions can be made without departing from the concept of the present invention, which should be regarded as falling within the protection scope of the present invention.

Claims

1. A GaN smart power chip with over-temperature protection capability, characterized in that: include: A two-dimensional electron gas structure (1), a first isolation groove (2), a second isolation groove (3), a cathode (4), an anode (5), a first ohmic contact electrode (6), a second ohmic contact electrode (7), and a plurality of power device electrodes, wherein: The first isolation groove (2) and the second isolation groove (3) are arranged in the two-dimensional electron gas structure (1) to isolate the two-dimensional electron gas channel in the two-dimensional electron gas structure (1), so that the two-dimensional electron gas structure (1) forms a power device region, an ohmic contact resistance region and a diode temperature sensor region which are arranged in sequence laterally; The cathode (4) and the anode (5) are arranged at intervals in the diode temperature sensor region and are located above the two-dimensional electron gas channel; the first ohmic contact electrode (6) and the second ohmic contact electrode (7) are arranged at intervals in the ohmic contact resistance region and are located above the two-dimensional electron gas channel; the plurality of power device electrodes are distributed in the power device region and are located above the two-dimensional electron gas channel; The anode (5) is used to input a power supply voltage; the cathode (4) is connected to the second ohmic contact electrode (7) via an interconnecting metal wire, and the interconnected electrode is connected to a voltage control electrode in the plurality of power device electrodes via an interconnecting metal wire; and the first ohmic contact electrode (6) is used to be grounded.

2. The GaN smart power chip with over-temperature protection capability according to claim 1, characterized in that: The two-dimensional electron gas structure (1) comprises a substrate (101), a nucleation layer (102), a buffer layer (103), a channel layer (104) and a barrier layer (105) which are stacked in sequence from bottom to top, wherein: The channel layer (104) and the barrier layer (105) form a two-dimensional electron gas channel.

3. The GaN smart power chip with over-temperature protection capability according to claim 2, characterized in that: The first isolation groove (2) and the second isolation groove (3) both extend to the surface of the buffer layer (103); The first ohmic contact electrode (6), the second ohmic contact electrode (7), and the cathode (4) all extend to the surface of the channel layer (104); The anode (5) is located on the surface of the barrier layer (105).

4. The GaN smart power chip with over-temperature protection capability according to claim 2, characterized in that: The power device comprises a HEMT power device, and accordingly, the plurality of power device electrodes comprises a source electrode (8), a drain electrode (9) and a gate electrode (10), wherein: The source electrode (8), the gate electrode (10) and the drain electrode (9) are sequentially arranged at intervals in the power device region; The gate electrode (10), the cathode (4) and the second ohmic contact electrode (7) are connected in parallel via the interconnecting metal wire.

5. The GaN smart power chip with over-temperature protection capability according to claim 4, characterized in that: The source electrode (8) and the drain electrode (9) both extend to the surface of the channel layer (104); The gate electrode (10) is located on the surface of the barrier layer (105).

6. The GaN smart power chip with over-temperature protection capability according to claim 4, characterized in that: It also includes a partial P-type GaN layer (11), wherein: The partial P-type GaN layer (11) is located on the surface of the barrier layer (105) between the source electrode (8) and the drain electrode (9), and the gate electrode (10) is located on the partial P-type GaN layer (11).

7. The GaN smart power chip with over-temperature protection capability according to claim 6, characterized in that: Also included is a passivation layer (12), wherein: The passivation layer (12) covers the surface of the first isolation groove (2), the surface of the second isolation groove (3), the surface of the barrier layer (105), and a portion of the surface of the partial P-type GaN layer (11); The anode (5) overlaps the passivation layer (12).

8. The GaN smart power chip with over-temperature protection capability according to claim 7, characterized in that: The cathode (4) is made of ohmic metal, including one or more of Ti, Al, Ni and Au; The material of the anode (5) is Schottky metal, including one or more of TiN, Ti, and Al; The materials of the first ohmic contact electrode (6) and the second ohmic contact electrode (7) both include one or more of Ti, Al, Ni, and Au; The source electrode (8) and the drain electrode (9) are made of ohmic metal, including one or more of Ti, Al, Ni, and Au; The gate electrode (10) is made of Schottky metal, including one or more of TiN, Ti, and Al; The material of the interconnection metal line includes Cu; The material of the partial P-type GaN layer (11) includes Mg + Ion-doped GaN, hole doping concentration is 10 17 -10 18 cm -3 , thickness is 60-80nm; The material of the passivation layer (12) includes Si3N4 and has a thickness of 100-150nm.

9. A method for preparing a GaN smart power chip with over-temperature protection capability, characterized in that: Includes steps: S1. preparing a two-dimensional electron gas structure (1); S2, etching the two-dimensional electron gas structure (1) to below the two-dimensional electron gas channel to form a first isolation groove (2) and a second isolation groove (3), so as to isolate the two-dimensional electron gas structure (1) into a power device region, an ohmic contact resistance region and a diode temperature sensor region which are sequentially arranged laterally; S3, depositing a passivation layer (12) on the surface of the two-dimensional electron gas structure (1), the surface of the first isolation groove (2), and the surface of the second isolation groove (3); S4, preparing a metal electrode above the two-dimensional electron gas channel of the two-dimensional electron gas structure (1), forming a cathode (4) and an anode (5) arranged at intervals in the diode temperature sensor region, a first ohmic contact electrode (6) and a second ohmic contact electrode (7) arranged at intervals in the ohmic contact resistance region, and a plurality of power device electrodes distributed in the power device region, wherein the anode (5) is used to input a power supply voltage, and the first ohmic contact electrode (6) is used to be grounded; S5. Use interconnecting metal wires to connect the cathode (4) to the second ohmic contact electrode (7), and connect the connected electrodes to voltage control electrodes among the plurality of power device electrodes.

10. The method for preparing a GaN smart power chip with over-temperature protection capability according to claim 9, characterized in that: Step S4 includes: S41, defining a plurality of ohmic metal electrode regions on the surface of the passivation layer (12), and etching the passivation layer (12) and the two-dimensional electron gas structure (1) in the ohmic metal electrode regions to form a plurality of ohmic metal electrode grooves; S42, depositing ohmic metal in the plurality of ohmic metal electrode grooves and performing annealing to form a cathode (4) arranged in the diode temperature sensor region, a first ohmic contact electrode (6) and a second ohmic contact electrode (7) arranged at intervals in the ohmic contact resistor region, and a plurality of ohmic metal electrodes distributed in the power device region; S43, defining a plurality of Schottky metal electrode regions on the surface of the passivation layer (12), and etching the passivation layer (12) in the Schottky metal electrode regions to form a plurality of Schottky metal electrode grooves; S44, depositing Schottky metal in the plurality of Schottky metal electrode grooves to form an anode (5) spaced apart from the cathode (4) in the diode temperature sensor region and a Schottky electrode in the power device region.

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