Semiconductor device and method for manufacturing the same

Abstract

The present invention discloses a semiconductor device and a manufacturing method thereof, comprising: a substrate, and a silicon carbide layer and a gate structure sequentially located on the substrate; the gate structure comprises: a silicon oxide layer, a gate electrode and a protective layer, the silicon oxide layer is arranged between the gate electrode and the silicon carbide layer, and the protective layer wraps the surface and side of the gate electrode away from the substrate; a metal electrode is arranged on the area of ​​the silicon carbide layer not covered by the gate structure, and the metal electrode forms an ohmic contact with the silicon carbide layer. Among them, the protective layer located on the side of the gate electrode overlaps with the orthographic projection of the silicon oxide layer on the substrate; in the cross section of the silicon oxide layer, the edge of the side away from the substrate has a first width, and the edge of the side facing the substrate has a second width, and the first width is smaller than the second width, so the damage caused by etching to the silicon oxide layer between the gate electrode and the silicon carbide layer can be effectively reduced, the risk of gate electrode leakage is reduced, and the performance and reliability of the semiconductor device are improved.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and in particular to a semiconductor device and a manufacturing method thereof. Background Art

[0002] In the process of manufacturing semiconductor devices, the silicon oxide layer between the gate electrode and the silicon carbide layer is easily damaged by etching, which increases the risk of gate electrode leakage and reduces the performance and reliability of the semiconductor device. Therefore, how to reduce the damage of the silicon oxide layer between the gate electrode and the silicon carbide layer to improve the performance and reliability of the semiconductor device has become a technical problem to be solved in this field. Summary of the invention

[0003] An embodiment of the present invention provides a semiconductor device and a manufacturing method thereof, which are used to reduce damage to a silicon oxide layer between a gate electrode and a silicon carbide layer, thereby improving the performance and reliability of the semiconductor device.

[0004] In a first aspect, an embodiment of the present invention provides a semiconductor device, comprising: a substrate, and a silicon carbide layer and a gate structure sequentially located on the substrate;

[0005] The gate structure comprises: a silicon oxide layer, a gate electrode and a protective layer, wherein the silicon oxide layer is arranged between the gate electrode and the silicon carbide layer, and the protective layer wraps the surface and side of the gate electrode away from the substrate; the protective layer located on the side of the gate electrode overlaps with the orthographic projection of the silicon oxide layer on the substrate;

[0006] A metal electrode is arranged on the area of ​​the silicon carbide layer not covered by the gate structure, and the metal electrode forms an ohmic contact with the silicon carbide layer; in a cross-section of the silicon oxide layer parallel to a reference plane, an edge on a side facing away from the substrate has a first width, and an edge on a side facing the substrate has a second width, the first width is smaller than the second width, and the reference plane is perpendicular to the substrate surface and parallel to the arrangement direction of the metal electrode and the gate structure.

[0007] In a second aspect, an embodiment of the present invention provides a method for manufacturing a semiconductor device, comprising:

[0008] forming a silicon carbide layer and a silicon oxide layer in sequence on the substrate;

[0009] forming a gate electrode on the silicon oxide layer;

[0010] A protective layer is formed to wrap the gate electrode and expose the silicon oxide layer, and under the same etching conditions, the etching rates of the protective layer and the silicon oxide layer are different; the gate structure comprises: a silicon oxide layer, a gate electrode and a protective layer, and the protective layer located on the side of the gate electrode overlaps with the orthographic projection of the silicon oxide layer on the substrate;

[0011] The exposed silicon oxide layer is etched to reduce the thickness of the exposed silicon oxide layer, and the thickness of the exposed silicon oxide layer after the reduction is greater than 0; and the exposed silicon oxide layer after the reduction is etched by a Siconi process to expose the silicon carbide layer and retain the protective layer;

[0012] A metal electrode is formed on an area of ​​the silicon carbide layer not covered by the gate structure, and the metal electrode forms an ohmic contact with the silicon carbide layer; in a cross section of the silicon oxide layer parallel to a reference plane, an edge on a side facing away from the substrate has a first width, and an edge on a side facing the substrate has a second width, the first width is smaller than the second width, and the reference plane is perpendicular to the substrate surface and parallel to the arrangement direction of the metal electrode and the gate structure.

[0013] The beneficial effects of the present invention are as follows:

[0014] A semiconductor device and a method for manufacturing the same provided by an embodiment of the present invention include: a substrate, and a silicon carbide layer and a gate structure sequentially located on the substrate; the gate structure includes: a silicon oxide layer, a gate electrode and a protective layer, the silicon oxide layer is arranged between the gate electrode and the silicon carbide layer, and the protective layer wraps the surface and side of the gate electrode facing away from the substrate; a metal electrode is arranged on the area of ​​the silicon carbide layer not covered by the gate structure, and the metal electrode forms an ohmic contact with the silicon carbide layer. Among them, the protective layer located on the side of the gate electrode overlaps with the positive projection of the silicon oxide layer on the substrate; the reference plane is perpendicular to the substrate surface and parallel to the arrangement direction of the metal electrode and the gate structure, and in the cross-section of the silicon oxide layer parallel to the reference plane, the edge of the side facing away from the substrate has a first width, and the edge of the side facing the substrate has a second width, and the first width is smaller than the second width, so the damage to the silicon oxide layer between the gate electrode and the silicon carbide layer caused by etching can be effectively reduced, the risk of gate electrode leakage is reduced, and the performance and reliability of the semiconductor device are improved; and, when forming the silicon oxide layer, the Siconi process is adopted, which can effectively reduce the damage to the silicon carbide layer. When the silicon carbide layer forms an ohmic contact with the metal electrode, the damage to the ohmic contact interface can be effectively reduced, and the performance and reliability of the semiconductor device are further improved. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] Figure 1 is a cross-sectional view of a semiconductor device provided in an embodiment of the present invention;

[0016] Figure 2 A partial enlarged view of a gate structure of a semiconductor device provided in an embodiment of the present invention;

[0017] Figure 3 A partial enlarged view of another gate structure of a semiconductor device provided in an embodiment of the present invention;

[0018] Figure 4 A flow chart of a method for manufacturing a semiconductor device provided in an embodiment of the present invention;

[0019] Figure 5 The present invention is a schematic diagram of a manufacturing process of a semiconductor device provided in an embodiment of the present invention. DETAILED DESCRIPTION

[0020] The following will be combined with the accompanying drawings to describe in detail the specific implementation of a semiconductor device and a method for manufacturing the same provided by an embodiment of the present invention. It should be noted that the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present invention.

[0021] An embodiment of the present invention provides a semiconductor device, such as Figure 1 As shown, it includes: a substrate 100, and a silicon carbide layer 200 and a gate structure S sequentially located on the substrate;

[0022] The gate structure S includes: a silicon oxide layer 300, a gate electrode 400 and a protective layer 500, wherein the silicon oxide layer 300 is disposed between the gate electrode 400 and the silicon carbide layer 200, and the protective layer 500 wraps the surface and side surface of the gate electrode 400 away from the substrate 100; the protective layer 500 located on the side surface of the gate electrode 400 overlaps with the orthographic projection of the silicon oxide layer 300 on the substrate 100;

[0023] A metal electrode 600 is disposed on the area of ​​the silicon carbide layer 200 that is not covered by the gate structure S, and the metal electrode 600 forms an ohmic contact with the silicon carbide layer 200; in a cross section of the silicon oxide layer 300 parallel to the reference plane, an edge of a side facing away from the substrate 100 has a first width d1, and an edge of a side of the silicon oxide layer 300 facing the substrate 100 has a second width d2, the first width d1 is smaller than the second width d2, and the reference plane is perpendicular to the surface of the substrate 100 and parallel to the arrangement direction of the metal electrode 600 and the gate structure S, that is, the reference plane is Figure 1 The plane formed by the x-direction and the z-direction.

[0024] In this way, since the protective layer located on the side of the gate electrode overlaps with the orthographic projection of the silicon oxide layer on the substrate, the silicon oxide layer is less damaged, thereby reducing the leakage of the gate electrode and improving the performance and reliability of the semiconductor device.

[0025] It should be understood that the semiconductor device provided in the embodiment of the present invention may be, but is not limited to, a metal oxide semiconductor field effect transistor (i.e., MOSFET) or an insulated gate bipolar transistor (i.e., IGBT), etc. As long as the semiconductor device involves ohmic contact and needs to reduce the interface damage of the ohmic contact, it belongs to the protection scope of the embodiment of the present application. The following description is made by taking the metal oxide semiconductor field effect transistor as an example.

[0026] like Figure 1 As shown, when the semiconductor device is a metal oxide semiconductor field effect transistor, the surface of the silicon carbide layer 200 away from the substrate 100 also includes: a P-doped region 201, an N+ doped region 202, a P+ doped region 203, and an N-doped region 204, wherein the arrangement of the P-doped region 201, the N+ doped region 202, the P+ doped region 203, and the N-doped region 204 can be designed according to actual needs and is not specifically limited herein.

[0027] Among them, Figure 1 As shown, the structure in the region X between the dotted lines can be regarded as: the structure of the minimum repeating unit of the metal oxide semiconductor field effect transistor, and the structure included in the region X can be repeatedly extended to both sides.

[0028] Alternatively, if Figure 1 As shown, the side M of the silicon oxide layer 300 in contact with the metal electrode 600 is an inclined surface; or Figure 2 As shown, Figure 2 The gate structure of the semiconductor device is shown, and the side surface M of the silicon oxide layer 300 in contact with the metal electrode has a step.

[0029] The side of the silicon oxide layer in contact with the metal electrode is an inclined surface, or the side of the silicon oxide layer in contact with the metal electrode has a step, which can be formed by a multi-step etching method. In this way, through multi-step etching, the side of the silicon oxide layer in contact with the metal electrode forms an inclined surface or has a step, which reduces the damage to the silicon oxide layer, reduces the leakage of the semiconductor device, and improves the performance and reliability of the semiconductor device.

[0030] Alternatively, if Figure 2As shown, the step on the side of the silicon oxide layer 300 in contact with the metal electrode is a first-level step, wherein the first-level step can be formed by a two-step etching method to reduce the etching steps. In this way, the process complexity of the semiconductor device can be reduced, while also reducing the damage to the silicon oxide layer, and improving the performance and reliability of the semiconductor device. Of course, the step on the side of the silicon oxide layer in contact with the metal electrode is not limited to a first-level step, but can also be a second-level step, a third-level step or more steps, which can be set according to actual needs and is not limited here.

[0031] Optionally, the surface of the silicon carbide layer not covered by the gate structure contains hydrogen and fluorine elements. In this way, the hydrogen and fluorine elements fill the holes and defects on the surface of the silicon carbide layer when on the surface of the silicon carbide layer to passivate the defects on the surface of the silicon carbide layer, thereby reducing the interface defects of the ohmic contact, improving the ohmic contact, and improving the performance and reliability of the semiconductor device.

[0032] Alternatively, if Figure 3 As shown, Figure 3 is a partial enlarged view of a semiconductor device. The material of the silicon oxide layer 300 may include, but is not limited to, silicon oxide; the material of the protective layer 500 may include, but is not limited to, silicon nitride, aluminum oxide, a stacked arrangement of silicon oxide and silicon nitride, a stacked arrangement of silicon oxide and silicon oxynitride, and a stacked arrangement of silicon oxide and aluminum oxide. Figure 3 As shown in (b), the silicon oxide in the protection layer 500 is located on the side of the silicon nitride, silicon oxynitride or aluminum oxide away from the gate electrode 400.

[0033] In this way, multiple film layers can be stacked to form a protective layer, thereby improving the protective effect of the protective layer on the gate electrode and preventing the gate electrode from being damaged during the etching process. The specific structural setting of the protective layer can be designed according to actual needs to meet the needs of different application scenarios and improve the flexibility of the design.

[0034] Optionally, the gate structure further includes an oxide layer, which is disposed between the gate electrode and the protective layer. In this way, the oxide layer can further protect the gate electrode, thereby preventing the gate electrode from being damaged during the etching process, thereby improving the reliability of the semiconductor device.

[0035] Optionally, the thickness of the oxide layer can be set to to In this way, the thickness of the oxide layer is set within a suitable range, which reduces the difficulty of manufacturing and protects the gate electrode, thereby improving the reliability of the semiconductor device and improving the manufacturing efficiency of the semiconductor device.

[0036] The embodiment of the present invention provides a method for manufacturing a semiconductor device, such as Figure 4 As shown, including:

[0037] S401, sequentially forming a silicon carbide layer and a silicon oxide layer on a substrate;

[0038] S402, forming a gate electrode on the silicon oxide layer;

[0039] S403, forming a protective layer that wraps the gate electrode and exposes the silicon oxide layer, wherein under the same etching conditions, the etching rates of the protective layer and the silicon oxide layer are different; the gate structure comprises: a silicon oxide layer, a gate electrode and a protective layer, and the protective layer located on the side of the gate electrode overlaps with the orthographic projection of the silicon oxide layer on the substrate;

[0040] S404, etching the exposed silicon oxide layer to reduce the thickness of the exposed silicon oxide layer, and the thickness of the exposed silicon oxide layer after the reduction is greater than 0; then using the Siconi process to etch the exposed silicon oxide layer after the reduction to expose the silicon carbide layer, and retain the protective layer;

[0041] Among them, the siconi process is a pre-cleaning process that can remove the silicon dioxide film at a low-intensity, low-rate chemical etching rate. The specific etching process can include two steps: Step 1, remote plasma etching using NF3 and NH3, the reaction that occurs is: NF3+NH3→NH4F+NH4F·HF, NH4F / NH4F·HF+SiO2→(NH4)2SiF6(s)+H2O; Step 2, in-situ annealing, the reaction that occurs is: (NH4)2SiF6(s)→SiF4(g)+NH3(g)+HF(g), and the above two steps are completed in the same chamber. Therefore, when the siconi process is used to etch the silicon oxide layer, a two-step reaction is required, and the reaction rate is slow, so the etching rate is also slow and easy to control, thereby reducing the damage to the silicon carbide layer during etching.

[0042] S405. Form a metal electrode on an area of ​​the silicon carbide layer that is not covered by the gate structure, and form an ohmic contact between the metal electrode and the silicon carbide layer; in a cross section of the silicon oxide layer parallel to a reference plane, an edge on a side facing away from the substrate has a first width, and an edge on a side facing the substrate has a second width, the first width is smaller than the second width, and the reference plane is perpendicular to the substrate surface and parallel to an arrangement direction of the metal electrode and the gate structure.

[0043] Thus, since the etching rate is low when the Siconi process is used for etching, the damage to the silicon oxide layer between the gate electrode and the silicon carbide layer caused by etching can be effectively reduced, the risk of gate electrode leakage is reduced, and the performance and reliability of the semiconductor device are improved; in addition, the Siconi process can also effectively reduce the damage to the silicon carbide layer, and then when the silicon carbide layer forms an ohmic contact with the metal electrode, the damage to the ohmic contact interface can be effectively reduced, thereby improving the performance and reliability of the semiconductor device. Moreover, by first reducing the thickness of the exposed silicon oxide layer and then etching with the Siconi process, the etching efficiency of the silicon oxide layer can be improved, thereby improving the manufacturing efficiency of semiconductor devices.

[0044] Optionally, in the above step S404, etching the exposed silicon oxide layer to reduce the thickness of the exposed silicon oxide layer may include: using dry etching or wet etching to reduce the thickness of the exposed silicon oxide layer. The dry etching and wet etching may be performed using processes well known to those skilled in the art and are not limited here.

[0045] In this way, by using dry etching or wet etching to reduce the thickness of the exposed silicon oxide layer, the silicon oxide layer to be etched in the subsequent Siconi process etching is thinner, thereby improving the etching efficiency and further improving the manufacturing efficiency of semiconductor devices.

[0046] Optionally, the thickness of the exposed silicon oxide layer after cutting can be to In this way, it is possible to avoid etching the silicon carbide layer due to the remaining silicon oxide layer being too thin, and it is also possible to avoid the etching time required using the Siconi process being too long due to the remaining silicon oxide layer being too thick. Therefore, controlling the thickness of the remaining silicon oxide layer within an appropriate range can not only improve the manufacturing efficiency of semiconductor devices, but also reduce damage to the ohmic contact interface.

[0047] Optionally, after etching the exposed silicon oxide layer after cutting using the Siconi process, the surface of the exposed silicon carbide layer contains hydrogen and fluorine elements, and the atomic percentage content of hydrogen in the surface of the silicon carbide layer is 0.5% to 1.5%, and the atomic percentage content of fluorine in the surface of the silicon carbide layer is 0.5% to 1.5%.

[0048] The Siconi process uses NF3 and NH3 for remote plasma etching, which will leave hydrogen and fluorine elements on the surface of the silicon carbide layer. When hydrogen and fluorine elements are on the surface of the silicon carbide layer, they will fill the holes and defects on the surface of the silicon carbide layer to passivate the defects on the surface of the silicon carbide layer. In addition, based on the etching characteristics of the Siconi process, the depth of hydrogen and fluorine elements entering the silicon carbide layer is generally to Therefore, hydrogen or fluorine elements basically play a role on the surface of the silicon carbide layer to reduce defects on the surface of the silicon carbide layer, thereby further reducing interface defects of ohmic contact and further improving the performance and reliability of semiconductor devices.

[0049] Optionally, a Siconi process is used to etch the exposed silicon oxide layer after the reduction, and a metal electrode is formed on the exposed silicon carbide layer, including:

[0050] When the vacuum reaction equipment comprises: a vacuum etching chamber, a vacuum coating chamber, and a vacuum processing chamber, and a first vacuum transfer chamber is provided between the vacuum etching chamber and the vacuum coating chamber, and a second vacuum transfer chamber is provided between the vacuum coating chamber and the vacuum processing chamber:

[0051] In a vacuum etching chamber, the exposed silicon oxide layer is etched by using a Siconi process to obtain a first processed part;

[0052] The first processed part is transferred to the vacuum coating chamber through the first vacuum transfer chamber, and a metal layer is formed on the surface of the first processed part, wherein the metal layer covers the exposed silicon carbide layer and the protective layer, thereby obtaining a second processed part;

[0053] Transferring the second processing component to the vacuum processing chamber through the second vacuum transfer chamber, and performing a heat treatment on the second processing component so that the metal layer covering the exposed silicon carbide layer forms an ohmic contact with the silicon carbide layer;

[0054] The metal layer is etched so that the metal layer covering the protective layer is etched away and the metal layer covering the silicon carbide layer is retained, and the retained metal layer forms a metal electrode.

[0055] In the process of transferring the first processing piece to the vacuum coating chamber through the first vacuum transfer chamber, the first processing piece is always in a vacuum environment and does not contact the external environment, and in the process of transferring the second processing piece to the vacuum processing chamber through the second vacuum transfer chamber, the second processing piece is also always in a vacuum environment and does not contact the external environment. Therefore, the entire process of forming the ohmic contact is completed in a vacuum environment, avoiding contact with oxygen in the air, avoiding oxidation of the ohmic contact interface, eliminating the problem of ohmic contact failure due to oxidation, and improving the reliability of the ohmic contact and the performance of the semiconductor device.

[0056] Furthermore, the material of the metal electrode may include but is not limited to other metal materials such as nickel, aluminum, copper, gold, titanium, etc., and may be specifically selected based on factors such as the material of the silicon carbide layer, and is not specifically limited here.

[0057] Optionally, combined Figure 1The structure shown in the figure, the manufacturing method further includes: before forming the protective layer 500, using a thermal oxidation process, forming an oxide layer 700 on the surface of the gate electrode 400 away from the silicon carbide layer 200 and the side of the gate electrode 400. Before forming the protective layer 500, the silicon oxide layer 300 has not been etched, the gate electrode 400 is arranged on the silicon oxide layer 300, and no other film layer is arranged on the surface and side of the gate electrode 400 away from the substrate 100. At this time, through the thermal oxidation process, the oxide layer 700 can be formed only on the surface and side of the gate electrode 400 away from the substrate 100, and other positions will not be oxidized due to the presence of the silicon oxide layer 300.

[0058] In this way, an oxide layer can be formed on the surface and side of the gate electrode through a simple process, reducing the difficulty of manufacturing semiconductor devices; and the oxide layer can eliminate the damage to the surface and side of the gate electrode caused by etching, thereby improving the stability of the semiconductor device.

[0059] Furthermore, the thickness of the oxide layer can be to In this way, it can be avoided that the damage caused by etching cannot be effectively improved due to the oxide layer being too thin, and it can also be avoided that the thermal oxidation time is too long due to the oxide layer being too thick, so that the thickness of the oxide layer can be set within an appropriate range, which can not only improve the stability of the semiconductor device, but also improve the manufacturing efficiency of the semiconductor device.

[0060] Optionally, when the oxide layer and the silicon oxide layer are made of the same material, the oxide layer is located between the gate electrode and the protective layer. In this way, when etching the silicon oxide layer, the protective layer will protect the oxide layer and the gate electrode at the same time, avoiding etching the oxide layer when etching the silicon oxide layer, thereby avoiding damage to the gate electrode, ensuring that the structure of the oxide layer and the gate electrode is intact, improving the yield of semiconductor device manufacturing, and also improving the performance of the manufactured semiconductor device.

[0061] Of course, the oxide layer and the silicon oxide layer may be made of different materials. In this case, the oxide layer may be arranged between the gate electrode and the protective layer, so that the oxide layer and the gate electrode are effectively protected by the protective layer.

[0062] Optionally, forming the protective layer includes:

[0063] Depositing a dielectric layer on the substrate with the gate electrode formed thereon, wherein the dielectric layer wraps the gate electrode and covers the silicon oxide layer exposed by the gate electrode;

[0064] The dielectric layer is etched by using a plasma etching process, so that the dielectric layer wrapping the gate electrode is retained, and the dielectric layer covering the exposed silicon oxide layer is etched away to form a protective layer.

[0065] The dielectric layer may be, but is not limited to, any of the silicon nitride, aluminum oxide, stacked silicon oxide and silicon nitride, stacked silicon oxide and silicon oxynitride, and stacked silicon oxide and aluminum oxide as described above. Thus, by etching the dielectric layer covering the exposed silicon oxide layer, the dielectric layer wrapping the gate electrode is retained, thereby forming a protective layer to protect the gate electrode and the oxide layer, thereby preventing the gate electrode and the oxide layer from being damaged during the etching process.

[0066] The following will explain the method for manufacturing the semiconductor device provided by the embodiment of the present invention in conjunction with a specific embodiment, taking the semiconductor device as a metal oxide semiconductor field effect transistor.

[0067] Combination Figure 5 As shown, the specific production process may include:

[0068] S1, such as Figure 5 As shown in (a), a silicon carbide layer is formed on a substrate by epitaxial technology, wherein the size of the substrate can be but is not limited to 4 inches, 6 inches, 8 inches or other sizes, which can be selected according to actual needs and are not specifically limited here.

[0069] S2, such as Figure 5 As shown in (b), a P-doped region 201, an N+ doped region 202, a P+ doped region 203, and an N-doped region 204 are respectively formed on the surface of the silicon carbide layer facing away from the substrate, wherein the N+ doped region 202 and the P+ doped region 203 are located in the P-doped region 201, and the P+ doped region 203 is located between two adjacent N+ doped regions 202, and the N-doped region 204 is located between two adjacent P-doped regions 201.

[0070] The specific process of forming the P-doped region may include: first, cleaning the surface of the silicon carbide layer; then, forming a first mask layer with a predetermined pattern on the surface of the silicon carbide layer away from the substrate; and using an ion implantation method to implant aluminum ions into the area exposed by the first mask layer, thereby forming a P-doped region.

[0071] Wherein, forming a first mask layer having a predetermined pattern may specifically include:

[0072] Silicon nitride is deposited on the surface of the silicon carbide layer and used as an etching barrier layer; a layer of silicon oxide is produced on the surface of the etching barrier layer and used as a first mask layer by a PECVD (Plasma Enhanced Chemical Vapor Deposition) method; a photoresist is formed on the surface of the first mask layer, and the photoresist is patterned to obtain a photoresist with a predetermined pattern; the area exposed by the photoresist is etched to transfer the predetermined pattern to the first mask layer, so as to form a first mask layer with a predetermined pattern.

[0073] The specific process of forming the N+ doped region may include: first, cleaning the surface of the structure forming the P- doped region; then, forming a second mask layer with a predetermined pattern in a manner similar to the formation of the first mask layer; and using ion implantation to implant nitrogen ions into the exposed area of ​​the second mask layer, thereby forming an N+ doped region.

[0074] The specific process of forming the P+ doped region may include: first, cleaning the surface of the structure forming the N+ doped region; then, using a method similar to forming the first mask layer, using polysilicon to form a third mask layer with a predetermined pattern; using ion implantation to inject aluminum ions into the exposed area of ​​the third mask layer, thereby forming a P+ doped region.

[0075] The specific process of forming the N-doped region may include: first, cleaning the surface of the structure forming the P+ doped region; then, forming a fourth mask layer having a predetermined pattern in a manner similar to the formation of the first mask layer; and using an ion implantation method, implanting nitrogen ions into the region exposed by the fourth mask layer, thereby forming the N-doped region. Of course, the N-doped region may also be formed before forming the P-doped region, which is not limited here.

[0076] Among them, the first to third mask layers may not be removed immediately after each ion implantation, but may be removed uniformly after the ion implantation is completed using the fourth mask layer. This can simplify the process. Of course, the corresponding mask layers may also be removed after each ion implantation, which is not limited here.

[0077] In addition, after forming the P-doped region, the N+ doped region, the P+ doped region, and the N-doped region, each of the doped regions needs to be activated annealed. The specific process of the activation annealing may include: first cleaning the surface of the silicon carbide layer, then depositing a carbon film on the surface of the side of the silicon carbide layer away from the substrate, then performing high-temperature annealing, and finally removing the carbon film. The carbon film can prevent the precipitation of carbon in the silicon carbide layer during high-temperature annealing, thereby protecting the silicon carbide layer.

[0078] S3, such as Figure 5As shown in (c), a silicon oxide layer 300 and a gate electrode are sequentially formed on the surface of the silicon carbide layer facing away from the substrate.

[0079] The manufacturing process of the silicon oxide layer and the gate electrode may include: first, cleaning the surface of the silicon carbide layer; then, using a thermal oxidation process to form a whole layer of silicon oxide layer on the surface of the silicon carbide layer away from the substrate; then, using an LPCVD (Low Pressure Chemical Vapor Deposition) process to form a whole layer of polycrystalline silicon on the silicon oxide layer, and using a method similar to forming the first mask layer, forming a fifth mask layer with a predetermined pattern; finally, etching the polycrystalline silicon exposed by the fifth mask layer and etching to the silicon oxide layer, so that the polycrystalline silicon that is not etched and retained forms the gate electrode.

[0080] S4, such as Figure 5 As shown in (d), an oxide layer 700 and a protective layer 500 are formed.

[0081] The specific process of forming the oxide layer may include: using a thermal oxidation process to form an oxide layer on the surface and side of the gate electrode facing away from the substrate.

[0082] The specific process of forming the protective layer may include: using a CVD (Chemical Vapor Deposition) process to deposit a whole layer of silicon nitride so that the silicon nitride covers the oxide layer and the silicon oxide layer; then using a plasma etching process to etch the silicon nitride until the silicon oxide is etched; since a groove is formed between two adjacent gate electrodes and the etching rate in the groove is higher than the etching rate in other positions, the silicon nitride in the groove will be etched first, while the silicon nitride in other positions is not completely etched at this time, so a certain thickness of silicon nitride can be retained on the surface and side of the gate electrode facing away from the substrate, while the silicon nitride above the silicon oxide layer is etched, thereby forming a protective layer that wraps the gate electrode and exposes the silicon oxide layer.

[0083] Among them, the process of forming a protective layer is also called the Spacer process, that is: when depositing silicon nitride, the deposition thickness of silicon nitride on the surface of the gate electrode is greater than the deposition thickness of silicon nitride in the groove, and when performing plasma etching, plasma is more likely to gather in the groove, and then the etching speed of silicon nitride in the groove is higher than the etching speed of silicon nitride on the surface of the gate electrode, so the silicon nitride at the bottom of the groove can be completely etched, and a certain thickness of silicon nitride is retained on the surface and side of the gate electrode to form a protective layer. In this way, the Spacer process does not require the production of mask plates or photolithography, which simplifies the production process, improves the production efficiency of semiconductor devices, and reduces production costs.

[0084] S5, such as Figure 5As shown in (e) and (f), the exposed silicon oxide layer 300 is etched.

[0085] The specific process can include the following two steps:

[0086] Step 1: Using a wet etching process or a dry etching process to reduce the thickness of the exposed silicon oxide layer.

[0087] Step 2: In a vacuum etching chamber, a Siconi process is used to etch the exposed silicon oxide layer after the reduction, thereby exposing the silicon carbide layer, and obtaining a first processed component.

[0088] In this way, the silicon oxide layer can be etched through the above two steps, which can not only increase the etching speed but also reduce the damage to the surface of the silicon carbide layer caused by etching, thereby improving the reliability of the ohmic contact when forming the ohmic contact and improving the performance of the semiconductor device.

[0089] S6, such as Figure 5 As shown in (g), a metal electrode 600 is formed.

[0090] The specific process may include: first, transferring the first processed part to the vacuum coating chamber through the first vacuum transfer chamber; then, depositing a metal layer on the surface of the first processed part away from the substrate, the metal layer covering the exposed silicon carbide layer and the protective layer, so as to obtain the second processed part; then, transferring the second processed part to the vacuum processing chamber through the second vacuum transfer chamber, and performing high-temperature annealing, so that the metal layer covering the exposed silicon carbide layer forms an ohmic contact with the silicon carbide layer; finally, through a wet etching process, the metal layer covering the protective layer is etched away, and the metal layer covering the silicon carbide layer is retained, so that the retained metal layer forms a metal electrode.

[0091] It should be understood that after the ohmic contact is formed, the elements in the silicon carbide layer will enter the metal layer in contact with it, while the material of the metal layer at other positions remains unchanged, so that the material of the metal layer forming the ohmic contact is different from the material at other positions, so that when the metal layer is etched, the metal layer at other positions can be etched away, while the metal layer in contact with the silicon carbide layer will remain. Figure 1 and Figure 2 FIG. 4 shows the shape of the side surface M in the silicon oxide layer in contact with the metal electrode. Figure 3 and Figure 5 Not shown in the figure.

[0092] In this way, a semiconductor device can be manufactured through steps S1 to S6, and the semiconductor device manufactured by this manufacturing method has the following advantages:

[0093] 1. By reducing the thickness and then using the siconi process to etch the silicon oxide layer, the side of the silicon oxide layer in contact with the metal electrode is less damaged, the leakage of the gate electrode is reduced, and the performance and reliability of the semiconductor device are improved.

[0094] 2. Reduce the oxidation of the ohmic contact interface, ensure the purity of the ohmic contact, reduce the potential barrier, and improve the performance of semiconductor devices;

[0095] 3. When etching the silicon oxide layer using the Siconi process, the damage to the silicon carbide layer can be reduced, thereby improving the reliability of the ohmic contact when forming the ohmic contact and improving the performance of the semiconductor device;

[0096] 4. The oxide layer can eliminate the damage caused by etching on the surface and sides of the gate electrode, thereby enhancing the stability of the semiconductor device;

[0097] 5. The Spacer process is used when etching the protective layer. There is no need to make a mask layer or photolithography, which simplifies the production process, improves the production efficiency of semiconductor devices, and reduces production costs.

[0098] Obviously, those skilled in the art can make various changes and modifications to the present invention without departing from the spirit and scope of the present invention. Thus, if these modifications and variations of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A semiconductor device, characterized in that: include: A substrate, and a silicon carbide layer and a gate structure sequentially located on the substrate; The gate structure comprises: a silicon oxide layer, a gate electrode and a protective layer, wherein the silicon oxide layer is arranged between the gate electrode and the silicon carbide layer, and the protective layer wraps the surface and side of the gate electrode away from the substrate; the protective layer located on the side of the gate electrode overlaps with the orthographic projection of the silicon oxide layer on the substrate; A metal electrode is disposed on an area of ​​the silicon carbide layer that is not covered by the gate structure, and the metal electrode forms an ohmic contact with the silicon carbide layer; in a cross section of the silicon oxide layer parallel to a reference plane, an edge of a side away from the substrate has a first width, and an edge of a side of the silicon oxide layer facing the substrate has a second width, the first width is smaller than the second width, and the reference plane is perpendicular to the substrate surface and parallel to the arrangement direction of the metal electrode and the gate structure; Wherein, the side surface of the silicon oxide layer in contact with the metal electrode has a step.

2. The semiconductor device according to claim 1, wherein The step is a single-stage step.

3. The semiconductor device according to claim 1, wherein The surface of the silicon carbide layer not covered by the gate structure contains hydrogen and fluorine elements.

4. The semiconductor device according to claim 1, wherein The protective layer is made of materials including silicon nitride, aluminum oxide, a stacked arrangement of the silicon oxide and the silicon nitride, a stacked arrangement of the silicon oxide and silicon oxynitride, and any one of a stacked arrangement of the silicon oxide and the aluminum oxide, and the silicon oxide in the protective layer is located on the side of the silicon nitride, the silicon oxynitride or the aluminum oxide away from the gate electrode.

5. The semiconductor device according to any one of claims 1 to 4, characterized in that: The gate structure further includes an oxide layer, and the oxide layer is arranged between the gate electrode and the protection layer.

6. The semiconductor device according to claim 5, characterized in that The thickness of the oxide layer is to 7. A method for manufacturing a semiconductor device, characterized in that: include: forming a silicon carbide layer and a silicon oxide layer in sequence on the substrate; forming a gate electrode on the silicon oxide layer; forming a protective layer that wraps the gate electrode and exposes the silicon oxide layer, wherein under the same etching conditions, the etching rates of the protective layer and the silicon oxide layer are different; The gate structure comprises: a silicon oxide layer, a gate electrode and a protective layer, wherein the protective layer located on the side of the gate electrode overlaps with the orthographic projection of the silicon oxide layer on the substrate; The exposed silicon oxide layer is etched to reduce the thickness of the exposed silicon oxide layer, and the thickness of the exposed silicon oxide layer after the reduction is greater than 0; and the exposed silicon oxide layer after the reduction is etched by a Siconi process to expose the silicon carbide layer and retain the protective layer; A metal electrode is formed on an area of ​​the silicon carbide layer not covered by the gate structure, and the metal electrode forms an ohmic contact with the silicon carbide layer; in a cross section of the silicon oxide layer parallel to a reference plane, an edge of a side facing away from the substrate has a first width, and an edge of the silicon oxide layer facing the substrate has a second width, the first width is smaller than the second width, and the reference plane is perpendicular to the substrate surface and parallel to the arrangement direction of the metal electrode and the gate structure; wherein a side of the silicon oxide layer in contact with the metal electrode has a step.

8. The method according to claim 7, characterized in that: The thickness of the exposed silicon oxide layer after cutting is to 9. The production method according to claim 7 or 8, characterized in that: The exposed silicon oxide layer is etched by using a Siconi process, and a metal electrode is formed on the exposed silicon carbide layer, including: When the vacuum reaction equipment comprises: a vacuum etching chamber, a vacuum coating chamber, and a vacuum processing chamber, and a first vacuum transfer chamber is provided between the vacuum etching chamber and the vacuum coating chamber, and a second vacuum transfer chamber is provided between the vacuum coating chamber and the vacuum processing chamber: In the vacuum etching chamber, the exposed silicon oxide layer is etched by the Siconi process to obtain a first processed part; Transferring the first processed part to the vacuum coating chamber through the first vacuum transfer chamber, forming a metal layer on the surface of the first processed part, wherein the metal layer covers the exposed silicon carbide layer and the protective layer, to obtain a second processed part; Transferring the second processing piece into the vacuum processing chamber through the second vacuum transfer chamber, and performing heat treatment on the second processing piece so that the metal layer covering the exposed silicon carbide layer forms an ohmic contact with the silicon carbide layer; The metal layer is etched so that the metal layer covering the protective layer is etched away, and the metal layer covering the silicon carbide layer is retained, and the retained metal layer forms the metal electrode.

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