A circuit to reduce undershoot when switching from main LDO to low power LDO

Abstract

The present invention discloses a circuit for reducing undershoot when a main LDO switches to a low-power LDO, wherein the main LDO and the low-power LDO share the same output, the input end of the main LDO and the first input end of the low-power LDO are connected to the same main reference voltage source, and the second input end of the low-power LDO is connected to the low-power reference voltage source; a first switch and a delay branch are provided between the input connection point of the main LDO and the low-power LDO and the main reference voltage source, and when the main LDO switches to the low-power LDO, the first switch is disconnected and the delay branch is started, so that the main LDO is completely turned off after a preset delay time. The present invention reduces the output undershoot when the main LDO and the low-power LDO share the same output when the normal working mode switches to the low-power working mode by delaying the switch strategy structure and using a relatively small circuit cost.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductor design, and more specifically, relates to a method for reducing output undershoot when a main LDO and a low-power LDO output are shared and the main LDO switches to the low-power LDO when the low-power mode is entered from the normal working mode. Background Art

[0002] The application of LDO is mainly to provide a stable power supply voltage for functional modules. The undershoot of LDO output will cause the module that uses LDO output as power supply voltage to malfunction and fail to meet normal working requirements.

[0003] At present, in most designs, the main LDO and the low-power LDO are two independent modules with two independent feedback loops and output ports. When entering the low-power mode from the working mode, you only need to enable the low-power LDO first and then turn off the main LDO to achieve the switch, and the two outputs do not interfere with each other. There are also some designs that use larger off-chip capacitors at the LDO output to deal with the problem of output undershoot.

[0004] If two independent output ports, the main LDO and the low-power LDO, are used, two independent feedback loops and two independent compensation groups are required, which increases the circuit complexity and the chip area. If an off-chip capacitor is used, a PAD will be added to the chip, which not only increases the area but also increases the ESD risk. Summary of the invention

[0005] In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a circuit for reducing the undershoot when the main LDO switches to the low-power LDO. By delaying the switching strategy structure and utilizing a relatively low circuit cost, the output undershoot when the main LDO and the low-power LDO share the same output and when the normal working mode switches to the low-power working mode is reduced.

[0006] The present invention is achieved through the following technical solutions:

[0007] A circuit for reducing undershoot when a main LDO switches to a low-power LDO, wherein the main LDO and the low-power LDO share the same output, the input end of the main LDO and the first input end of the low-power LDO are connected to the same main reference voltage source, and the second input end of the low-power LDO is connected to the low-power reference voltage source; a first switch and a delay branch are provided between the connection point of the input ends of the main LDO and the low-power LDO and the main reference voltage source, and when the main LDO switches to the low-power LDO, the first switch is disconnected and the delay branch is started, so that the main LDO is completely shut down after a preset delay time.

[0008] As a further technical solution, the main reference voltage output by the main reference voltage source is equal to the low power reference voltage output by the low power reference voltage source in value, and the low power reference voltage exists since power-on.

[0009] As a further technical solution, the main LDO and the low-power LDO are always in working state after the reference voltage is ready, and after entering the normal working mode, the low-power LDO does not work.

[0010] As a further technical solution, the delay branch is arranged between the input terminal connection point of the main LDO and the low-power LDO and the first switch, including a capacitor and a current source connected in parallel, and a second switch is arranged on the current source branch.

[0011] As a further technical solution, when the first switch is opened and the second switch is closed, the discharge time of the main reference voltage at the connection point of the input terminals of the main LDO and the low power LDO is:

[0012]

[0013] Among them, C C Indicates capacitance value, MV ref Indicates the main reference voltage value, I C Represents the current source current.

[0014] As a further technical solution, after the undershoot time is determined, the capacitance value and the current source current are determined according to the undershoot time, and then the discharge time is determined.

[0015] As a further technical solution, the low-power LDO includes an input unit, an N current mirror unit and a P current mirror unit. The input unit is used to obtain multiple currents of the same magnitude. The multiple currents are mirrored in turn by the N current mirror unit and the P current mirror unit and are used to turn on or off the MOS tube.

[0016] Compared with the prior art, the present invention has the following beneficial effects:

[0017] The present invention realizes that when the main LDO switches to the low-power LDO, the first switch is disconnected and the delay branch is started by arranging a first switch and a delay branch between the input terminal connection point of the main LDO and the low-power LDO and the main reference voltage source, so that the main LDO is turned off after a preset delay time, and by setting the delay parameter, it is ensured that the low-power LDO is completely started before the main LDO is completely turned off, thereby achieving the purpose of reducing the undershoot time caused by the switching.

[0018] The present invention can significantly reduce the output undershoot when the main LDO and the low-power LDO share the same output when the normal working mode is switched to the low-power working mode, and achieves considerable performance improvement with a relatively small circuit cost. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 The schematic diagram of the circuit structure for reducing undershoot when the main LDO switches to a low power consumption LDO according to an embodiment of the present invention.

[0020] Figure 2 FIG. 4 is a schematic diagram of a reference voltage according to an embodiment of the present invention.

[0021] Figure 3 A schematic diagram of a switching delay switch structure for eliminating output undershoot when switching between a main LDO and a low-power LDO according to an embodiment of the present invention.

[0022] Figure 4 is a comparison diagram of simulation results according to an embodiment of the present invention, Figure 4 (a) is the simulation result before using the structure of the present invention, Figure 4 (b) is the simulation result after adopting the structure of the present invention. DETAILED DESCRIPTION

[0023] The application of LDO is mainly to provide a stable power supply voltage for functional modules. The undershoot of output voltage will cause abnormal function of the circuit using this voltage as power supply. In severe cases, it will cause the circuit to fail to work and fail to meet normal needs. To this end, the present invention provides a delay structure strategy to solve the problem of output voltage undershoot when the main LDO switches to low power consumption mode when the normal working mode is switched to low power consumption mode with a smaller area cost and without introducing additional risks.

[0024] The following will clearly and completely describe the technical solutions of various embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of the present invention.

[0025] In the description of the present invention, it should be understood that the terms "center", "longitudinal", "lateral", "length", "width", "thickness", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", "clockwise", "counterclockwise" and the like indicate positions or positional relationships based on the positions or positional relationships shown in the accompanying drawings, and are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as limiting the present invention. In addition, the terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the number of technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the present invention, the meaning of "multiple" is two or more, unless otherwise clearly and specifically defined.

[0026] In the description of the present invention, it should be noted that, unless otherwise clearly specified and limited, the terms "installed", "connected", and "connected" should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection, an electrical connection, or mutual communication; it can be a direct connection, or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in the present invention can be understood according to specific circumstances.

[0027] The present invention provides a circuit for reducing undershoot when a main LDO is switched to a low-power LDO, wherein the main LDO and the low-power LDO share the same output, the input end of the main LDO and the first input end of the low-power LDO are connected to the same main reference voltage source, and the second input end of the low-power LDO is connected to the low-power reference voltage source; a first switch and a delay branch are provided between the connection point of the input ends of the main LDO and the low-power LDO and the main reference voltage source, and when the main LDO is switched to the low-power LDO, the first switch is disconnected and the delay branch is started, so that the main LDO is turned off after a preset delay time.

[0028] As attached Figure 1 FIG. 1 is a schematic diagram of the circuit structure of the main LDO and the low-power LDO in the present invention, wherein LPEN is a low-power mode enable signal, LPENB is an inverted signal of LPEN, MVref is a main LDO reference voltage, LPVref is a low-power LDO reference voltage, and MVref=LPVref, with equal values ​​but different sources. The LPVref signal has been present since power-on, and MVref becomes 0 after a delay of T1 after entering the low-power mode, as shown in FIG. Figure 2Shown is a schematic diagram of the reference voltage.

[0029] It should be noted that the equal values ​​of MVref and LPVref can ensure that LPLDO does not work in normal working mode because the LPLDO power tube is turned off due to the input proportional relationship. Different sources of MVref and LPVref can ensure that after MVref is disconnected in low power mode, LPVref provides reference for LPLDO so that LPLDO can work.

[0030] The main LDO and low-power LDO are always in working state after the reference is ready. This setting makes it possible to output normally as long as MVref disconnects LPLDO when low-power switching is performed, without turning on LPLDO again.

[0031] When in normal working mode, LPEN is low, LPENB is high, S1 is closed, Ms is turned on, and the main LDO works normally, and the output Vout = 1.1V; the ratio of the three input tubes in the low-power LDO is 1:1:1, and MVref and LPVref act on the low-power LDO at the same time, resulting in an input tube ratio equivalent to 1:2., and I1 = (I2 + I3) / 2 is obtained. Since MVref = LPVref, I2 = I3, and I1 = I2 = I3 is obtained. After the N current mirror image, I4 = 2I2 = 2I3, I5 = 4I2 = 4I3, after the P current mirror image, I6 = 4I4 = 6I2 = 6I3, and I6>I5. The gate signal is pulled high. At this time, the low-power LDO power stage does not work, that is, the low-power LDO has no output, and Vout = 1.1V is contributed by the main LDO.

[0032] When switching from normal working mode to low power working mode, LPEN is high, LPENB is low, S1 is disconnected, the main LDO stops working, Ms is disconnected, MVre=0, only LPVref is used as the reference voltage of low power LDO, I1=I2, I5=4I4, I6=4I4, I5=I6 is obtained, the gate voltage will not be pulled up, and the low power LDO can work normally, maintaining the output of Vout=1.1V. However, the load capacity of the low power LDO power tube is less than that of the main LDO power tube. Under the same working conditions, when switching from the main LDO to the low power LDO, the external load does not change, but the internal driving capacity changes, causing Vout to undershoot, that is, the current capacity that meets the external load cannot be provided at the moment of switching, so undershoot occurs, as shown in the attached figure. Figure 4 As shown in (a), when the structure of the present invention is not adopted, the undershoot amplitude reaches 480mV, which is 43% of 1.1V, and can only provide an output of 630mV. If a circuit module uses Vout as a power supply, it may cause the module to not work normally or even not work.

[0033] Therefore, the present invention proposes a delay switching strategy to reduce the undershoot amplitude when the main LDO switches to the low-power LDO. As shown in the appendix Figure 3 The delay switching strategy of the present invention is shown. When in the normal working mode, the main LDO works, and MVref provides the reference voltage for the main LDO. S1 is closed and S2 is open. The low-power LDO does not work, but LPVref still inputs normally as the reference voltage of the low-power LDO.

[0034] When switching to the low-power mode, S1 is open and S2 is closed. Since the voltage on the capacitor cannot change suddenly, the voltage at point A is still MVref. Under the action of the current source Ic and Cc, when S1 is open and S2 is closed, the voltage at point A will slowly discharge from MVref to the GND potential, giving a certain buffer time for the startup of the low-power LDO. The discharge time is adjusted according to the undershoot time:

[0035]

[0036] After determining the undershoot time T1, the values of the capacitor and current can be determined, and then the discharge time t can be determined.

[0037] MVref will be pulled down to 0 after a delay of T1 time, giving a certain buffer time for the turn-off of the main LDO. If it is ensured that t < T1, that is, the low-power LDO is fully started before the main LDO is completely turned off, the undershoot time caused by the switching can be reduced. Because within the T1 time, the main LDO has not been completely turned off and can provide a certain load-carrying capacity, and the low-power LDO is being started and will gradually provide a load-carrying capacity. There is an overlap in the working time, providing a buffer time during the switching from the working mode to the low-power mode. Therefore, the undershoot amplitude can be reduced, and the influence of Vout on the subsequent module operation can be reduced.

[0038] According to the simulation results, as shown in the appendix Figure 4 (b), after adopting the present invention, the undershoot is reduced to 980 mV, and the undershoot amplitude is 130 mV, which is 11% of 1.1 V, significantly improving the undershoot effect.

[0039] The delay switching strategy provided by the present invention is that in the normal working mode, S1 is closed and S2 is open, the main LDO works normally, and the low-power LDO does not work; when entering the low-power mode, S1 is open and S2 is closed, the main LDO does not work, and the low-power LDO works. This strategy can significantly reduce the output undershoot when the main LDO and the low-power LDO share the same output and switch from the normal working mode to the low-power working mode, and achieve considerable performance improvement with a small circuit cost.

[0040] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the technical solutions of the embodiments of the present invention.

Claims

1. A circuit to reduce undershoot when the main LDO switches to a low power LDO, wherein: The main LDO and the low-power LDO share the same output, characterized in that the input end of the main LDO and the first input end of the low-power LDO are connected to the same main reference voltage source, and the second input end of the low-power LDO is connected to the low-power reference voltage source; a first switch and a delay branch are provided between the input connection point of the main LDO and the low-power LDO and the main reference voltage source, and when the main LDO switches to the low-power LDO, the first switch is disconnected and the delay branch is started, so that the main LDO is completely turned off after a preset delay time; the main reference voltage output by the main reference voltage source is equal to the low-power reference voltage output by the low-power reference voltage source in terms of value, and combined with the proportional relationship of the multi-channel input current in the low-power LDO, the low-power LDO power tube is turned off in the normal working mode.

2. A circuit for reducing undershoot when a main LDO switches to a low power LDO according to claim 1, characterized in that: The low power consumption reference voltage is always present since power is turned on.

3. A circuit for reducing undershoot when a main LDO switches to a low power LDO according to claim 1, characterized in that: The main LDO and the low power consumption LDO are in working state after the reference voltage is ready, and the low power consumption LDO does not work after entering the normal working mode.

4. A circuit for reducing undershoot when a main LDO switches to a low power LDO according to claim 1, characterized in that: The delay branch is arranged between the input terminal connection point of the main LDO and the low power consumption LDO and the first switch, and comprises a capacitor and a current source connected in parallel. The current source branch is provided with a second switch.

5. A circuit for reducing undershoot when a main LDO switches to a low power LDO according to claim 4, characterized in that: When the first switch is open and the second switch is closed, the discharge time of the main reference voltage at the input connection point of the main LDO and the low-power LDO is: ， in, Indicates the capacitance value, Indicates the main reference voltage value, Represents the current source current.

6. A circuit for reducing undershoot when a main LDO switches to a low power consumption LDO according to claim 5, characterized in that: After the undershoot time is determined, the capacitance value and the current source current are determined according to the undershoot time, and then the discharge time is determined.

7. A circuit for reducing undershoot when a main LDO switches to a low power consumption LDO according to claim 1, characterized in that: The low-power LDO includes an input unit, an N current mirror unit and a P current mirror unit. The input unit is used to obtain multiple currents of the same magnitude. After the multiple currents are mirrored in sequence by the N current mirror unit and the P current mirror unit, the on or off of the MOS tube controlled by the gate voltage in the low-power LDO is controlled to trigger the low-power LDO output or not trigger the low-power LDO output.

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